KR20000039717A - Method for forming contact hole of semiconductor device - Google Patents

Method for forming contact hole of semiconductor device Download PDF

Info

Publication number
KR20000039717A
KR20000039717A KR1019980055129A KR19980055129A KR20000039717A KR 20000039717 A KR20000039717 A KR 20000039717A KR 1019980055129 A KR1019980055129 A KR 1019980055129A KR 19980055129 A KR19980055129 A KR 19980055129A KR 20000039717 A KR20000039717 A KR 20000039717A
Authority
KR
South Korea
Prior art keywords
contact hole
forming
semiconductor device
plasma
insulating layer
Prior art date
Application number
KR1019980055129A
Other languages
Korean (ko)
Other versions
KR100511929B1 (en
Inventor
이성욱
Original Assignee
김영환
현대반도체 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김영환, 현대반도체 주식회사 filed Critical 김영환
Priority to KR10-1998-0055129A priority Critical patent/KR100511929B1/en
Publication of KR20000039717A publication Critical patent/KR20000039717A/en
Application granted granted Critical
Publication of KR100511929B1 publication Critical patent/KR100511929B1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching

Abstract

PURPOSE: A method for forming a contact hole of semiconductor device is provided to be able to make a microscopic contact hole using a power source. CONSTITUTION: An isolation film(20) is stuck on a semiconductor substrate. A photoresist(PR) is applied on the isolation film(20). And the PR is exposed on the light and developed to make an area of the exposed isolation layer(20) lower than 0.32 square meter. A mixed gas of C4F8, CF4, and Ar is made plasma using split power. A polymer is made when the plasma etched the exposed isolation layer(20) and a contact hole is made. The process for making a contact hole is completed by removing the PR pattern.

Description

반도체 장치의 콘택홀 형성방법Contact hole formation method of semiconductor device

본 발명은 반도체 장치의 콘택홀 형성방법에 관한 것으로, 특히 크기가 0.37 m 이상인 콘택홀의 형성을 위해 사용하던 건식식각장비의 스플릿 파워(split power)를 그 값의 변형없이 크기가 0.32 m 이하의 콘택홀 형성을 위한 건식식각장비에 적용하여 장치의 사용효율을 향상시키는데 적당하도록 한 반도체 장치의 콘택홀 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a contact hole in a semiconductor device. m The split power of dry etching equipment used for the formation of the above-mentioned contact hole was 0.32 without changing its value. m The present invention relates to a method for forming a contact hole in a semiconductor device suitable for improving the use efficiency of a device by applying to dry etching equipment for forming the following contact holes.

종래의 반도체 제조공정에서 콘택홀을 형성하기 위해서 콘택홀이 형성될 절연막의 건식식각으로 형성되는 홀의 크기에 따라 사용하는 플라즈마의 농도를 다르게 하였다.In order to form the contact hole in the conventional semiconductor manufacturing process, the concentration of the plasma used is varied according to the size of the hole formed by dry etching of the insulating film on which the contact hole is to be formed.

즉, 형성하고자 하는 홀의 크기가 0.37 m 이상인 경우에는 저농도 플라즈마를 사용하며, 그 전력소스로는 스플릿 파워를 사용한다. 이 스플릿 파워를 이용하여 저농도의 플라즈마를 형성하는 과정은 압력이 높아야 하며, 상기 압력이 높은 경우 입자의 충돌이 발생하여 홀의 측면부가 식각되어 콘택홀의 크기를 예상치보다 크게 형성하게 된다.That is, the size of the hole to be formed is 0.37 m In the above case, low concentration plasma is used, and split power is used as the power source. The process of forming a low concentration of plasma using this split power should be high in pressure, and when the pressure is high, particle collision occurs and the side surface of the hole is etched to form the size of the contact hole larger than expected.

상기와 같은 이유로 콘택홀의 크기가 0.32 m 이하인 것을 절연막에 형성하는데 상기 스플릿 파워를 이용하지 못하였으며, 이와 같은 초미세 패턴을 형성하기 위해서 파워소스로 고밀도 플라즈마(HDP)를 사용하였다.For the same reason as above, the contact hole size is 0.32. m The split power was not used to form the following in the insulating film, and high density plasma (HDP) was used as the power source to form such an ultrafine pattern.

고밀도 플라즈마(HDP)는 압력이 낮은 상태에서도 플라즈마를 형성하여 그 플라즈마 입자간의 충돌이 거의 없으며, 이에 따라 콘택홀의 측면 절연막을 식각하지 않게 되어 원하는 크기의 콘택홀을 산화막에 형성할 수 있게 된다.High density plasma (HDP) forms a plasma even at a low pressure, so that there is almost no collision between the plasma particles. Accordingly, the side insulating film of the contact hole is not etched so that a contact hole having a desired size can be formed in the oxide film.

도1은 일반적인 스플릿 파워장치의 개략적인 구성도로서, 이에 도시한 바와 같이 RF파워를 발생하는 RF발생부(1)와; 상기 RF파워를 스플릿(SPLIT) 파워로 변환하는 스플릿파워 변환부(2)와; 상기 스플릿 파워를 인가받아 플라즈마를 생성하고, 그 플라즈마를 이용하여 절연막을 건식식각하는 챔버(3)로 구성된다.1 is a schematic configuration diagram of a general split power device, and an RF generator 1 for generating RF power as shown therein; A split power converter (2) for converting the RF power into split power; It is composed of a chamber (3) is applied to the split power to generate a plasma, and dry etching the insulating film using the plasma.

상기와 같은 구조의 장치는 상기 설명한 바와 같이 0.32 m 이하의 콘택홀을 형성하는 공정에 사용할 수 없으며, 집적화가 심화될 경우 상기의 장비는 사용할 수 없게 된다.The device of the above structure is 0.32 as described above. m It cannot be used in the process of forming the following contact holes, and if the integration is deepened, the above equipment cannot be used.

상기한 바와 같이 종래 반도체 장치의 콘택홀 형성방법은 절연막에 형성할 콘택홀의 크기에 따라 다른 전력소스를 사용하여, 상대적으로 큰 홀을 형성하던 장비를 집적화가 심화되는 추세에 따라 사용할 수 없는 문제점이 있었다.As described above, the conventional method of forming a contact hole in a semiconductor device may not use a device that forms a relatively large hole by using a different power source depending on the size of the contact hole to be formed in the insulating layer, according to a trend of increasing integration. there was.

이와 같은 문제점을 감안한 본 발명은 종래 사용하던 전력소스를 이용하여 초미세의 콘택홀을 형성할 수 있는 반도체 장치의 콘택홀 형성방법을 제공함에 그 목적이 있다.In view of the above problems, an object of the present invention is to provide a method for forming a contact hole in a semiconductor device capable of forming an ultra-fine contact hole using a conventionally used power source.

도1은 일반적인 스플릿 파워을 이용한 건식식각장비의 개략적인 구조도.1 is a schematic structural diagram of a dry etching apparatus using a typical split power.

도2a 내지 도2c는 본 발명 반도체 장치의 콘택홀 제조공정 수순단면도.2A to 2C are cross-sectional views of a process for manufacturing a contact hole in a semiconductor device of the present invention.

***도면의 주요 부분에 대한 부호의 설명****** Description of the symbols for the main parts of the drawings ***

10:기판 20:절연층10: substrate 20: insulating layer

상기와 같은 목적은 반도체 소자가 형성된 기판의 상부에 절연층을 증착하고, 상기 절연층에 포토레지스트 패턴을 형성하여 상기 절연층의 상부를 0.32 m 이하로 노출시키는 마스크 형성단계와; 플라즈마를 이용한 건식식각으로 상기 노출된 절연층에 콘택홀을 형성하는 건식식각단계와; 상기 포토레지스트 패턴을 제거하는 마스크 제거단계로 이루어지는 반도체 장치의 콘택홀 형성방법에 있어서, 상기 건식식각단계를 스플릿 파워를 이용하여 폴리머를 발생시키는 소스가스를 플라즈마화하여 그 플라즈마로 상기 0.32 m 이하의 크기로 노출된 절연층을 식각하도록 함으로써 달성되는 것으로, 이와 같은 본 발명을 첨부한 도면을 참조하여 상세히 설명하면 다음과 같다.The above object is to deposit an insulating layer on top of the substrate on which the semiconductor device is formed, and to form a photoresist pattern on the insulating layer to form an upper portion of the insulating layer 0.32. m A mask forming step of exposing below; A dry etching step of forming contact holes in the exposed insulating layer by dry etching using plasma; In the method for forming a contact hole of a semiconductor device comprising removing the photoresist pattern, in the dry etching step, a source gas for generating a polymer using a split power is converted into plasma, and the plasma is 0.32. m It is achieved by etching the insulating layer exposed to the following size, it will be described in detail with reference to the accompanying drawings, the present invention as follows.

도2a 내지 도2c는 종래 반도체 장치의 콘택홀 제조공정 수순단면도로서, 이에 도시한 바와 같이 반도체 소자가 형성된 기판(10)의 상부에 절연막(2)을 증착하고, 상기 절연막(2)의 상부전면에 포토레지스트(PR)를 도포하고, 노광 및 현상하여 상기 절연층(20)을 0.32 m 이하의 면적을 갖도록 노출시키는 단계(도2a)와; 스플릿 파워를 이용하여, C4F8, CF4, Ar 혼합가스를 플라즈마화하여 상기 노출된 절연막(2)을 식각하여 상기 기판(10)에 형성한 반도체 소자의 특정영역을 노출시키는 단계(도2b)와; 상기 포토레지스트(PR)를 제거하는 단계(도2c)로 구성된다.2A to 2C are cross-sectional views of a process for manufacturing a contact hole in a conventional semiconductor device. As shown in FIG. 2A to 2C, an insulating film 2 is deposited on a substrate 10 on which a semiconductor device is formed, and the upper front surface of the insulating film 2 is shown. Photoresist (PR) is applied to, exposed and developed to 0.32 the insulating layer 20 m Exposing to have the following area (FIG. 2A); Plasma-forming the mixed gas C 4 F 8 , CF 4 , and Ar using the split power to etch the exposed insulating film 2 to expose a specific region of the semiconductor device formed on the substrate 10 (FIG. 2b); Removing the photoresist PR (Fig. 2c).

이하, 상기와 같은 본 발명 반도체 장치의 콘택홀 형성방법을 좀 더 상세히 설명한다.Hereinafter, a method of forming a contact hole in the semiconductor device of the present invention as described above will be described in more detail.

먼저, 도2a에 도시한 바와 같이 일반적인 콘택홀 형성과 동일한 방법으로, 반도체 소자가 형성된 기판(10)의 상부에 절연층(20)을 증착하고, 그 절연층(20)의 상부에 콘택홀 패턴이 형성된 포토레지스트(PR)을 형성한다. 이때, 상기 콘택홀 패턴은 0.32 m 이하로 한다.First, as shown in FIG. 2A, the insulating layer 20 is deposited on the substrate 10 on which the semiconductor device is formed, and the contact hole pattern is formed on the insulating layer 20 in the same manner as in the general contact hole formation. The formed photoresist PR is formed. At this time, the contact hole pattern is 0.32 m It is set as follows.

그 다음, 도2b에 도시한 바와 같이 종래 0.37 m 이상의 콘택홀을 형성할 때 사용하던 스플릿파워를 이용하여 높은 압력에서 플라즈마를 형성하고, 그 플라즈마를 이용하여 상기 노출된 절연층(20)을 식각한다.Then, as shown in Fig. 2B, the conventional 0.37 m The split power used to form the above-mentioned contact hole is used to form a plasma at a high pressure, and the exposed insulating layer 20 is etched using the plasma.

이와 같은 식각공정에서 종래기술에서 설명한 바와 같이 높은 압력조건에서 플라즈마의 충돌에 의해 상기 콘택홀이 형성되는 절연층(20)의 콘택홀 측면부가 식각되어 0.32 m 이하의 콘택홀을 형성할 수 없게 되나, 절연층(20)의 식각시 폴리머(POLYMER)를 발생시키는 C4F8, CF4, Ar 혼합가스를 소스가스로 이용하여 플라즈마를 형성한 후, 콘택홀을 형성하면 그 콘택홀의 측면에는 폴리머에 의해 식각되지 않는다.In this etching process, as described in the related art, the contact hole side surface portion of the insulating layer 20 in which the contact hole is formed by the impact of plasma under high pressure is etched and 0.32. m The following contact holes cannot be formed, but after forming plasma using C 4 F 8 , CF 4 , Ar mixed gas which generates a polymer during etching of the insulating layer 20 as a source gas, the contact is formed. When the hole is formed, the side of the contact hole is not etched by the polymer.

이와 같은 과정으로 스플릿파워를 이용하여 0.32 m 이하의 콘택홀을 형성할 수 있게 되나, 상기 폴리머가 많이 발생되어 콘택홀의 저면에 쌓일 경우 콘택홀의 형성이 잘 진행되지 않을 수 있어, 온도조건을 5℃ 이상으로 유지하여 상기 폴리머가 콘택홀 하부에 형성되지 않도록 한다.This process uses split power 0.32 m The following contact holes can be formed, but when a lot of the polymer is generated and accumulated on the bottom of the contact hole, the formation of the contact hole may not proceed well. Thus, the polymer is maintained under the contact hole by maintaining a temperature condition of 5 ° C or higher. Do not form.

그 다음, 도2c에 도시한 바와 같이 상기 포토레지스트(PR) 패턴을 제거하여 콘택홀 형성과정을 완료하게 된다.Next, as shown in FIG. 2C, the photoresist (PR) pattern is removed to complete the contact hole forming process.

상기한 바와 같이 본 발명 반도체 장치의 콘택홀 형성방법은 폴리머를 발생시키는 소스 가스를 이용하여 스플릿파워의 사용할 때 발생하는 콘택홀 측면부의 과도식각을 방지하여, 0.32 m 이하의 콘택홀을 0.37 m 이상의 콘택홀을 형성할 때, 사용하던 스플릿파워를 사용할 수 있게 되어 콘택홀 형성장비의 사용효율성을 향상시키는 효과가 있다.As described above, the method for forming a contact hole in the semiconductor device of the present invention prevents excessive etching of the contact hole side portion generated when the split power is used by using a source gas that generates a polymer, thereby preventing 0.32. m 0.37 or less contact holes m When forming the above-mentioned contact hole, it is possible to use the split power used has the effect of improving the efficiency of use of the contact hole forming equipment.

Claims (3)

반도체 소자가 형성된 기판의 상부에 절연층을 증착하고, 상기 절연층에 포토레지스트 패턴을 형성하여 상기 절연층의 상부를 0.32 m 이하로 노출시키는 마스크 형성단계와; 플라즈마를 이용한 건식식각으로 상기 노출된 절연층에 콘택홀을 형성하는 건식식각단계와; 상기 포토레지스트 패턴을 제거하는 마스크 제거단계로 이루어지는 반도체 장치의 콘택홀 형성방법에 있어서, 상기 건식식각단계는 스플릿 파워를 이용하여 폴리머를 발생시키는 소스가스를 플라즈마화하여 그 플라즈마로 상기 0.32 m 이하의 크기로 노출된 절연층을 식각하는 것을 특징으로 하는 반도체 장치의 콘택홀 형성방법.An insulating layer is deposited on the substrate on which the semiconductor device is formed, and a photoresist pattern is formed on the insulating layer, thereby forming an upper portion of the insulating layer at 0.32. m A mask forming step of exposing below; A dry etching step of forming contact holes in the exposed insulating layer by dry etching using plasma; In the method for forming a contact hole of a semiconductor device comprising removing the photoresist pattern, the dry etching step is to plasma the source gas to generate a polymer using a split power to the plasma 0.32 m A method for forming a contact hole in a semiconductor device, comprising etching the insulating layer exposed to the following size. 제 1항에 있어서, 폴리머를 발생시키는 소스 가스는 C4F8, CF4, Ar 혼합가스인 것을 특징으로 하는 반도체 장치의 콘택홀 형성방법.The method of claim 1, wherein the source gas generating the polymer is a mixed gas of C 4 F 8 , CF 4 , and Ar. 제 1항에 있어서, 상기 건식식각단계는 5℃이상의 온도분위기에서 식각을 실시하여 발생된 폴리머가 콘택홀의 저면에 쌓이는 것을 방지하는 것을 특징으로 하는 반도체 장치의 콘택홀 형성방법.The method of claim 1, wherein the dry etching step is performed by etching in a temperature atmosphere of 5 ° C. or higher to prevent the polymer from being accumulated on the bottom surface of the contact hole.
KR10-1998-0055129A 1998-12-15 1998-12-15 Method for forming contact hole in semiconductor device_ KR100511929B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR10-1998-0055129A KR100511929B1 (en) 1998-12-15 1998-12-15 Method for forming contact hole in semiconductor device_

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR10-1998-0055129A KR100511929B1 (en) 1998-12-15 1998-12-15 Method for forming contact hole in semiconductor device_

Publications (2)

Publication Number Publication Date
KR20000039717A true KR20000039717A (en) 2000-07-05
KR100511929B1 KR100511929B1 (en) 2005-10-26

Family

ID=19562943

Family Applications (1)

Application Number Title Priority Date Filing Date
KR10-1998-0055129A KR100511929B1 (en) 1998-12-15 1998-12-15 Method for forming contact hole in semiconductor device_

Country Status (1)

Country Link
KR (1) KR100511929B1 (en)

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0794468A (en) * 1993-09-24 1995-04-07 Fujitsu Ltd Manufacture of semiconductor device
KR960015486A (en) * 1994-10-05 1996-05-22 이헌조 Sled Servo Control Method of Disc Playback Device
JPH09172070A (en) * 1995-12-18 1997-06-30 Matsushita Electric Ind Co Ltd Manufacture of semiconductor device
KR100230981B1 (en) * 1996-05-08 1999-11-15 김광호 Plasma etching method for manufacturing process of semiconductor device
KR100236089B1 (en) * 1996-12-20 1999-12-15 김영환 Contact hole forming method for semiconductor chip

Also Published As

Publication number Publication date
KR100511929B1 (en) 2005-10-26

Similar Documents

Publication Publication Date Title
US5895740A (en) Method of forming contact holes of reduced dimensions by using in-situ formed polymeric sidewall spacers
US20080182422A1 (en) Methods of etching photoresist on substrates
JP2988455B2 (en) Plasma etching method
US6647994B1 (en) Method of resist stripping over low-k dielectric material
KR100511929B1 (en) Method for forming contact hole in semiconductor device_
US5640038A (en) Integrated circuit structure with self-planarized layers
JPH0685396B2 (en) Etching method and apparatus used therefor
KR100338097B1 (en) Method for forming contact hole in semiconductor device
KR20000061225A (en) Method for fabricating trench of semiconductor device
KR19980036950A (en) Semiconductor device manufacturing method
TWI249202B (en) Dielectric etching method to prevent photoresist damage and bird's beak
KR0153508B1 (en) Method of fabricating a semiconductor device
KR100317310B1 (en) Method for fabricating contact hole of semiconductor device
KR100434312B1 (en) Method for making contact hole in semiconductor device
KR100200737B1 (en) Method for forming a contact hole of a semiconductor device
KR100195245B1 (en) Method for forming a contact of a semiconductor device
KR19980050430A (en) Oxide dry etching method
CN111785624A (en) Method for forming shallow trench structure
JPH04162625A (en) Formation method of contact hole
JPH0684841A (en) Formation method of groove in silicon substrate
KR20020024619A (en) method and apparatus for forming a pattern in a semiconductor fabricating
KR19980056995A (en) Metal wiring formation method of semiconductor device
JPH03156915A (en) Formation of pattern by multilayer resist method
JPH09326435A (en) Manufacture of semiconductor device
KR20000066421A (en) Method of forming micro patterns for semiconductor devices

Legal Events

Date Code Title Description
N231 Notification of change of applicant
A201 Request for examination
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20100726

Year of fee payment: 6

LAPS Lapse due to unpaid annual fee