KR20000037842A - Method for manufacturing thin film transistors - Google Patents
Method for manufacturing thin film transistors Download PDFInfo
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- KR20000037842A KR20000037842A KR1019980052621A KR19980052621A KR20000037842A KR 20000037842 A KR20000037842 A KR 20000037842A KR 1019980052621 A KR1019980052621 A KR 1019980052621A KR 19980052621 A KR19980052621 A KR 19980052621A KR 20000037842 A KR20000037842 A KR 20000037842A
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- mask
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- thin film
- drain electrode
- layer
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- 239000010409 thin film Substances 0.000 title abstract description 25
- 238000000034 method Methods 0.000 title abstract description 24
- 238000004519 manufacturing process Methods 0.000 title abstract description 22
- 239000012535 impurity Substances 0.000 claims abstract description 22
- 239000004065 semiconductor Substances 0.000 claims abstract description 16
- 238000000059 patterning Methods 0.000 claims abstract description 10
- 238000002161 passivation Methods 0.000 claims abstract description 7
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 239000000463 material Substances 0.000 claims description 3
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 claims description 2
- 239000010408 film Substances 0.000 abstract description 18
- 229910021417 amorphous silicon Inorganic materials 0.000 abstract description 9
- 238000000151 deposition Methods 0.000 abstract description 5
- 239000012212 insulator Substances 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 27
- 239000004973 liquid crystal related substance Substances 0.000 description 8
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 5
- 230000001681 protective effect Effects 0.000 description 5
- 238000000206 photolithography Methods 0.000 description 4
- 229910052779 Neodymium Inorganic materials 0.000 description 3
- 230000007547 defect Effects 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 229910052750 molybdenum Inorganic materials 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005401 electroluminescence Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000003384 imaging method Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 230000002035 prolonged effect Effects 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136231—Active matrix addressed cells for reducing the number of lithographic steps
Abstract
Description
본 발명은 예컨대, 액정표시장치의 능동소자로 사용되는 박막트랜지스터 제조방법에 관한 것으로, 좀더 상세하게는 소요되는 마스크의 매수를 예컨대, 5매에서 4매로 줄임으로써, 전체적인 제품의 재공기간을 단축시킬 수 있도록 하는 박막트랜지스터 제조방법에 관한 것이다.The present invention relates to, for example, a method for manufacturing a thin film transistor used as an active element of a liquid crystal display device, and more particularly, by reducing the number of masks required from 5 to 4, for example, to reduce the overall service life of the product. The present invention relates to a thin film transistor manufacturing method.
근래에 고품위 TV(High definition TV) 등의 새로운 첨단 영상기기가 개발됨에 따라 평판 표시기에 대한 요구가 급속히 확대되고 있다.Recently, with the development of new advanced imaging devices such as high definition TVs, the demand for flat panel displays is rapidly expanding.
액정표시장치는 이러한 평판 표시기의 대표적인 장치 중의 하나로써, 이를 이용하면, 예컨대, ELD(Electro luminescence display), VFD(Vacuum fluorescence display), PDP(Plasma display panel) 등이 해결하지 못한 저전력화, 고속화 등의 문제를 해결할 수 있기 때문에, 최근 들어 그 사용 영역이 크게 확산되고 있다.The liquid crystal display is one of the representative devices of such a flat panel display, and when it is used, for example, low power, high speed, etc., which the electroluminescence display (ELD), vacuum fluorescence display (VFD), plasma display panel (PDP), etc. cannot solve Since the problem can be solved, its use area has been greatly expanded in recent years.
이러한 액정표시장치는 크게 수동형과 능동형의 두 가지 형태로 나뉘는데, 이 중, 능동형 액정표시장치는 각 화소 하나하나를 박막트랜지스터와 같은 능동소자가 제어하도록 되어 있어, 속도, 시야각, 그리고 콘트라스트 측면에서, 수동형 액정표시장치에 비해 훨씬 뛰어나기 때문에, 100만 화소 이상의 해상도를 필요로하는 고품위 TV 등에 적합한 평판 표시기로 널리 각광받고 있다.The liquid crystal display is divided into two types, a passive type and an active type. Among the active liquid crystal display devices, each pixel is controlled by an active element such as a thin film transistor, and in terms of speed, viewing angle, and contrast, Since it is much superior to the passive liquid crystal display device, it has been widely spotlighted as a flat panel display suitable for high-definition TV or the like requiring a resolution of 1 million pixels or more.
최근, 액정표시장치의 능동소자로 사용되는 박막트랜지스터의 중요성이 크게 부각되면서, 이에 대한 연구개발이 더욱 심화되고 있다.Recently, as the importance of the thin film transistor used as an active element of the liquid crystal display device is greatly highlighted, the research and development thereof has been further intensified.
이러한 액정표시장치의 능동소자로 사용되는 박막트랜지터의 종래 구조 및 제조방법은 예컨대, 미국특허공보 제 5407846 호 "박막트랜지스터 제조방법(Method of manufacturing a thin film transistor)", 미국특허공보 제 5414283 호 "기생 캐패시턴스를 줄인 티에프티(TFT with reduced parasitic capacitance)", 미국특허공보 제 5508531 호 "박막트랜지스터 및 그의 제조방법(Thin film transistor and method of manufacturing thereof)", 미국특허공보 제 5532180 호 "채널길이를 줄인 티에프티 제조방법(Method of fabricating a TFT with reduced channel length)", 미국특허공보 제 5650358 호 "채널길이가 줄어든 티에프티 제조방법(Method of making a TFT having a reduced channel length)" 등에 좀더 상세하게 제시되어 있다.Conventional structures and manufacturing methods of thin film transistors used as active elements of such liquid crystal display devices are disclosed in, for example, US Patent No. 5407846, "Method of manufacturing a thin film transistor," US Patent No. 5414283. "TFT with reduced parasitic capacitance", US Patent No. 5508531 "Thin film transistor and method of manufacturing", US Patent No. 5532180 "Channel length Method of fabricating a TFT with reduced channel length ", US Patent No. 5650358" Method of making a TFT having a reduced channel length " Is presented.
통상, 상술한 종래의 박막트랜지스터를 완전하게 형성하기 위해서는 5매의 마스크가 소요되는 것이 일반적이다.In general, five masks are generally required to form the above-described conventional thin film transistor completely.
이를 살펴보면, 먼저, 게이트 전극을 형성하는 과정에서 1매의 마스크가 소요되고, 액티브 패턴을 형성하는 과정에서 다른 1매의 마스크가 더 소요되며, 소오스/드레인 전극 및 n+a-Si막을 패터닝하는 과정에서 또 다시 1매의 마스크가 소요되고, 보호막을 형성하는 과정에서 1매의 마스크가 더 소요되며, 화소전극을 형성하는 과정에서 1매의 마스크가 더 소요된다. 결국, 박막트랜지스터를 제조하는데에는 최소한 5매의 마스크가 소요되는 것이다.Referring to this, first, one mask is required in the process of forming the gate electrode, another mask is required in the process of forming the active pattern, and the source / drain electrode and the n + a-Si film are patterned. Another mask is required in the process, one mask is required in the process of forming the protective film, and one mask is required in the process of forming the pixel electrode. As a result, at least five masks are required to manufacture the thin film transistor.
통상, 1매의 마스크를 운용하는데에는 많은 운용경비가 지출되기 때문에, 종래의 생산라인에서는 이러한 마스크의 소요매수를 줄이고자 하는 노력을 부단히 기울이고 있다.In general, since a large operating cost is required to operate one mask, efforts are made to reduce the number of masks required in a conventional production line.
그런데, 종래의 경우, 정상적으로 동작하는 박막트랜지스터를 형성하기 위해서는 상술한 바와 같이, 최소한 5매의 마스크 공정이 필요로하며, 이러한 5매의 마스크는 박막트랜지스터를 제조하는 과정에서 반드시 필요한 한계 마스크 매수로 알려져 있기 때문에, 마스크의 소요매수를 줄여야할 필요성이 거듭 제기됨에도 불구하고, 종래의 상황에서는 이에 대한 대처방안이 전무한 형편이다.However, in the related art, as described above, at least five mask processes are required to form a thin film transistor that operates normally, and the five masks are limited to the number of limit masks necessary in the process of manufacturing the thin film transistor. Since the necessity of reducing the number of required masks has been repeatedly raised, there is no way to deal with this in the conventional situation.
만약, 마스크 소요매수를 적정 수준으로 줄이지 못하면, 제품의 재공기간 또한 줄이지 못하게 되고, 그 결과로, 재공기간이 길어질 경우, 제품에 예측하지 못한 불량이 발생될 개연성이 매우 높아진다.If the number of masks required is not reduced to an appropriate level, the service period of the product may not be reduced, and as a result, if the service period is prolonged, the probability of unforeseen defects occurring in the product becomes very high.
따라서, 본 발명의 목적은 박막트랜지스터/아이씨 패드의 구조를 정상적으로 확보함과 아울러, 마스크의 소요매수를 적정 수준으로 줄임으로써, 전체적인 제품의 생산효율을 향상시키는데 있다.Accordingly, an object of the present invention is to ensure the structure of the thin film transistor / IC pad as well as to reduce the required number of masks to an appropriate level, thereby improving the overall product production efficiency.
본 발명의 다른 목적은 마스크 소요매수 저감을 통해, 전체적인 재공기간을 단축시키는데 있다.Another object of the present invention is to reduce the total number of deadlines through reducing the number of masks required.
본 발명의 또 다른 목적은 제품의 재공기간을 단축시킴으로써, 제품에 발생될 수 있는 불량 개연성을 줄이는데 있다.It is another object of the present invention to shorten the deadline of the product, thereby reducing the probability of defects that may occur in the product.
본 발명의 또 다른 목적들은 다음의 상세한 설명과 첨부된 도면으로부터 보다 명확해질 것이다.Still other objects of the present invention will become more apparent from the following detailed description and the accompanying drawings.
도 1a 내지 도 1d는 본 발명에 따른 박막트랜지스터 제조방법을 순차적으로 도시한 단면공정도.1A to 1D are cross-sectional process diagrams sequentially illustrating a method of manufacturing a thin film transistor according to the present invention.
상기와 같은 목적을 달성하기 위한 본 발명은 기판상에 게이트 전극을 형성하고, 게이트 전극이 커버되도록 기판상에 게이트 절연막을 형성하는 단계와, 게이트 절연막상에 반도체층과 불순물층을 순차적으로 형성한 후, 불순물층을 미세결정화 하고, 게이트 절연막의 일부가 노출되도록 반도체층과 불순물층을 동시에 패터닝하여 액티브 패턴을 형성하는 단계와, 액티브 패턴이 커버되도록 게이트 절연막상에 ITO 재질의 소오스/드레인 전극을 형성한 후 불순물층의 일부가 노출되도록 소오스/드레인 전극을 패터닝하고, 패터닝된 소오스/드레인 전극을 마스크로 반도체층이 노출되도록 채널부분의 불순물층을 제거하는 단계와, 반도체층이 커버되도록 소오스/드레인 전극상에 보호막을 형성하고, 소오스/드레인 전극의 일부가 노출되도록 보호막을 패터닝하는 단계와, 소오스/드레인 전극과 전기적으로 접촉되도록 보호막상에 화소전극을 형성하는 단계를 포함한다.The present invention for achieving the above object is to form a gate electrode on the substrate, forming a gate insulating film on the substrate so that the gate electrode is covered, and sequentially forming a semiconductor layer and an impurity layer on the gate insulating film Thereafter, microcrystallization of the impurity layer and patterning the semiconductor layer and the impurity layer simultaneously to expose a portion of the gate insulating film to form an active pattern, and source / drain electrodes made of ITO on the gate insulating film so as to cover the active pattern Patterning the source / drain electrodes to expose a portion of the impurity layer after formation, and removing the impurity layer in the channel portion so that the semiconductor layer is exposed using the patterned source / drain electrodes as a mask, and source / drain to cover the semiconductor layer. A passivation film is formed on the drain electrode, and the passivation film is exposed so that a part of the source / drain electrode is exposed. And forming a pixel electrode on the protective film in contact with the step of turning, and a source / drain electrode.
이러한 본 발명이 달성되는 경우, 박막트랜지스터를 제조하는데 소요되는 전체 마스크의 매수는 5매에서 예컨대, 4매로 줄어들 수 있다.When the present invention is achieved, the total number of masks required to manufacture the thin film transistor can be reduced from five to for example four.
이하, 첨부된 도면을 참조하여 본 발명에 따른 박막트랜지스터 제조방법을 좀더 상세히 설명하면 다음과 같다.Hereinafter, a thin film transistor manufacturing method according to the present invention with reference to the accompanying drawings in more detail.
후술하는 본 발명의 박막트랜지스터 제조방법에서 소요되는 마스크의 총 매수는 예컨대, 모두 4개이다.The total number of masks required in the method of manufacturing a thin film transistor of the present invention described below is, for example, all four.
첫 번째 마스크가 소요되는 과정을 설명한다.Explain how the first mask takes.
본 발명에서는 먼저, 도 1a에 도시된 바와 같이, 기판(3)상에, 예컨대, Al-Nd와, Mo을 순차적으로 증착한다. 이러한 Al-Nd, Mo 등은 예컨대, 스퍼터링 증착법에 의해 증착된다. 이어서, 마스크를 이용한 사진식각공정을 진행하여, 형성된 Al-Nd, Mo 등을 정교하게 식각함으로써, 예컨대, "Al-Nd/Mo"의 적층구조를 갖는 게이트 전극(11)을 형성한다. 물론, 게이트 전극(11)은 Al, Ta, W, Cr 등과 같은 금속을 이용하여 단일층 구조로 형성될 수도 있다. 이러한 게이트 전극(11)의 패터닝을 위하여, 첫 번째 마스크가 소요된다.In the present invention, first, as shown in FIG. 1A, for example, Al-Nd and Mo are sequentially deposited on the substrate 3. Such Al-Nd, Mo or the like is deposited by, for example, a sputtering deposition method. Subsequently, a photolithography process using a mask is performed, and the formed Al-Nd, Mo, etc. are precisely etched to form the gate electrode 11 having a stacked structure of "Al-Nd / Mo", for example. Of course, the gate electrode 11 may be formed in a single layer structure using a metal such as Al, Ta, W, Cr or the like. For this patterning of the gate electrode 11, the first mask is taken.
계속해서, 게이트 전극(11)이 커버되도록 기판(3)상에, 예컨대, SiNX를 증착하여 게이트 절연막(12)을 형성한다. 이러한 게이트 절연막(12)은 예컨대, PECVD법에 의해 형성된다.Subsequently, for example, SiN X is deposited on the substrate 3 so that the gate electrode 11 is covered to form a gate insulating film 12. Such a gate insulating film 12 is formed by, for example, PECVD.
계속해서, 두 번째 마스크가 소요되는 과정을 설명한다.In the following, the process of taking the second mask is explained.
도 1b에 도시된 바와 같이, 본 발명에서는 다음 공정을 진행하여, 게이트 절연막(12)상에, 예컨대, 아모르포스 실리콘(a-Si)으로 이루어진 반도체층(13)과, N+-아모르포스 실리콘(N+a-Si)으로 이루어진 불순물층(14)을 순차적으로 증착한다. 이러한 반도체층(13), 불순물층(14) 등은 예컨대, PECVD 증착법에 의해 형성된다.As shown in FIG. 1B, in the present invention, the following process is performed, and the semiconductor layer 13 made of, for example, amorphous silicon (a-Si) and N + -amorphous silicon on the gate insulating film 12. The impurity layer 14 made of (N + a-Si) is sequentially deposited. The semiconductor layer 13, the impurity layer 14, and the like are formed by, for example, PECVD deposition.
계속해서, 통상의 미세결정화 공정을 진행시켜, 불순물층(14)을 미세결정화시킨다. 이와 같이, 불순물층(14)이 미세결정화되는 경우, 추후에 형성되는 ITO 재질의 소오스/드레인 전극과 불순물층(14)과의 콘택저항은 크게 줄어든다.Subsequently, a normal microcrystallization process is performed to fine-crystallize the impurity layer 14. As described above, when the impurity layer 14 is microcrystallized, the contact resistance between the source / drain electrode of ITO material and the impurity layer 14 formed later is greatly reduced.
이어서, 마스크를 이용한 사진식각공정을 진행하여, 게이트 절연막(12)의 일부가 노출되도록 반도체층(13), 불순물층(14)의 양 측부를 정교하게 패터닝함으로써, 반도체층(13)과 불순물층(14)이 적층된 구조의 액티브 패턴을 형성한다. 이러한 액티브 패턴의 패터닝을 위하여 두 번째 마스크가 소요된다.Subsequently, a photolithography process using a mask is performed, and the semiconductor layer 13 and the impurity layer are precisely patterned on both sides of the semiconductor layer 13 and the impurity layer 14 so that a part of the gate insulating film 12 is exposed. An active pattern having a stacked structure of 14 is formed. A second mask is required to pattern the active pattern.
그 다음에, 세 번째 마스크가 소요되는 과정을 설명한다.Next, the process of taking the third mask will be described.
본 발명에서는 다음 단계를 진행하여, 액티브 패턴이 커버되도록 게이트 절연막(12)상에, 예컨대, ITO(Indium Tin Oxide) 재질로 이루어진 소오스/드레인 전극(15)을 증착 형성한다. 이때, ITO로 이루어진 소오스/드레인 전극(15)은 예컨대, PECVD 증착법에 의해 형성된다. 물론, 상술한 바와 같이, 소오스/드레인 전극(15)의 저부에 배치된 불순물층(14)은 미리 진행된 미세결정화 공정에 의해 미세결정화 되어 있기 때문에, 상술한 공정에 의해 소오스/드레인 전극(15)이 형성되더라도 이들 사이의 콘택저항은 최소한의 값을 유지할 수 있다.In the present invention, the next step is carried out to form a source / drain electrode 15 formed of, for example, indium tin oxide (ITO) on the gate insulating layer 12 so as to cover the active pattern. At this time, the source / drain electrodes 15 made of ITO are formed by, for example, PECVD deposition. Of course, as described above, since the impurity layer 14 disposed on the bottom of the source / drain electrode 15 is microcrystallized by a previously advanced microcrystallization process, the source / drain electrode 15 is formed by the above-described process. Even if this is formed, the contact resistance therebetween can be kept to a minimum value.
이어서, 마스크를 이용한 사진식각공정을 진행하여, 소오스/드레인 전극(15)의 채널부분을 패터닝함으로써, 액티브 패턴을 구성하는 불순물층(14)의 일부가 콘택홀 A를 통하여 노출되도록 한다. 이러한 소오스/드레인 전극(15)의 패터닝을 위하여 세 번째 마스크가 소요된다.Subsequently, a photolithography process using a mask is performed to pattern a channel portion of the source / drain electrode 15 so that a part of the impurity layer 14 constituting the active pattern is exposed through the contact hole A. FIG. A third mask is required for patterning this source / drain electrode 15.
계속해서, 패터닝된 소오스/드레인 전극(15)을 에칭 마스크로하여, 예컨대, 플라즈마 에칭공정을 진행하고, 이를 통해, 채널부분에 형성된 불순물층(14)의 일부를 제거시킴으로써, 반도체층(13)의 일부를 노출시킨다. 이에 따라, 도 2b에 도시된 바와 같은 에치백 구조가 완성된다.Subsequently, using the patterned source / drain electrodes 15 as an etching mask, for example, a plasma etching process is performed, and through this, a portion of the impurity layer 14 formed in the channel portion is removed, whereby the semiconductor layer 13 Expose a portion of the. Thus, an etch back structure as shown in Fig. 2B is completed.
마지막으로 네 번째 마스크가 소요되는 과정을 설명한다.Finally, the process of taking the fourth mask is explained.
도 1c에 도시된 바와 같이, 본 발명에서는 다음 단계를 진행하여, 반도체층(13)이 커버되도록 소오스/드레인 전극(15)상에, 예컨대, SiNX로 이루어진 보호막(16)을 증착한다. 이러한 보호막(16)은 예컨대, PECVD 증착법에 의해 형성된다.As shown in FIG. 1C, in the present invention, a protective film 16 made of, for example, SiN X is deposited on the source / drain electrodes 15 so that the semiconductor layer 13 is covered. This protective film 16 is formed by, for example, PECVD deposition.
이어서, 마스크를 이용한 사진식각공정을 진행하여, 콘택홀 B를 통해 소오스/드레인 전극(15)의 일부가 노출되도록 보호막(16)의 일부를 정교하게 패터닝한다. 이러한 보호막(16)의 패터닝을 위하여 네 번째 마스크가 소요된다.Subsequently, a photolithography process using a mask is performed to partially pattern the passivation layer 16 so that a portion of the source / drain electrode 15 is exposed through the contact hole B. A fourth mask is required for the patterning of the protective film 16.
이후, 도 1d에 도시된 바와 같이, 예컨대, PECVD 공정이 진행되어, 콘택홀 B에는 예컨대, ITO 재질의 화소전극(17)이 형성되고, 본 발명에 의한 박막트랜지스터는 제조 완료된다.Thereafter, as illustrated in FIG. 1D, for example, a PECVD process is performed, and a pixel electrode 17 made of, for example, an ITO material is formed in the contact hole B, and the thin film transistor according to the present invention is manufactured.
이상의 설명에서와 같이, 본 발명에서는 박막트랜지스터를 제조할 때 소요되는 마스크의 매수를 예컨대, 5매에서 4매로 줄일 수 있다.As described above, in the present invention, the number of masks required when manufacturing the thin film transistor can be reduced, for example, from five to four.
이러한 본 발명은 단지 상술한 액정표시장치용 박막트랜지스터에 국한되지 않으며, 생산라인에서 제조되는 전 품종의 박막트랜지스터에서 전반적으로 유용한 효과를 나타낸다.The present invention is not limited to the above-described thin film transistors for liquid crystal display devices, and has an overall useful effect in all kinds of thin film transistors manufactured in a production line.
그리고, 본 발명의 특정한 실시예가 설명되고 도시되었지만 본 발명이 당업자에 의해 다양하게 변형되어 실시될 가능성이 있는 것은 자명한 일이다.And while certain embodiments of the invention have been described and illustrated, it will be apparent that the invention may be embodied in various modifications by those skilled in the art.
이와 같은 변형된 실시예들은 본 발명의 기술적사상이나 관점으로부터 개별적으로 이해되어서는 안되며 이와 같은 변형된 실시예들은 본 발명의 첨부된 특허청구의 범위안에 속한다 해야 할 것이다.Such modified embodiments should not be understood individually from the technical spirit or point of view of the present invention and such modified embodiments should fall within the scope of the appended claims of the present invention.
이상에서 상세히 설명한 바와 같이, 본 발명에 따른 박막트랜지스터 제조방법에서는 박막트랜지스터를 제조할 때 소요되는 마스크의 매수를 예컨대, 5매에서 4매로 줄임으로써, 전체적인 제품의 재공기간을 단축시킨다. 이 경우, 제품에 발생될 수 있는 불량 개연성은 종래에 비해 현저히 저감된다.As described in detail above, in the method of manufacturing a thin film transistor according to the present invention, the number of masks required for manufacturing the thin film transistor is reduced from, for example, 5 to 4 sheets, thereby reducing the overall service life of the product. In this case, the probability of defects that may occur in the product is significantly reduced as compared with the prior art.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100390802B1 (en) * | 2001-05-24 | 2003-07-12 | 엘지.필립스 엘시디 주식회사 | Manufacturing method for tft-lcd |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR900005612A (en) * | 1988-09-30 | 1990-04-14 | 최근선 | Amorphous Silicon Thin Film Transistor with 4 Mask Level Protection Structure |
| US5462887A (en) * | 1993-11-22 | 1995-10-31 | Ernst Luder | Process for making a matrix of thin layer transistors with memory capacitors |
| KR970028753A (en) * | 1995-11-20 | 1997-06-24 | 김주용 | Manufacturing method of liquid crystal display element |
| KR970053623A (en) * | 1995-12-29 | 1997-07-31 | 김광호 | Thin film transistor substrate for liquid crystal display device and manufacturing method thereof |
| KR970077369A (en) * | 1996-05-16 | 1997-12-12 | 김광호 | Manufacturing method of thin film transistor |
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR900005612A (en) * | 1988-09-30 | 1990-04-14 | 최근선 | Amorphous Silicon Thin Film Transistor with 4 Mask Level Protection Structure |
| US5462887A (en) * | 1993-11-22 | 1995-10-31 | Ernst Luder | Process for making a matrix of thin layer transistors with memory capacitors |
| KR970028753A (en) * | 1995-11-20 | 1997-06-24 | 김주용 | Manufacturing method of liquid crystal display element |
| KR970053623A (en) * | 1995-12-29 | 1997-07-31 | 김광호 | Thin film transistor substrate for liquid crystal display device and manufacturing method thereof |
| KR970077369A (en) * | 1996-05-16 | 1997-12-12 | 김광호 | Manufacturing method of thin film transistor |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100390802B1 (en) * | 2001-05-24 | 2003-07-12 | 엘지.필립스 엘시디 주식회사 | Manufacturing method for tft-lcd |
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