KR20000027932A - Method of manufacturing bit line of semiconductor device - Google Patents
Method of manufacturing bit line of semiconductor device Download PDFInfo
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- KR20000027932A KR20000027932A KR1019980045977A KR19980045977A KR20000027932A KR 20000027932 A KR20000027932 A KR 20000027932A KR 1019980045977 A KR1019980045977 A KR 1019980045977A KR 19980045977 A KR19980045977 A KR 19980045977A KR 20000027932 A KR20000027932 A KR 20000027932A
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- Prior art keywords
- forming
- titanium
- film
- contact hole
- bit line
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 21
- 238000004519 manufacturing process Methods 0.000 title abstract description 4
- 239000010410 layer Substances 0.000 claims abstract description 43
- 238000000034 method Methods 0.000 claims abstract description 30
- 229910052751 metal Inorganic materials 0.000 claims abstract description 26
- 239000002184 metal Substances 0.000 claims abstract description 26
- 239000011229 interlayer Substances 0.000 claims abstract description 22
- 239000010936 titanium Substances 0.000 claims abstract description 21
- 229910052719 titanium Inorganic materials 0.000 claims abstract description 20
- 229910000838 Al alloy Inorganic materials 0.000 claims abstract description 19
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims abstract description 18
- 230000004888 barrier function Effects 0.000 claims abstract description 18
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims abstract description 15
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 150000001875 compounds Chemical class 0.000 claims abstract description 10
- 238000005530 etching Methods 0.000 claims abstract description 10
- 229910052782 aluminium Inorganic materials 0.000 claims abstract description 3
- 150000004767 nitrides Chemical class 0.000 claims abstract description 3
- 229910010038 TiAl Inorganic materials 0.000 claims description 8
- 238000005229 chemical vapour deposition Methods 0.000 claims description 8
- 238000005240 physical vapour deposition Methods 0.000 claims description 5
- 229910052710 silicon Inorganic materials 0.000 claims description 5
- 238000000151 deposition Methods 0.000 claims description 3
- 229910052802 copper Inorganic materials 0.000 claims description 2
- 230000008021 deposition Effects 0.000 claims description 2
- 229910052698 phosphorus Inorganic materials 0.000 claims description 2
- 239000011574 phosphorus Substances 0.000 claims description 2
- -1 phosphorus ions Chemical class 0.000 claims description 2
- 150000003608 titanium Chemical class 0.000 claims description 2
- 230000006866 deterioration Effects 0.000 abstract description 3
- 229910010039 TiAl3 Inorganic materials 0.000 abstract 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 17
- 229920005591 polysilicon Polymers 0.000 description 17
- 238000010438 heat treatment Methods 0.000 description 6
- 229910008484 TiSi Inorganic materials 0.000 description 5
- 230000002776 aggregation Effects 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical group [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 3
- 238000005054 agglomeration Methods 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 238000004220 aggregation Methods 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000007872 degassing Methods 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 208000024891 symptom Diseases 0.000 description 1
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 1
- 229910021342 tungsten silicide Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/482—Bit lines
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/2855—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by physical means, e.g. sputtering, evaporation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76846—Layer combinations
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76855—After-treatment introducing at least one additional element into the layer
- H01L21/76858—After-treatment introducing at least one additional element into the layer by diffusing alloying elements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
- H01L21/76889—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances by forming silicides of refractory metals
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- Computer Hardware Design (AREA)
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- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
본 발명은 반도체 소자의 제조 방법에 관한 것으로서, 특히 TiAl3/TiN 구조로 장벽 금속층을 형성하여 안정된 콘택 저항을 확보할 수 있는 반도체 소자의 비트라인 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a bit line of a semiconductor device capable of securing stable contact resistance by forming a barrier metal layer with a TiAl 3 / TiN structure.
종래의 비트라인은 폴리실리콘과 텅스텐 실리사이드로 이루어진 폴리사이드를 사용하였다. 그러나, 폴리사이드는 텅스텐(W) 등의 금속에 비해 상대적으로 큰 전기저항이 유발되었고, 이에 따라 소자의 고속화에 어려움이 발생되었다. 그래서, 비트라인 형성시 금속을 사용하였으며, 이 경우에는 티타늄/티타늄나이트라이드막(Ti/TiN)의 장벽 금속층이 사용되었는데, 도 1을 통해 종래의 비트라인 형성 방법을 설명한다.The conventional bit line uses a polyside composed of polysilicon and tungsten silicide. However, polysides have a relatively large electrical resistance compared to metals such as tungsten (W), thereby causing difficulties in speeding up the device. Thus, a metal was used to form the bit line, and in this case, a barrier metal layer of a titanium / titanium nitride layer (Ti / TiN) was used.
도 1(a) 내지 도 1(c)는 종래 반도체 소자의 비트라인 형성 방법을 설명하기 위한 단면도이다.1 (a) to 1 (c) are cross-sectional views for describing a bit line forming method of a conventional semiconductor device.
도 1(a)를 참조하면, 접합부(5)가 형성된 반도체 기판(1)상에 제 1 층간 절연막(10)을 형성한 후, 콘택 식각 공정을 통해 제 1 층간 절연막(10)의 선택된 부분을 식각하여 제 1 콘택홀(20)을 형성한다. 상기 제 1 콘택홀(20)에 도프트 폴리실리콘을 매립하여 폴리실리콘 플러그(30)를 형성한다.Referring to FIG. 1A, after forming the first interlayer insulating film 10 on the semiconductor substrate 1 on which the junction part 5 is formed, a selected portion of the first interlayer insulating film 10 is formed through a contact etching process. Etching is performed to form the first contact hole 20. Doped polysilicon is embedded in the first contact hole 20 to form a polysilicon plug 30.
도 1(b)를 참조하면, 상기 폴리실리콘 플러그(30)가 형성된 전체 구조상에 제 2 층간 절연막(40)을 형성한다. 콘택 식각 공정을 통해, 폴리실리콘 플러그(30)가 노출되도록 제 2 층간 절연막(40)의 선택된 부분을 식각하여 제 2 콘택홀(50)을 형성한다. 스퍼터링 증착 공정을 통해, 상기 제 2 콘택홀(50)을 포함하는 전체 구조상에 티타늄막(58) 및 티타늄 나이트라이드막(59)이 순차적으로 형성된 장벽 금속층(60)을 형성한다.Referring to FIG. 1B, a second interlayer insulating film 40 is formed on the entire structure in which the polysilicon plug 30 is formed. Through the contact etching process, the selected portion of the second interlayer insulating film 40 is etched to expose the polysilicon plug 30 to form the second contact hole 50. Through the sputtering deposition process, the barrier metal layer 60 in which the titanium film 58 and the titanium nitride film 59 are sequentially formed is formed on the entire structure including the second contact hole 50.
도 1(c)를 참조하면, 화학 기상 증착법을 통해, 상기 장벽 금속층(60)이 형성된 전체 구조상에 제 2 콘택홀(50)이 충분히 매립되도록 금속층(70)을 형성한다. 상기 금속층(70) 및 장벽 금속층(60)을 순차적으로 식각하여, 폴리실리콘 플러그(30)를 통해 반도체 기판(1)의 접합부(5)와 전기적으로 연결되는 비트라인(70)을 형성한다.Referring to FIG. 1C, the metal layer 70 is formed to sufficiently fill the second contact hole 50 on the entire structure in which the barrier metal layer 60 is formed by chemical vapor deposition. The metal layer 70 and the barrier metal layer 60 are sequentially etched to form a bit line 70 electrically connected to the junction portion 5 of the semiconductor substrate 1 through the polysilicon plug 30.
티타늄/티타늄나이트라이드막으로 이루어진 장벽 금속층(60)은 후속 열처리 공정시에 티타늄과 폴리실리콘 플러그(30)의 실리콘(Si)과의 과도한 반응이 야기되어, 도 1(c)의 A 부분에 도시된 TiSi2의 응집 현상이 발생될 수 있다. TiSi2의 응집 현상은 TiSi2가 700℃ 이상에서 상변화를 일으키는 동시에 구상화 반응을 일으켜 서로 뭉치는 현상으로서, 실리콘 내부에 있는 도펀트까지 소모하는 문제점을 야기시킨다. 이로 인하여, 콘택 저항 및 누설 전류의 증가 현상이 발생하게 되었다.The barrier metal layer 60 made of titanium / titanium nitride film causes excessive reaction of titanium and silicon (Si) of the polysilicon plug 30 during the subsequent heat treatment process, as shown in part A of FIG. 1 (c). Aggregation of TiSi 2 may occur. Agglomeration of the TiSi 2 is a bundle Symptoms each other causing a reaction at the same time, the spheroidized TiSi 2, causing a phase change in at least 700 ℃, thereby causing a problem that consumption by the dopant inside the silicon. As a result, an increase in contact resistance and leakage current occurs.
따라서, 본 발명은 알루미늄합금/티타늄/티타늄나이트라이드막으로 이루어진 장벽 금속층을 형성하여 종래의 TiSi2의 응집 현상을 방지하므로서, 콘택 저항을 안정화시킬 수 있고 전기적 특성 저하를 방지할 수 있는 반도체 소자의 비트라인 형성 방법을 제공하는데 그 목적이 있다.Accordingly, the present invention forms a barrier metal layer made of an aluminum alloy / titanium / titanium nitride film to prevent a conventional TiSi 2 agglomeration phenomenon, thereby making it possible to stabilize contact resistance and to prevent electrical property deterioration. It is an object of the present invention to provide a bit line forming method.
상기한 목적을 달성하기 위한 본 발명에 따른 반도체 소자의 비트라인 형성 방법은 접합부가 형성된 반도체 기판상에 제 1 층간 절연막을 형성한 후, 상기 제 1 층간 절연막의 선택된 부분에 제 1 콘택홀을 형성하는 단계; 상기 제 1 콘택홀 내에 플러그를 형성한 후, 제 2 층간 절연막을 형성하는 단계; 상기 플러그가 노출되도록 상기 제 2 층간 절연막의 선택된 부분을 식각하여 제 2 콘택홀을 형성하는 단계; 상기 제 2 콘택홀을 포함하는 전체 구조상에 알루미늄 합금막, 티타늄막 및 티타늄 나이트라이드막을 순차적으로 형성하는 단계; 상기 알루미늄 합금막 및 티타늄막이 상호 반응하도록 350 내지 500℃의 온도 범위의 열처리를 실시하여 TiAl3의 화합물을 형성하고, 이로 인하여 상기 TiAl3의 화합물 및 상기 나이트라이드막으로 이루어지는 장벽 금속층이 형성되는 단계; 및 상기 플러그를 통해 상기 반도체 기판과 전기적으로 연결되는 비트라인을 형성하는 단계를 포함하여 이루어지는 것을 특징으로 한다.In the method of forming a bit line of a semiconductor device according to the present invention for achieving the above object, after forming a first interlayer insulating film on a semiconductor substrate on which a junction is formed, a first contact hole is formed in a selected portion of the first interlayer insulating film. Doing; Forming a second interlayer insulating layer after forming a plug in the first contact hole; Etching a selected portion of the second interlayer insulating layer to expose the plug to form a second contact hole; Sequentially forming an aluminum alloy film, a titanium film, and a titanium nitride film on the entire structure including the second contact hole; Heat treating at a temperature in the range of 350 to 500 ° C. such that the aluminum alloy film and the titanium film react with each other to form a compound of TiAl 3 , thereby forming a barrier metal layer comprising the compound of TiAl 3 and the nitride film. ; And forming a bit line electrically connected to the semiconductor substrate through the plug.
도 1(a) 내지 도 1(c)는 종래 반도체 소자의 비트라인 형성 방법을 설명하기 위한 단면도.1 (a) to 1 (c) are cross-sectional views for explaining a bit line forming method of a conventional semiconductor device.
도 2(a) 내지 도 2(c)는 본 발명에 따른 반도체 소자의 비트라인 형성 방법을 설명하기 위한 단면도.2 (a) to 2 (c) are cross-sectional views illustrating a method of forming a bit line of a semiconductor device according to the present invention.
〈도면의 주요 부분에 대한 부호 설명〉<Description of Signs of Major Parts of Drawings>
1 및 100 : 반도체 기판 10 및 110 : 제 1 층간 절연막1 and 100: semiconductor substrate 10 and 110: first interlayer insulating film
20 및 120 : 제 1 콘택홀 30 및 130 : 폴리실리콘 플러그20 and 120: first contact hole 30 and 130: polysilicon plug
40 및 140 : 제 2 층간 절연막 50 및 150 : 제 2 콘택홀40 and 140: Second interlayer insulating film 50 and 150: Second contact hole
58 및 158 : 티타늄막 59 및 159 : 티타늄 나이트라이드막58 and 158: titanium film 59 and 159: titanium nitride film
60 및 160 : 장벽 금속층 157 : 알루미늄 합금층60 and 160: barrier metal layer 157: aluminum alloy layer
70 및 170 : 비트라인 5 및 105 : 접합부70 and 170: bitline 5 and 105: junction
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
도 2(a) 내지 도 2(c)는 본 발명에 따른 반도체 소자의 비트라인 형성 방법을 설명하기 위한 단면도이다.2 (a) to 2 (c) are cross-sectional views illustrating a method of forming a bit line of a semiconductor device according to the present invention.
도 2(a)를 참조하면, 접합부(105)가 형성된 반도체 기판(100)상에 제 1 층간 절연막(110)을 형성한 후, 콘택 식각 공정을 통해 제 1 층간 절연막(110)의 선택된 부분을 식각하여 제 1 콘택홀(120)을 형성한다. 상기 제 1 콘택홀(120)에 도프트 폴리실리콘을 매립하여 폴리실리콘 플러그(130)를 형성한다.Referring to FIG. 2A, after forming the first interlayer insulating layer 110 on the semiconductor substrate 100 on which the junction portion 105 is formed, the selected portion of the first interlayer insulating layer 110 is formed through a contact etching process. Etching is performed to form the first contact hole 120. A doped polysilicon is embedded in the first contact hole 120 to form a polysilicon plug 130.
폴리실리콘 플러그(130)는 반응로(furnace)나 챔버(chamber)를 이용한 증착 방법에 의해 1000 내지 5000Å의 두께로 형성된다. 또한, 폴리실리콘 플러그(130)에 도핑된 도펀트는 인(phosporus)이고, 도핑 농도는 1E18 내지 1E21/㎤이다. 이때, 제 1 콘택홀(120) 내부에만 폴리실리콘이 잔류되도록 하기 위해, 제 1 콘택홀(120) 외부의 폴리실리콘은 화학적 기계적 연마(CMP) 또는 에치-백(Etch- Back) 공정을 통해 제거한다.The polysilicon plug 130 is formed to a thickness of 1000 to 5000 kPa by a deposition method using a furnace or a chamber. In addition, the dopant doped in the polysilicon plug 130 is phosphorus, and the doping concentration is 1E18 to 1E21 / cm 3. In this case, in order to ensure that the polysilicon remains only in the first contact hole 120, the polysilicon outside the first contact hole 120 is removed through a chemical mechanical polishing (CMP) or etch-back process. do.
도 2(b)를 참조하면, 상기 폴리실리콘 플러그(130)가 형성된 전체 구조상에 제 2 층간 절연막(140)을 형성한다. 콘택 식각 공정을 통해 폴리실리콘 플러그(130)가 노출되도록 제 2 층간 절연막(140)의 선택된 부분을 식각하여 제 2 콘택홀(150)을 형성한다. 스퍼터링 증착 공정을 통해, 상기 제 2 콘택홀(150)을 포함하는 전체 구조상에 알루미늄 합금막(157), 티타늄막(158) 및 티타늄 나이트라이드막(159)이 순차적으로 형성된 장벽 금속층(160)을 형성한다.Referring to FIG. 2B, a second interlayer insulating layer 140 is formed on the entire structure in which the polysilicon plug 130 is formed. The second contact hole 150 is formed by etching the selected portion of the second interlayer insulating layer 140 to expose the polysilicon plug 130 through a contact etching process. Through the sputtering deposition process, the barrier metal layer 160 in which the aluminum alloy layer 157, the titanium layer 158, and the titanium nitride layer 159 are sequentially formed is formed on the entire structure including the second contact hole 150. Form.
알루미늄 합금막(157)은 100∼94% Al, 0∼3% Si, 0∼3% Cu의 조성을 갖는다. 또한, 알루미늄 합금막(157)은 물리 기상 증착법(PVD) 또는 화학 기상 증착법(CVD)을 통해 25 내지 400℃의 증착 온도 범위에서 50 내지 200Å 두께로 형성된다. 티타늄막(158) 및 티타늄 나이트라이드막(159)은 물리 기상 증착법 또는 화학 기상 증착법을 통해 형성되고, 50 내지 500Å의 두께로 각각 형성된다.The aluminum alloy film 157 has a composition of 100 to 94% Al, 0 to 3% Si, and 0 to 3% Cu. In addition, the aluminum alloy film 157 is formed to have a thickness of 50 to 200 kPa in a deposition temperature range of 25 to 400 ° C. through physical vapor deposition (PVD) or chemical vapor deposition (CVD). The titanium film 158 and the titanium nitride film 159 are formed by a physical vapor deposition method or a chemical vapor deposition method, and are formed to have a thickness of 50 to 500 kPa, respectively.
알루미늄 합금막(157) 및 티타늄막(158)은 열처리에 의해 상호 반응하여 TiAl3의 화합물이 된다. 이때, 알루미늄 합금막(157)은 후속 공정시 알루미늄 융해 (Al melting) 현상을 방지하기 위해, 상기 열처리시 전부 반응시킨다. 여기서, 열처리는 350 내지 500℃의 온도 범위로 실시되고, 반응로(furnace), 스퍼터 시스템(Sputter System) 자체에 부착된 챔버(Degassing Chamber) 또는 급속 열처리 공정 시스템(RTP System)이 이용된다. TiAl3의 화합물은 알루미늄 합금막(157)과 티타늄막(158)의 반응하여 350℃부터 형성되기 시작하는데, 일단 형성되면 1400℃까지 상 변화없이 안정된 화학양론적 화합물로 존재하는 특성을 갖는다. 또한, 비저항이 티타늄 나이트라이드막(159)과 비슷하여 실리콘과의 오옴 콘택(Ohmic Contact)을 형성할 수 있다.The aluminum alloy film 157 and the titanium film 158 react with each other by heat treatment to form a compound of TiAl 3 . At this time, the aluminum alloy film 157 is all reacted during the heat treatment to prevent Al melting phenomenon in the subsequent process. Here, the heat treatment is carried out in a temperature range of 350 to 500 ℃, a degassing chamber or a rapid heat treatment process system (RTP System) attached to the furnace (furnace), the sputter system (Sputter System) itself is used. The compound of TiAl 3 starts to form at 350 ° C. by reacting the aluminum alloy film 157 with the titanium film 158. Once formed, the compound of TiAl 3 exists as a stable stoichiometric compound without a phase change to 1400 ° C. In addition, since the resistivity is similar to that of the titanium nitride film 159, an ohmic contact with silicon may be formed.
한편, 상기 장벽 금속층(160)은 티타늄막(158), 알루미늄 합금막(157) 및 티타늄 나이트라이드막(159)의 형태로 형성될 수 있다.The barrier metal layer 160 may be formed in the form of a titanium film 158, an aluminum alloy film 157, and a titanium nitride film 159.
도 2(c)를 참조하면, 화학 기상 증착법을 통해, 상기 장벽 금속층(160)이 형성된 전체 구조상에 제 2 콘택홀(150)이 충분히 매립되도록 텅스텐과 같은 금속층(170)을 형성한다. 상기 금속층(170) 및 장벽 금속층(160)을 순차적으로 식각하여, 폴리실리콘 플러그(130)를 통해 반도체 기판(100)의 접합부(105)와 전기적으로 연결되는 비트라인(170)을 형성한다.Referring to FIG. 2C, a metal layer 170 such as tungsten is formed to sufficiently fill the second contact hole 150 on the entire structure in which the barrier metal layer 160 is formed through chemical vapor deposition. The metal layer 170 and the barrier metal layer 160 are sequentially etched to form a bit line 170 electrically connected to the junction portion 105 of the semiconductor substrate 100 through the polysilicon plug 130.
금속층(170)은 물리 기상 증착법 또는 화학 기상 증착법에 의해 200 내지 4000Å의 두께로 형성되고, 특히 화학 기상 증착법인 경우에는 B2H6가스의 사용을 포함한다. 금속층(170)의 반사 방지층으로 TiN 또는 SiON을 사용한다.The metal layer 170 is formed to a thickness of 200 to 4000 kPa by the physical vapor deposition method or the chemical vapor deposition method, in particular in the case of the chemical vapor deposition method includes the use of B 2 H 6 gas. TiN or SiON is used as the antireflection layer of the metal layer 170.
상술한 바와 같이, 본 발명은 알루미늄합금/티타늄/티타늄나이트라이드막으로 이루어진 장벽 금속층을 형성하여 종래의 TiSi2의 응집 현상을 방지하므로서, 콘택 저항을 안정화시킬 수 있고 전기적 특성 저하를 방지할 수 있다. 또한, 본 발명은 별도의 설계 변경없이, 캐패시터가 비트라인 상부에 있는 구조는 물론 캐패시터가 비트라인 하부에 있는 구조에도 적용 가능하다. 그리고, 후속 열처리 공정에 의해 특성 열화가 없으므로 캐패시터 종류 및 공정을 다양하게 적용할 수 있다.As described above, the present invention forms a barrier metal layer made of an aluminum alloy / titanium / titanium nitride film, thereby preventing the conventional TiSi 2 agglomeration phenomenon, thereby making it possible to stabilize contact resistance and prevent electrical property degradation. . In addition, the present invention can be applied to a structure in which the capacitor is located below the bit line as well as a structure in which the capacitor is located below the bit line without any design change. In addition, since there is no characteristic deterioration by a subsequent heat treatment process, a variety of capacitor types and processes may be applied.
Claims (6)
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| KR1019980045977A KR20000027932A (en) | 1998-10-29 | 1998-10-29 | Method of manufacturing bit line of semiconductor device |
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| Application Number | Priority Date | Filing Date | Title |
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| KR1019980045977A KR20000027932A (en) | 1998-10-29 | 1998-10-29 | Method of manufacturing bit line of semiconductor device |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100463178B1 (en) * | 2002-04-19 | 2004-12-23 | 아남반도체 주식회사 | Formation method of stacking structure of metal line in semiconductor device |
| KR100702803B1 (en) * | 2005-12-28 | 2007-04-03 | 동부일렉트로닉스 주식회사 | Method for forming metal wiring layer of semiconductor device |
| KR100905872B1 (en) | 2007-08-24 | 2009-07-03 | 주식회사 하이닉스반도체 | Method of forming a metal layer in semiconductor device |
| KR101035396B1 (en) * | 2003-12-08 | 2011-05-20 | 주식회사 하이닉스반도체 | method for forming a pattern in a semiconductor device |
-
1998
- 1998-10-29 KR KR1019980045977A patent/KR20000027932A/en not_active Application Discontinuation
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100463178B1 (en) * | 2002-04-19 | 2004-12-23 | 아남반도체 주식회사 | Formation method of stacking structure of metal line in semiconductor device |
| KR101035396B1 (en) * | 2003-12-08 | 2011-05-20 | 주식회사 하이닉스반도체 | method for forming a pattern in a semiconductor device |
| KR100702803B1 (en) * | 2005-12-28 | 2007-04-03 | 동부일렉트로닉스 주식회사 | Method for forming metal wiring layer of semiconductor device |
| KR100905872B1 (en) | 2007-08-24 | 2009-07-03 | 주식회사 하이닉스반도체 | Method of forming a metal layer in semiconductor device |
| US7713867B2 (en) | 2007-08-24 | 2010-05-11 | Hynix Semiconductor Inc. | Method for forming a metal line in a semiconductor device |
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