KR100593138B1 - Method of forming a metal wiring in a semiconductor device - Google Patents

Method of forming a metal wiring in a semiconductor device Download PDF

Info

Publication number
KR100593138B1
KR100593138B1 KR1019990061777A KR19990061777A KR100593138B1 KR 100593138 B1 KR100593138 B1 KR 100593138B1 KR 1019990061777 A KR1019990061777 A KR 1019990061777A KR 19990061777 A KR19990061777 A KR 19990061777A KR 100593138 B1 KR100593138 B1 KR 100593138B1
Authority
KR
South Korea
Prior art keywords
film
forming
contact hole
metal wiring
semiconductor device
Prior art date
Application number
KR1019990061777A
Other languages
Korean (ko)
Other versions
KR20010063701A (en
Inventor
정철모
손현철
Original Assignee
주식회사 하이닉스반도체
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 주식회사 하이닉스반도체 filed Critical 주식회사 하이닉스반도체
Priority to KR1019990061777A priority Critical patent/KR100593138B1/en
Publication of KR20010063701A publication Critical patent/KR20010063701A/en
Application granted granted Critical
Publication of KR100593138B1 publication Critical patent/KR100593138B1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
    • H01L21/2855—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System by physical means, e.g. sputtering, evaporation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
    • H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76855—After-treatment introducing at least one additional element into the layer
    • H01L21/76856—After-treatment introducing at least one additional element into the layer by treatment in plasmas or gaseous environments, e.g. nitriding a refractory metal liner
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material

Abstract

본 발명은 반도체 소자의 금속 배선 형성 방법에 관한 것으로, 콘택홀 종횡비가 큰 고집적 메모리 소자에서 콘택 저항이 우수한 C-54 TiSi2 막을 콘택홀 저면을 이루는 실리콘 기판의 접합부에 형성하는데 있어서, C-54 TiSi2 막 형성을 촉진하는 Ta막 형성후 저온 급속 열공정으로 형성함으로써 콘택 저항을 낮추고 비용을 절감할 수 있는 반도체 소자의 금속 배선 형성 방법이 개시된다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a metal wiring of a semiconductor device, wherein a C-54 TiSi 2 film having excellent contact resistance is formed at a junction portion of a silicon substrate forming a contact hole bottom in a highly integrated memory device having a large contact hole aspect ratio. Disclosed is a method of forming a metal wiring of a semiconductor device capable of lowering contact resistance and reducing cost by forming a Ta film that promotes TiSi 2 film formation and then forming the film by a low temperature rapid thermal process.

금속 배선, C-54 TiSi2 막, 오믹 콘택,Metal wiring, C-54 TiSi2 film, ohmic contact,

Description

반도체 소자의 금속 배선 형성 방법 {Method of forming a metal wiring in a semiconductor device} Method of forming a metal wiring in a semiconductor device             

도 1a 내지 도 1c는 본 발명에 다른 반도체 소자의 금속 배선 형성 방법을 설명하기 위한 소자의 단면도.1A to 1C are cross-sectional views of a device for explaining a metal wiring formation method of a semiconductor device according to the present invention.

〈도면의 주요 부분에 대한 부호 설명〉<Description of Signs of Major Parts of Drawings>

1 : 실리콘 기판 2 : 층간 절연막1 silicon substrate 2 interlayer insulating film

3 : 콘택홀 4 : Ta막3: contact hole 4: Ta film

5 : 배리어 메탈층 6 : C-54 TiSi2 막5: barrier metal layer 6: C-54 TiSi 2 film

7 : 금속 배선7: metal wiring

본 발명은 반도체 소자의 금속 배선 형성 방법에 관한 것으로, 특히 금속 콘택 저항을 개선할 수 있는 반도체 소자의 금속 배선 형성 방법에 관한 것이다. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming metal wirings in semiconductor devices, and more particularly, to a method for forming metal wirings in semiconductor devices capable of improving metal contact resistance.

일반적으로, 반도체 소자가 고집적화 되어감에 따라 콘택 저항을 개선시키는 방안이 연구되어지고 있다. 최근 널리 적용되고 있는 콘택 저항 개선방안으로 콘택홀 저면의 콘택 부위에 실리사이드층을 형성하는 방안이 있다. In general, as semiconductor devices are highly integrated, a method of improving contact resistance has been studied. As a method for improving contact resistance, which has been widely applied in recent years, there is a method of forming a silicide layer on a contact portion of a bottom surface of a contact hole.

종래 반도체 소자의 금속 배선 형성 방법은 실리콘 기판 상에 층간 절연막을 형성한 후 실리콘 기판이 노출되도록 콘택홀을 형성한다. 콘택홀이 형성된 전체 구조상에 Ti/TiN을 증착 시켜 배리어 메탈층(barrier metal layer)을 형성한 후, 콘택 저항을 개선시키기 위해 열처리 공정을 실시하여 콘택홀 저면에 실리사이드층을 형성하고, 이후 콘택홀을 금속층으로 매립하여 금속 배선을 형성하였다.In the conventional method of forming a metal wiring of a semiconductor device, a contact hole is formed to expose a silicon substrate after forming an interlayer insulating layer on the silicon substrate. After forming a barrier metal layer by depositing Ti / TiN on the entire structure in which the contact hole is formed, a heat treatment process is performed to improve contact resistance to form a silicide layer on the bottom of the contact hole, and then the contact hole. Was embedded in a metal layer to form a metal wiring.

상기에서, 실리사이드층은 650℃에서 급속 열처리 공정(RTP)으로 형성하며, 이때에 형성된 실리사이드층은 콘택 저항이 우수한 C-54 TiSi2 상이 형성되지 않고 C-49상이나 또는 비정질 Ti-Si 상으로 오믹 콘택이 형성되었다.In the above, the silicide layer is formed by a rapid heat treatment process (RTP) at 650 ℃, the silicide layer formed at this time ohmic to C-49 phase or amorphous Ti-Si phase without forming a C-54 TiSi 2 phase excellent in contact resistance The contact was made.

최근에는 Ti막을 화학적 기상증착(CVD)방법으로 형성하여 C-54 TiSi2 상을 형성하려는 시도가 진행중이나, 증착 온도가 높아서 트랜지스터의 전기적 특성에 영향을 미치거나 누설전류가 증가시키는 문제가 발생하였다. 또한, 화학적 기상증착방법으로 Ti막 형성시 장비에 대한 투자 비용이 발생하는 문제가 있다. Recently, attempts to form a C-54 TiSi 2 phase by forming a Ti film by a chemical vapor deposition (CVD) method are in progress, but the deposition temperature is high to affect the electrical characteristics of the transistor or increase the leakage current. . In addition, there is a problem that the investment cost for the equipment when the Ti film is formed by the chemical vapor deposition method.

따라서, 본 발명은 현재 일반적으로 사용중인 장비를 이용하여 콘택 저항이 우수한 C-54 TiSi2 막을 저온에서 형성하므로써 트랜지스터의 전기적 특성 저하 없 이 콘택 저항을 낮출 수 있어, 메모리 소자의 고집적화를 실현할 수 있을 뿐만 아니라 소자의 수율 및 신뢰성을 향상시키면서 비용도 절감할 수 있는 반도체 소자의 금속 배선 형성 방법을 제공하는데 그 목적이 있다.Therefore, the present invention can form a C-54 TiSi 2 film having excellent contact resistance at low temperature by using the equipment currently in use, thereby lowering the contact resistance without deteriorating the electrical characteristics of the transistor, thereby realizing high integration of the memory device. In addition, it is an object of the present invention to provide a method for forming a metal wiring of a semiconductor device that can reduce costs while improving the yield and reliability of the device.

상기한 목적을 달성하기 위한 본 발명에 따른 반도체 소자의 금속 배선 형성 방법은 실리콘 기판 상에 층간절연막을 형성한 후 상기 실리콘 기판이 노출되도록 콘택홀을 형성하는 단계; 상기 콘택홀을 포함한 전체상부면에 Ta막 및 배리어 메탈층을 형성한 후, 저온급속 열공정을 실시하여 콘택홀 저면의 실리콘 기판에 실리사이드층을 형성하는 단계; 및 상기 콘택홀이 매립되도록 금속층을 증착하고 패터닝하여 금속 배선을 형성하는 단계를 포함하는 것을 특징으로 한다.
According to an aspect of the present invention, there is provided a method of forming a metal wiring of a semiconductor device, the method comprising: forming a contact hole so that the silicon substrate is exposed after forming an interlayer insulating film on a silicon substrate; Forming a Ta film and a barrier metal layer on the entire upper surface including the contact hole, and then performing a low temperature rapid thermal process to form a silicide layer on a silicon substrate on the bottom of the contact hole; And depositing and patterning a metal layer to fill the contact hole to form a metal wiring.

이하, 첨부한 도면을 참조하여 본 발명을 상세히 설명하면 다음과 같다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

도 1a 내지 도 1c는 본 발명에 따른 반도체 소자의 금속 배선 형성 방법을 설명하기 위한 소자의 단면도이다.1A to 1C are cross-sectional views of devices for explaining a method for forming metal wirings of a semiconductor device according to the present invention.

도 1a를 참조하면, 실리콘 기판(1) 상에 층간 절연막(2)을 형성한 후 실리콘 기판(1)이 노출되도록 콘택홀(3)을 형성하고, 콘택홀(3)이 형성된 전체 상부면에 Ta막(4)을 형성한다.Referring to FIG. 1A, after forming the interlayer insulating film 2 on the silicon substrate 1, the contact hole 3 is formed to expose the silicon substrate 1, and the entire upper surface on which the contact hole 3 is formed is formed. A Ta film 4 is formed.

상기에서, Ta막(4)은 물리 기상증착(PVD) 방법으로 5 내지 50Å 두께가 되도록 형성한다.In the above, the Ta film 4 is formed to have a thickness of 5 to 50 kPa by the physical vapor deposition (PVD) method.

도 1b를 참조하면, Ta막(4)이 형성된 전체 상부면에 배리어 메탈층(5)을 형 성한 후, 저온급속 열공정을 실시하여 콘택홀(3) 저면의 실리콘 기판(1)에 실리사이드층인 C-54 TiSi2막(6)을 형성시킨다.Referring to FIG. 1B, after forming the barrier metal layer 5 on the entire upper surface where the Ta film 4 is formed, a low temperature rapid thermal process is performed to form a silicide layer on the silicon substrate 1 at the bottom of the contact hole 3. Phosphorus C-54 TiSi 2 film 6 was formed.

상기에서, 배리어 메탈층(5)은 Ti/TiN막, Ti막 및 TiN막 중 어느 하나로 이루어지며, Ti막 증착시 이온화 금속 플라즈마(IMP)방법을 이용하고, TiN막은 화학기상증착(CVD)방법으로 형성한다. C-54 TiSi2막(6)은 저온급속 열공정에 의해 C-54 TiSi2로 상전이 되어 형성되는데, 이때 저온급속 열공정 온도는 500 내지 700℃의 온도이며, 가장 적당한 온도는 550℃의 온도이다. 열공정 동안 실리콘 기판(1)의 Si가 확산되고, 확산된 Si가 Ta막(4)을 거쳐서 배리어 메탈층(5)의 Ti와 반응하므로 콘택홀(3)의 측벽에서는 반응하지 않고 Ta막(4) 및 배리어 메탈층(5)은 그대로 유지된다.In the above description, the barrier metal layer 5 is formed of any one of a Ti / TiN film, a Ti film, and a TiN film, using an ionized metal plasma (IMP) method for depositing a Ti film, and the TiN film is a chemical vapor deposition (CVD) method. To form. The C-54 TiSi 2 film 6 is formed by phase transition to C-54 TiSi 2 by a low-temperature rapid thermal process, wherein the low-temperature rapid thermal process temperature is a temperature of 500 to 700 ℃, the most suitable temperature of 550 ℃ to be. During the thermal process, the Si of the silicon substrate 1 diffuses, and the diffused Si reacts with Ti of the barrier metal layer 5 through the Ta film 4, and thus does not react on the sidewall of the contact hole 3. 4) and the barrier metal layer 5 remain intact.

일반적으로, C-54상 TiSi2 상전이는 750℃에서 일어난다고 알려져 있으나, 본 발명에서는 이보다 낮은 온도인 500 내지 700℃의 온도에서 상전이 되도록 한다. Ta막(4)을 5~50Å 정도로 얇게 형성하면 C-54상으로 전이되는 것이 촉진되기 때문에 일반적인 상전이 온도보다 200℃ 이상 낮은 급속 열공정(RTP)에서 얻을 수 있다. Ta막(4)이 두껍게 형성되면 상전이 온도가 증가되므로 Ta막(4)을 50Å 이하의 두께로 얇게 형성하는 것이 필수적이다.Generally, the C-54 phase TiSi 2 phase transition is known to occur at 750 ° C., but in the present invention, the phase transition is performed at a temperature of 500 to 700 ° C., which is lower than this. When the Ta film 4 is thinly formed at a thickness of about 5 to 50 kPa, the transition to the C-54 phase is promoted, and therefore, it can be obtained in a rapid thermal process (RTP) lower than the normal phase transition temperature by 200 ° C or more. If the Ta film 4 is formed thick, the phase transition temperature is increased, so it is essential to form the Ta film 4 thin with a thickness of 50 kPa or less.

Ta막(4)을 얇게 형성하는 위하여 현재 64M 급 이상 소자에서 종횡비가 큰 금속 콘택이 스텝 커버리지(step coverage)가 열악해지는 것을 이용한다. 예를 들어 종횡비가 5 내지 10 인 금속 콘택은 스퍼터링(sputtering)에 의한 스텝 커버리지가 10% 이하이므로 5 내지 50Å 두께의 Ta막(3)을 형성하기 위하여 타겟 두께를 100Å 정도하면 콘택홀(3) 내부에서는 충분히 얇은 두께의 Ta막(4)을 얻을 수 있다.In order to form the Ta film 4 thinly, a metal contact having a large aspect ratio is used in the step coverage of the metal contact having a large aspect ratio of 64 M or more devices. For example, a metal contact having an aspect ratio of 5 to 10 has a step coverage of 10% or less due to sputtering, so that when the target thickness is about 100 µs to form a Ta film 3 having a thickness of 5 to 50 µs, the contact hole 3 is formed. Inside, a Ta film 4 having a sufficiently thin thickness can be obtained.

도 1c는 C-54 TiSi2막(6)이 형성된 전체 상부면에 금속층 증착 및 패터닝 공정으로 금속 배선(7)을 형성한 상태의 단면도이다. FIG. 1C is a cross-sectional view of the metal wiring 7 formed by a metal layer deposition and patterning process on the entire upper surface where the C-54 TiSi 2 film 6 is formed.

상기에서, 금속 배선(7)은 Al, Cu 및 W 중 어느 하나로 이루어 진다.In the above, the metal wiring 7 is made of any one of Al, Cu, and W.

상술한 바와 같이, 본 발명은 콘택홀 종횡비가 큰 고집적 메모리 소자에 적용하여 콘택 저항이 우수한 실리사이드층인 C-54 TiSi2층을 형성함으로써 금속 콘택 저항을 종래 보다 1/2 내지 1/3 수준으로 낮출 수 있고, 저온에서 급속 열공정을 실시할 수 있으므로 비용이 절감된다. 또한, 종래 사용하는 배리어막 기술을 그대로 사용하고, 추가 화학기상증착 장비를 도입하지 않아도 됨으로 비용이 절감되는 효과가 있다.As described above, the present invention is applied to a highly integrated memory device having a large contact hole aspect ratio, thereby forming a C-54 TiSi 2 layer, which is a silicide layer having excellent contact resistance, so that the metal contact resistance is 1/2 to 1/3 of the conventional level. The cost can be lowered and the rapid thermal process can be carried out at low temperature. In addition, the barrier film technology used in the prior art is used as it is, and additional chemical vapor deposition equipment does not need to be introduced, thereby reducing the cost.

Claims (5)

실리콘 기판 상에 층간절연막을 형성한 후 상기 실리콘 기판이 노출되도록 콘택홀을 형성하는 단계;Forming a contact hole to expose the silicon substrate after forming an interlayer dielectric layer on a silicon substrate; 상기 콘택홀을 포함한 전체 상부면에 5~50Å의 두께로 Ta막을 형성하는 단계;Forming a Ta film on the entire upper surface including the contact hole with a thickness of about 5 to about 50 microns; 상기 Ta막상에 배리어 메탈층을 형성한 후, 500 내지 700℃에서 저온급속 열공정을 실시하여 콘택홀 저면의 실리콘 기판에 C-54 TiSi2층을 형성하는 단계;Forming a barrier metal layer on the Ta film, and then performing a low temperature rapid thermal process at 500 to 700 ° C. to form a C-54 TiSi 2 layer on the silicon substrate on the bottom of the contact hole; 상기 콘택홀이 매립되도록 금속층을 증착하고 패터닝하여 금속 배선을 형성하는 단계를 포함하는 것을 특징으로 하는 반도체 소자의 금속 배선 형성 방법.And depositing and patterning a metal layer to fill the contact hole, thereby forming a metal wiring. 제 1 항에 있어서,The method of claim 1, 상기 Ta막은 물리기상증착 방법으로 형성하는 것을 특징으로 하는 반도체 소자의 금속 배선 형성 방법.And the Ta film is formed by a physical vapor deposition method. 제 1 항에 있어서,The method of claim 1, 상기 배리어 메탈층은 Ti/TiN막, Ti막 및 TiN막 중 어느 하나를 증착하여 형성하며, 상기 Ti막 증착시 이온화 금속 플라즈마 방법으로 형성하고, 상기 TiN막은 화학기상증착 방법으로 형성하는 것을 특징으로 하는 반도체 소자의 금속 배선 형 성 방법.The barrier metal layer is formed by depositing any one of a Ti / TiN film, a Ti film, and a TiN film, and is formed by an ionized metal plasma method when depositing the Ti film, and the TiN film is formed by a chemical vapor deposition method. Metal wiring formation method of a semiconductor device. 삭제delete 삭제delete
KR1019990061777A 1999-12-24 1999-12-24 Method of forming a metal wiring in a semiconductor device KR100593138B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019990061777A KR100593138B1 (en) 1999-12-24 1999-12-24 Method of forming a metal wiring in a semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019990061777A KR100593138B1 (en) 1999-12-24 1999-12-24 Method of forming a metal wiring in a semiconductor device

Publications (2)

Publication Number Publication Date
KR20010063701A KR20010063701A (en) 2001-07-09
KR100593138B1 true KR100593138B1 (en) 2006-06-26

Family

ID=19629352

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019990061777A KR100593138B1 (en) 1999-12-24 1999-12-24 Method of forming a metal wiring in a semiconductor device

Country Status (1)

Country Link
KR (1) KR100593138B1 (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR950024268A (en) * 1994-01-18 1995-08-21 김광호 Manufacturing Method of Semiconductor Device
KR960039204A (en) * 1995-04-17 1996-11-21 김광호 Metal film wiring formation method
KR970052925A (en) * 1995-12-07 1997-07-29 김광호 High heat-resistant metal wiring structure of semiconductor device and method of forming the same

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR950024268A (en) * 1994-01-18 1995-08-21 김광호 Manufacturing Method of Semiconductor Device
KR960039204A (en) * 1995-04-17 1996-11-21 김광호 Metal film wiring formation method
KR970052925A (en) * 1995-12-07 1997-07-29 김광호 High heat-resistant metal wiring structure of semiconductor device and method of forming the same

Also Published As

Publication number Publication date
KR20010063701A (en) 2001-07-09

Similar Documents

Publication Publication Date Title
US4960732A (en) Contact plug and interconnect employing a barrier lining and a backfilled conductor material
US6284651B1 (en) Method for forming a contact having a diffusion barrier
US20020019127A1 (en) Interconnect structure and method of making
JPS63205951A (en) Stable low resistance contact
US5851921A (en) Semiconductor device and method for forming the device using a dual layer, self-aligned silicide to enhance contact performance
JPH11150087A (en) Forming method of titanium nitride barrier layer and semiconductor device containing titanium nitride barrier layer
JPH09326436A (en) Formation of wiring
KR100459717B1 (en) Method for forming metal contact in semiconductor device
US20060202283A1 (en) Metal silicide adhesion layer for contact structures
KR100402428B1 (en) Method for forming metal line of semiconductor
KR100559028B1 (en) Copper wiring formation method of semiconductor device
KR100593138B1 (en) Method of forming a metal wiring in a semiconductor device
KR100430687B1 (en) Method of forming metal line of semiconductor device for improving anti-diffusion performance and electrical properties
JPH05335330A (en) Embedding-formation of connection hole
US6087259A (en) Method for forming bit lines of semiconductor devices
JPH07176532A (en) Tungsten formation process
KR100914975B1 (en) Method for forming metal plug of semiconductor device
KR100521051B1 (en) Method of forming a metal wiring in a semiconductor device
KR19980057024A (en) Metal wiring formation method of semiconductor device
KR100256238B1 (en) Method of forming metal wiring in semiconductor device
KR100197992B1 (en) Forming method for metal wiring in semiconductor device
KR20000043055A (en) Method for creating bit line of semiconductor device
KR20000027932A (en) Method of manufacturing bit line of semiconductor device
KR100196502B1 (en) Forming method for metal wiring in semiconductor device
KR100358058B1 (en) Method of forming barrier metal layer in a semiconductor device

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20110526

Year of fee payment: 6

LAPS Lapse due to unpaid annual fee