KR20030001860A - Method for forming metal line in semiconductor device - Google Patents
Method for forming metal line in semiconductor device Download PDFInfo
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- KR20030001860A KR20030001860A KR1020010037718A KR20010037718A KR20030001860A KR 20030001860 A KR20030001860 A KR 20030001860A KR 1020010037718 A KR1020010037718 A KR 1020010037718A KR 20010037718 A KR20010037718 A KR 20010037718A KR 20030001860 A KR20030001860 A KR 20030001860A
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- contact hole
- polycrystalline silicon
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
- H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
- H01L21/28052—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a silicide layer formed by the silicidation reaction of silicon with a metal layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76883—Post-treatment or after-treatment of the conductive material
Abstract
Description
본 발명은 반도체 소자의 금속배선 형성 방법에 관한 것으로, 보다 구체적으로는 금속배선간을 연결하는 콘택홀에 실리사이드막을 형성하여 콘택 저항을 줄일 수 있는 반도체 소자의 금속 배선 형성 방법에 관한 것이다.The present invention relates to a method for forming metal wiring of a semiconductor device, and more particularly, to a method for forming metal wiring of a semiconductor device capable of reducing contact resistance by forming a silicide layer in a contact hole connecting metal wirings.
일반적으로 반도체 기판과 배선 사이, 또는, 상·하층 배선 사이를 전기적으로 연결하기 위한 접속 통로로서 콘택홀을 형성하고 있으며, 이러한 콘택홀을 매립하기 위한 금속 배선의 재료로는 전도도가 높고, 경제성이 있는 텅스텐을 주로 사용하고 있다.In general, a contact hole is formed as a connection path for electrically connecting the semiconductor substrate and the wiring, or between the upper and lower layer wirings, and as the material of the metal wiring for filling the contact hole, high conductivity and economical efficiency are achieved. Mainly used tungsten.
도 1은 종래의 상기 콘택홀 매립에 대한 제조공정도이다.1 is a manufacturing process diagram of the conventional contact hole filling.
도시된 바와같이, 층간 절연막(2)이 형성된 실리콘 기판(1)을 제공한다. 이러한 층간 절연막(2)에 실리콘 기판(1) 소정부분을 노출시키는 콘택홀(4)을 형성한다. 이어서, 층간 절연막(2)과의 접착성 향상 및 실리콘(Si)과의 접촉저항을 낮추기 위해 티타늄막(5)을 증착한다. 그런다음, 티타늄막(5)이 증착된 전체 구조 상에 텅스텐을 형성시키기 위해 티타늄 질화막(6)을 증착한다. 이어서, 텅스텐막(8)을 매립한 다음, 도시하지는 않았지만 텅스텐막(8), 티타늄 질화막(6) 및 티타늄막(5)을 블랭킷 에치 백하여 플러그막을 형성한다.As shown, a silicon substrate 1 having an interlayer insulating film 2 formed thereon is provided. A contact hole 4 exposing a predetermined portion of the silicon substrate 1 is formed in the interlayer insulating film 2. Subsequently, a titanium film 5 is deposited to improve adhesion to the interlayer insulating film 2 and to lower contact resistance with silicon (Si). Then, a titanium nitride film 6 is deposited to form tungsten on the entire structure on which the titanium film 5 is deposited. Subsequently, the tungsten film 8 is embedded, and then although not shown, the tungsten film 8, the titanium nitride film 6 and the titanium film 5 are blanket etched back to form a plug film.
그러나, 상기 텅스텐막(8)은 도 2의 투시전자현미경 사진에 도시된 바와같이, 텅스텐막 자체의 특성상 스텝 커버리지(step coverage) 특성이 열악해 보이드가 발생하므로 콘택 저항을 증가시킨다.However, the tungsten film 8 has a poor step coverage characteristic due to the characteristics of the tungsten film itself, as shown in the transmission electron microscope photograph of FIG.
또한, 스퍼터링 방식으로 티타늄막(5) 및 티타늄 질화막(6)을 증착할 경우, 티타늄막(5) 및 티타늄 질화막(6) 또한 스텝 커버리지 특성이 매우 열악하여 상기 티타늄막(5)과 실리콘(Si)과의 반응이 일어나지 않는다. 이에의해 접촉 저항을 낮추는 티타늄 실리사이드막(TiSi4)을 형성하지 못하게 된다. 아울러, 텅스텐막(8) 증착시 이용되는 WF6가스가 스텝 커리지지 특성이 뒤떨어지는 티타늄 질화막(6)을 뚫고 나와 상기 티타늄막(5)과 반응을 함으로써, 도 3에 도시된 투시전자현미경 사진과 같이, 볼케이노(Volcano) 형상과 같이 부피가 팽창된 TiF4(15)가 형성되어 콘택저항을 증가시킨다.In addition, when the titanium film 5 and the titanium nitride film 6 are deposited by sputtering, the titanium film 5 and the titanium nitride film 6 also have very poor step coverage characteristics, so that the titanium film 5 and the silicon (Si) ) Does not occur. As a result, it is impossible to form a titanium silicide layer (TiSi4) that lowers the contact resistance. In addition, the WF 6 gas used in the deposition of the tungsten film 8 penetrates the titanium nitride film 6 having poor step coverage characteristics and reacts with the titanium film 5, thereby providing a perspective electron microscope image shown in FIG. 3. As such, the expanded volume of TiF 4 (15), such as Volcano shape, is formed to increase the contact resistance.
따라서, 상기 문제점을 해결하기 위해 안출된 본 발명의 목적은, 콘택홀 매립시 스텝 커버리지 특성이 좋은 다결정 실리콘막을 이용하여 콘택홀 매립 후 실리사이드로 변형시킴으로써 콘택 저항을 낮출 수 있는 반도체 소자의 금속 배선 형성방법을 제공하는 데 있다.Accordingly, an object of the present invention devised to solve the above problems is to form a metal wiring of a semiconductor device capable of lowering contact resistance by deforming to silicide after filling a contact hole using a polycrystalline silicon film having good step coverage characteristics when filling a contact hole. To provide a way.
도 1은 종래의 반도체 소자의 금속 배선 형성방법을 설명하기 위한 단면도.1 is a cross-sectional view for explaining a metal wiring formation method of a conventional semiconductor device.
도 2 및 도 3은 종래의 반도체 소자의 금속 배선 형성방법의 문제점을 설명하기 위한 투시전자현미경 사진.2 and 3 are perspective electron micrographs for explaining the problem of the conventional method for forming metal wiring of the semiconductor device.
도 4a 내지 도 4c는 본 발명의 반도체 소자의 금속 배선 형성방법을 설명하기 위한 제조공정도.4A to 4C are manufacturing process diagrams for explaining a metal wiring forming method of a semiconductor device of the present invention.
도 5a 내지 도 5c와, 도 6a 내지 도 6c 및, 도 7a 내지 도 7c는 본 발명의 다른 실시예를 설명하기 위한 제조공정도.5A to 5C, 6A to 6C, and 7A to 7C are manufacturing process diagrams for explaining another embodiment of the present invention.
* 도면의 주요 부분에 대한 부호 설명 *Explanation of symbols on the main parts of the drawings
10 : 실리콘 기판10: silicon substrate
12 : 층간 절연막12: interlayer insulation film
14 : 콘택홀14: contact hole
20 : 다결정 실리콘막20: polycrystalline silicon film
22 : 홀(hole)22: hole
30 : 티타늄막30: titanium film
50 : 티타늄 실리사이드막50: titanium silicide film
상기 목적 달성을 위한 본 발명의 반도체 소자의 금속 배선 형성방법은, 기판 상에 절연막을 형성하는 단계; 상기 절연막을 식각하여 콘택홀을 형성하는 단계; 상기 콘택홀과 대응되는 부분에 홀(hole)을 가지는 다결정 실리콘막을 형성하는 단계; 상기 다결정 실리콘막을 식각하여 상기 콘택홀내에만 남도록 하는 단계;및 상기 콘택홀내에 금속막을 증착하여 실리사이드막을 형성시키는 단계를 포함하는 것을 특징으로 한다.Method for forming a metal wiring of the semiconductor device of the present invention for achieving the above object, forming an insulating film on the substrate; Etching the insulating film to form a contact hole; Forming a polycrystalline silicon film having a hole in a portion corresponding to the contact hole; Etching the polycrystalline silicon film so as to remain only in the contact hole; and depositing a metal film in the contact hole to form a silicide film.
또한, 본 발명에 의하면, 기판 상부에 절연막을 형성하는 단계; 상기 절연막을 식각하여 콘택홀을 형성하는 단계; 상기 콘택홀과 대응되는 부분에 홀(hole)을 가지는 다결정 실리콘막을 형성하는 단계; 상기 다결정 실리콘막 상에 금속막을 형성하여 실리사이드막을 형성하는 단계; 및 상기 실리사이드막을 블랭킷 에치 백하여 상기 절연막 표면을 노출시키는 단계를 포함하는 것을 특징으로 한다.In addition, according to the present invention, forming an insulating film on the substrate; Etching the insulating film to form a contact hole; Forming a polycrystalline silicon film having a hole in a portion corresponding to the contact hole; Forming a silicide film by forming a metal film on the polycrystalline silicon film; And blanket etching back the silicide layer to expose the surface of the insulating layer.
또한, 본 발명에 의하면, 기판 상에 절연막을 형성하는 단계; 상기 절연막을 식각하여 콘택홀을 형성하는 단계; 상기 절연막 상부 및 콘택홀내에 금속막을 형성하는 단계; 상기 금속막 상에 다결정 실리콘막을 형성하는 단계; 상기 다결정 실리콘막 및 금속막을 블랭킷 에치 백하여 상기 절연막 표면을 노출시키는 단계; 및 상기 다결정 실리콘막과 금속막을 반응시키는 열처리 공정을 수행하여 실리사이드막을 형성하는 단계를 포함하는 것을 특징으로 한다.In addition, according to the present invention, forming an insulating film on the substrate; Etching the insulating film to form a contact hole; Forming a metal film on the insulating film and in the contact hole; Forming a polycrystalline silicon film on the metal film; Blanket etching back the polycrystalline silicon film and the metal film to expose the surface of the insulating film; And forming a silicide film by performing a heat treatment process for reacting the polycrystalline silicon film and the metal film.
아울러, 본 발명에 의하면, 기판 상에 절연막을 형성하는 단계; 상기 절연막을 식각하여 콘택홀을 형성하는 단계; 상기 절연막 상부 및 콘택홀 내에 금속막을 형성하는 단계; 상기 금속막 상에 다결정 실리콘막을 형성하여 실리사이드막을 형성하는 단계; 및 상기 실리사이드막을 블랭킷 에치 백하여 상기 절연막 표면을 노출시키는 단계를 포함하는 것을 특징으로 한다.In addition, according to the present invention, forming an insulating film on the substrate; Etching the insulating film to form a contact hole; Forming a metal film on the insulating film and in the contact hole; Forming a silicide film by forming a polycrystalline silicon film on the metal film; And blanket etching back the silicide layer to expose the surface of the insulating layer.
이하, 본 발명의 바람직한 실시예를 첨부한 도면을 참조하여 상세히 설명한다.Hereinafter, with reference to the accompanying drawings, preferred embodiments of the present invention will be described in detail.
도 4a 내지 도 4c는 본 발명의 일실시예에 따른 반도체 소자의 금속 배선 형성방법을 설명하기 위한 제조공정도이고, 도 5a 내지 도 5c는 본 발명의 다른 실시에를 설명하기 위한 제조공정도이며, 도 6a 내지 도 6c는 본 발명의 다른 실시예를 설명하기 위한 제조공정도이고, 도 7a 내지 도 7c는 본 발명의 또 다른 실시예를 설명하기 위한 제조공정도이다.4A to 4C are manufacturing process diagrams for explaining a method for forming metal wires of a semiconductor device according to one embodiment of the present invention, and FIGS. 5A to 5C are manufacturing process diagrams for explaining another embodiment of the present invention. 6A to 6C are manufacturing process diagrams for explaining another embodiment of the present invention, and FIGS. 7A to 7C are manufacturing process diagrams for explaining another embodiment of the present invention.
여기서, 실리콘 기판과 배선 사이, 또는 상·하층 배선 사이를 전기적으로 연결하기 위한 접속 통로인 콘택홀 중 실리콘 기판과 배선 사이를 연결하는 콘택홀을 예를 들어 설명한다. 또한, 이하의 동일 구성에 있어서의 도면 부호는 동일하게 한다.Here, the contact hole which connects between a silicon substrate and wiring among the contact holes which are connection paths for electrically connecting between a silicon substrate and wiring or between upper and lower wiring is demonstrated to an example. In addition, the code | symbol in the following same structure is made the same.
먼저, 도 4a에 도시된 바와같이, 층간 절연막(12)이 형성된 실리콘 기판(10)을 제공한다. 이어서, 상기 층간 절연막(12)상에 콘택홀 형성 영역을 한정하는 감광막 패턴(미도시)을 형성한 다음, 상기 감광막 패턴을 식각 장벽으로 층간 절연막(12)을 식각하여 콘택홀(14)을 형성한다.First, as shown in FIG. 4A, a silicon substrate 10 having an interlayer insulating film 12 formed thereon is provided. Subsequently, a photoresist pattern (not shown) defining a contact hole forming region is formed on the interlayer insulating layer 12, and then the interlayer insulating layer 12 is etched using the photoresist pattern as an etch barrier to form a contact hole 14. do.
그 다음, 도 4b에 도시된 바와같이, 상기 콘택홀(14)이 형성된 기판 전면에 소정의 홀(hole)(22)을 구비하는 다결정 실리콘막(20)을 형성한다. 여기서, 다결정 실리콘막(20)은 단차피복성, 즉 스텝 커버리지(step coverage)가 우수하며, 바람직하게는 사이드 월(side wall) 방향으로 70 ~ 100% 범위의 스텝 커버리지를 갖는다. 또한, 상기 홀(22)은 바람직하게 100 ~ 1000Å의 공간을 가지며, 이후 티타늄막 증착시 이 홀(22)을 통해 증착된다. 이러한 다결정 실리콘막(20)은 화학증기증착법에 의해 형성되며, 그 때의 증착 온도는 바람직하게 400 ~ 700℃ 범위로 한다.Next, as shown in FIG. 4B, a polycrystalline silicon film 20 having predetermined holes 22 is formed on the entire surface of the substrate on which the contact holes 14 are formed. Here, the polycrystalline silicon film 20 is excellent in step coverage, that is, step coverage, and preferably has a step coverage in the range of 70 to 100% in the side wall direction. In addition, the hole 22 preferably has a space of 100 to 1000 mW, and is then deposited through the hole 22 when the titanium film is deposited. The polycrystalline silicon film 20 is formed by chemical vapor deposition, and the deposition temperature at that time is preferably in the range of 400 to 700 占 폚.
이어서, 도 4c에 도시된 바와같이, 상기 다결정 실리콘막(20)을 블랭킷 에치 백하여 콘택홀(14) 내에만 다결정 실리콘막(20)이 남도록 한다. 그런다음, 상기 단계까지의 결과물상에 금속막을 증착하여 상기 콘택홀(14)에 실리사이드막을 형성한다. 이때, 상기 금속막은 티타늄막(Ti), 코발트막(Co), 텅스텐막(W) 또는 백금막(pt) 등 중 어느 하나를 선택하며 바람직하게는 티타늄막(Ti)으로 형성한다.Next, as shown in FIG. 4C, the polycrystalline silicon film 20 is blanket etched back so that the polycrystalline silicon film 20 remains only in the contact hole 14. Then, a metal film is deposited on the resultant up to the step to form a silicide film in the contact hole (14). In this case, the metal film may be any one selected from titanium film (Ti), cobalt film (Co), tungsten film (W), platinum film (pt), and the like, and is preferably formed of titanium film (Ti).
상기 티타늄막은 TiCl4가스와 NH3가스가 여기된 챔버내에서 700 ~ 1000℃의 고온에서 증착되는데, 상기 다결정 실리콘(20)의 키 홀(22)을 통하여 다결정 실리콘(20)과 반응시킴으로써 티타늄 실리사이드막(C54 TiSi2)(50)을 형성시킨다.The titanium film is deposited at a high temperature of 700 to 1000 ° C. in a chamber in which TiCl 4 gas and NH 3 gas are excited. The titanium silicide is reacted with the polycrystalline silicon 20 through the key hole 22 of the polycrystalline silicon 20. A film (C54 TiSi 2 ) 50 is formed.
또한, 상기 티타늄막 증착을 500 ~ 700℃의 저온에서 증착한 다음, 700 ~ 1000℃ 범위의 추가 어닐링을 실시하여 티타늄 실리사이드막(C54 TiSi2)(50)을 형성할 수도 있다. 이때, 상기 TiCl4가스는 10 ~ 60 sccm의 유량을 이용함이 바람직하다.In addition, the titanium film may be deposited at a low temperature of 500 to 700 ° C., followed by further annealing in the range of 700 to 1000 ° C. to form a titanium silicide layer (C54 TiSi 2 ) 50. At this time, the TiCl 4 gas is preferably used a flow rate of 10 ~ 60 sccm.
이러한 콘택홀(14)상에 형성되는 티타늄 실리사이드막(50)은 종래의 텅스텐에 비해 단차피복성이 우수하고 콘택 저항을 줄일 수 있어 안정적인 금속 배선을 형성할 수 있다.The titanium silicide layer 50 formed on the contact hole 14 has superior step coverage compared to conventional tungsten and can reduce contact resistance, thereby forming stable metal wiring.
그 다음, 도 5a 내지 도 5c는 본 발명의 다른 실시예를 설명하기 위한 제조공정도이다.5A to 5C are manufacturing process diagrams for explaining another embodiment of the present invention.
먼저, 도 5a에 도시된 바와같이, 층간 절연막(12)이 형성된 실리콘 기판(10)을 제공한다. 이어서, 도 4a에서와 같이 상기 층간 절연막(12) 상에 콘택홀(14)을형성한다. 그리고나서, 도 4b에서와 같이 콘택홀(14)상에 다결정 실리콘막(20)을 형성한다.First, as shown in FIG. 5A, a silicon substrate 10 having an interlayer insulating film 12 formed thereon is provided. Next, as shown in FIG. 4A, a contact hole 14 is formed on the interlayer insulating layer 12. Then, a polycrystalline silicon film 20 is formed on the contact hole 14 as shown in FIG. 4B.
이어서, 도 5b를 참조하여, 도 4c에서와 같이 고온에서 상기 다결정 실리콘막(20)과 티타늄막을 반응시켜 티타늄 실리사이드막(50)을 형성한다.Next, referring to FIG. 5B, the titanium silicide film 50 is formed by reacting the polycrystalline silicon film 20 with the titanium film at a high temperature as shown in FIG. 4C.
그런다음, 도 5c에 도시된 바와같이, 상기 티타늄 실리사이드막(50)을 블랭킷 에치 백하여 층간 절연막(20) 표면을 노출시킨다.Then, as illustrated in FIG. 5C, the titanium silicide layer 50 is blanket etched back to expose the surface of the interlayer dielectric layer 20.
그 다음, 도 6a 내지 도 6c는 본 발명의 다른 실시예를 설명하기 위한 제조공정도이다.6A to 6C are manufacturing process diagrams for explaining another embodiment of the present invention.
도 6a를 참조하여, 도 4a에서와 같이 층간 절연막(12)상에 콘택홀(14)을 형성한다. 그 다음, 콘택홀(14)이 형성된 기판 전면에 금속막을 형성한다. 이때, 상기 금속막은 티타늄막(Ti), 코발트막(Co), 텅스텐막(W) 또는 백금막(pt) 등 중 어느 하나를 선택하며 바람직하게는 티타늄막(Ti)(30)으로 형성하며, 그 조건은 도 4c에서와 설명된 바와같다.Referring to FIG. 6A, a contact hole 14 is formed on the interlayer insulating layer 12 as in FIG. 4A. Next, a metal film is formed over the entire surface of the substrate on which the contact holes 14 are formed. At this time, the metal film is any one selected from titanium film (Ti), cobalt film (Co), tungsten film (W) or platinum film (pt), preferably formed of a titanium film (Ti) (30), The condition is as described in FIG. 4C.
이어서, 도 6b에 도시된 바와같이, 상기 다결정 실리콘막(22) 및 티타늄막(30)을 블랭킷 에치 백하여 층간 절연막(12) 표면을 노출시킨다.Subsequently, as shown in FIG. 6B, the polycrystalline silicon film 22 and the titanium film 30 are blanket etched back to expose the surface of the interlayer insulating film 12.
그 다음, 도 6c에 도시된 바와같이, 콘택홀(14)내에 적층된 티타늄막(30) 및 다결정 실리콘막(22)에 어닐링 공정을 실시하여 티타늄 실리사이드막(50)을 형성한다. 이때, 상기 어닐링은 700 ~ 1000℃ 온도로 실시됨이 바람직하다.Next, as shown in FIG. 6C, an annealing process is performed on the titanium film 30 and the polycrystalline silicon film 22 stacked in the contact hole 14 to form a titanium silicide film 50. At this time, the annealing is preferably carried out at a temperature of 700 ~ 1000 ℃.
또한, 도 7a 내지 도 7c는 본 발명의 또 다른 실시예를 설명하기 위한 제조공정도이다.7A to 7C are manufacturing process diagrams for describing still another embodiment of the present invention.
도 7a를 참조하여, 도 6a에서와 같이 콘택홀(14)상에 티타늄막(30)을 증착한다. 이어서, 도 7b에 도시된 바와같이, 티타늄막(30)이 형성된 전체구조상에 다결정 실리콘막을 증착하여 티타늄 실리사이드막(50)을 형성한다. 이때 다결정 실리콘막의 증착 온도를 바람직하게 700 ~ 1000℃의 범위로 하여 다결정 실리콘막 증착시 티타늄막(30)과 반응시켜 티타늄 실리사이드막(50)을 형성한다.Referring to FIG. 7A, a titanium film 30 is deposited on the contact hole 14 as in FIG. 6A. Subsequently, as shown in FIG. 7B, a polysilicon film is deposited on the entire structure on which the titanium film 30 is formed to form a titanium silicide film 50. At this time, the deposition temperature of the polycrystalline silicon film is preferably in the range of 700 to 1000 ° C to react with the titanium film 30 during the deposition of the polycrystalline silicon film to form the titanium silicide film 50.
또한, 다결정 실리콘막의 증착 온도를 500 ~ 700℃에서 증착한 다음, 700 ~ 1000℃의 추가 어닐링을 수행하는 것을 더 포함하여 상기 티타늄 실리사이드막(50)을 형성할 수도 있다.In addition, the titanium silicide layer 50 may be further formed by further depositing a deposition temperature of the polycrystalline silicon layer at 500 to 700 ° C. and then performing an additional annealing at 700 to 1000 ° C.
이어서, 도 7c에 도시된 바와같이, 티타늄 실리사이드막(50)을 블랭 킷 에치 백하여 층간절연막(12)을 노출시킨다.Subsequently, as shown in FIG. 7C, the titanium silicide film 50 is blanket etched back to expose the interlayer insulating film 12.
상술한 실시예에서는 실리콘 기판과 배선 사이를 연결하는 콘택홀를 예를 들어 설명하였지만, 상·하층 배선 사이를 전기적으로 연결하기 위한 접속 통로인 콘택홀, 예컨대, 반도체 소자의 캐패시터에 있어서 상부 전극과 하부 전극을 연결하는 콘택홀에도 적용할 수 있다.In the above-described embodiment, a contact hole connecting the silicon substrate and the wiring has been described as an example. However, the upper electrode and the lower portion of the contact hole, for example, a capacitor of the semiconductor element, are connection holes for electrically connecting the upper and lower wirings. The present invention can also be applied to contact holes connecting electrodes.
한편, 이상에서 설명한 본 발명은 상술한 실시예 및 첨부된 도면에 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.On the other hand, the present invention described above is not limited to the above-described embodiment and the accompanying drawings, it is possible that various substitutions, modifications and changes within the scope without departing from the technical spirit of the present invention. It will be apparent to those of ordinary skill in Esau.
상술한 본 발명의 반도체 소자의 금속 배선 형성방법은, 금속 배선에서의 콘택홀(14)을 매립할 경우 스텝 커버리지가 우수한 다결정 실리콘막을 형성한 후 콘택홀(14)내에 다결정 실리콘막(20)과 티타늄막을 반응시켜 티타늄 실리사이드막(50)을 형성시킴으로써 종래의 텅스텐막 매립시의 보이드를 제거할 수 있으며, 이에의해 콘택 저항을 감소시킬 수 있을 뿐만 아니라 텅스텐 증착시의 볼케이노(volcano) 영향을 방지할 수 있다.The metal wiring forming method of the semiconductor element of the present invention described above forms a polycrystalline silicon film having excellent step coverage when the contact hole 14 is embedded in the metal wiring, and then the polycrystalline silicon film 20 is formed in the contact hole 14. By forming the titanium silicide film 50 by reacting the titanium film, voids in the conventional tungsten film buried can be removed, thereby not only reducing contact resistance but also preventing volcano effects during tungsten deposition. Can be.
또한, 기존의 폴리 실리콘막 콘택 플러그에 비해 금속 배선 저항을 낮출 수 있다.In addition, the metal wiring resistance can be lowered as compared with the conventional polysilicon contact plug.
Claims (15)
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| KR20200006024A (en) * | 2015-09-28 | 2020-01-17 | 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 | Semiconductor device and manufacturing method thereof |
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| JPH01270333A (en) * | 1988-04-22 | 1989-10-27 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPH07221096A (en) * | 1994-01-24 | 1995-08-18 | Lg Semicon Co Ltd | Silicide plug formation |
| KR19990012242A (en) * | 1997-07-28 | 1999-02-25 | 윤종용 | Contact structure of semiconductor device and method of forming the same |
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2001
- 2001-06-28 KR KR1020010037718A patent/KR20030001860A/en not_active Application Discontinuation
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01270333A (en) * | 1988-04-22 | 1989-10-27 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPH07221096A (en) * | 1994-01-24 | 1995-08-18 | Lg Semicon Co Ltd | Silicide plug formation |
| KR19990012242A (en) * | 1997-07-28 | 1999-02-25 | 윤종용 | Contact structure of semiconductor device and method of forming the same |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20200006024A (en) * | 2015-09-28 | 2020-01-17 | 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 | Semiconductor device and manufacturing method thereof |
| US11127680B2 (en) | 2015-09-28 | 2021-09-21 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and manufacturing method thereof |
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