KR20000027640A - Method of manufacturing semiconductor device - Google Patents

Abstract

PURPOSE: A method of manufacturing a semiconductor device is provided to easily secure electrostatic capacity by preventing the increase of defects by hemispherical silicon grain. CONSTITUTION: A method of manufacturing a semiconductor device comprises the steps of: forming a gate oxidation layer(12), a gate electrode(13), a mask oxidation layer pattern(14), source/drain regions(15) and a spacer(21) on a semiconductor substrate(10); forming a contact plug for a charge store electrode in contact with a portion for a charge store electrode contact in the source/drain regions; sequentially forming a first insulation layer(18) and an etching barrier layer(19) on the entire surface of the structure; forming a first contact hole by sequentially etching the etching barrier layer(19) and the first insulation layer(18) of the portion for a charge store electrode contact hole on the contact plug; forming an insulation spacer(21) on the side wall of the contact hole; forming a second insulation layer(22) on the entire surface; forming a second contact hole(23) for exposing the contact plug by eliminating the portion for a charge store electrode region on the contact plug in the second insulation layer; forming a conductive layer(24) for the charge store electrode on the entire surface of the structure; forming a planarized layer(25) on the entire surface of the structure; separating the charge store electrode, a conductive layer pattern, by sequentially eliminating the planarized layer and the conductive layer on the second insulation layer; eliminating the remaining planarized layer; and forming a dielectric layer and a plate electrode(27) on the resultant structure.

Description

Manufacturing method of semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and in particular, when forming a charge storage electrode of a capacitor, a cylindrical capacitor is formed by appropriately using a chemical mechanical polishing (hereinafter referred to as CMP) and a planarization film. By reopening the charge storage electrode contact in the state where the storage electrode is to be formed, the charge storage electrode is formed only in the region secured above to prevent bridge failure between adjacent electrodes, and increase the process margin by increasing the process margin. The present invention relates to a method for manufacturing a semiconductor device that can improve the reliability of device operation.

Recently, due to the trend toward higher integration of semiconductor devices, it is difficult to form capacitors with sufficient capacitance due to a decrease in cell size. In particular, DRAM devices composed of one MOS transistor and capacitors have a large area in the chip. Reducing the area while increasing the capacity is an important factor for high integration of the DRAM device.

At this time, the capacitor mainly uses an oxide film, a nitride film, or an O-oxide film (oxide-nitride-oxide) film as a dielectric, using polycrystalline silicon as a conductor.

Therefore, the capacitance C of the capacitor is C = (ε ₀ × ε _r × A) / T, where ε ₀ is the permittivity of vacuum, ε _r is the dielectric constant of the dielectric film, and A is the capacitor. In order to increase the capacitance (C) of the capacitor represented by the surface area of the film, T is the thickness of the dielectric film, a material having a high dielectric constant is used as the dielectric, a thin dielectric film is formed, or the surface area of the capacitor is increased. have.

However, all these methods have their own problems.

That is, dielectric materials having high dielectric constants _, such as Ta ₂ O ₅ , TiO ₂ or SrTiO ₃ , have been studied, but reliability and thin film characteristics such as junction breakdown voltage of these materials have not been confirmed. Difficult to apply to a real device, and reducing the thickness of the dielectric film seriously affects the reliability of the capacitor by breaking the dielectric film during device operation.

Furthermore, in order to increase the surface area of the charge storage electrode of the capacitor, a polycrystalline silicon layer is formed in multiple layers, and then formed into a fin structure through which they are connected to each other, or a cylindrical charge storage electrode is formed on the contact. Other methods may be used.

However, in the method of manufacturing a charge storage electrode of a semiconductor device according to the prior art as described above, if the height of the capacitor is increased, it becomes difficult to follow-up processes due to the step, and the area of the device is reduced due to the high integration of the DRAM, making it difficult to secure the capacitance. .

Also, in order to increase cell efficiency, the number of cells per bitline has been designed more than twice as much as before, so the capacitance of the cell capacitor should be further increased, and the usable surface area of the capacitor is decreasing. In the cylindrical capacitor, the effective surface area is increased by increasing the height of the capacitor, decreasing the gap between the charge storage electrodes, and using a hemi-spherical silicon grain (hereinafter referred to as HSG).

In the capacitor of the semiconductor device according to the prior art as described above, due to the reduction in the distance between the charge storage electrodes, the design rules in this part cannot be afforded, resulting in an increase in the failure of bridges between adjacent charge storage electrodes. It is reported that the use is further increased when used, there is a problem that the yield is further reduced.

The present invention is to solve the above problems, an object of the present invention is to first form a plug for the charge storage electrode contact contacting the substrate, and to expose the plug by opening the portion where the charge storage electrode is to be formed with a thick oxide film In this state, the conductive layer for the charge storage electrode is formed on the front surface and connected to the plug, and the conductive layer pattern is formed only in the region defined by the CMP or etch back process to prevent the bridge failure between the adjacent charge storage electrodes. The present invention also relates to a method of manufacturing a semiconductor device, which can prevent an increase in defects, thereby easily securing capacitance, and improving process yield and reliability of device operation.

1A to 1F illustrate a manufacturing process of a semiconductor device according to an embodiment of the present invention.

2A and 2B illustrate a manufacturing process of a semiconductor device according to another embodiment of the present invention.

3 is a cross-sectional view of a semiconductor device formed in accordance with another embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

10 semiconductor substrate 11 device isolation oxide film

12 gate oxide film 13 gate electrode

14 mask oxide film 15 source / drain region

16,21: spacer 17: contact plug

18: first insulating film 19,30: etching barrier layer

20: first contact hole 22: second insulating film

23: second contact hole 24: conductive layer

25 planarization film 26 dielectric film

27: plate electrode

Features of the semiconductor device manufacturing method according to the present invention for achieving the above object,

Forming a gate oxide film, a gate electrode, a mask oxide film pattern, a source / drain region, and a spacer on the semiconductor substrate;

Forming a contact plug for a charge storage electrode in contact with a portion of the source / drain region that is intended as a charge storage electrode contact;

Sequentially forming a first insulating film and an etch barrier layer on the entire surface of the structure;

Forming a first contact hole by sequentially removing the etch barrier layer and the first insulating layer, which are intended as the charge storage electrode contact holes on the contact plug, sequentially;

Forming an insulating spacer on sidewalls of the contact hole;

Forming a second insulating film on the entire surface of the structure;

Forming a second contact hole exposing the contact plug by removing a portion of the second insulating layer, which is defined as the charge storage electrode region on the contact plug;

Forming a conductive layer for a charge storage electrode on the entire surface of the structure;

Forming a planarization film on the entire surface of the structure;

Sequentially removing the planarization layer and the conductive layer on the second insulating layer to separate the conductive layer patterns serving as charge storage electrodes;

Removing the remaining planarization film;

A process of forming a dielectric film and a plate electrode on the structure is provided.

Hereinafter, a method of manufacturing a fine pattern of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.

1A to 1F are diagrams illustrating a manufacturing process of a semiconductor device according to an embodiment of the present invention.

First, an isolation oxide layer 11 is formed on the semiconductor substrate 10, and the gate oxide layer 12, the gate electrode 13, the mask oxide layer 14 pattern, the source / drain regions 15, and the spacers 16 are formed. Are formed in order and the doped polysilicon layer, ruthenium oxide film, tungsten, or the like is connected to the charge storage electrode contact plug 17 which is in contact with the portion of the source / drain region 15 which is intended as the charge storage electrode contact. After forming by doping with PoCl ₃ doping or ion implantation, the first insulating layer 18 is formed on the entire surface of the structure by using a Tetra Ortho Silicate (hereinafter referred to as TEOS) oxide, oil, S, or undoped. formed of silicate glass (hereinafter referred to as USG), Phosphor Silicate Glass (hereinafter referred to as PSG), Boro Phosphor Silicate Glass (hereinafter referred to as BPSG), or mesophilic oxide film Planarization, and the etch barrier layer 19 on the oxynitride layer A material such as a nitride film is formed to a thickness on the order of 50~1000Å. (See FIG. 1A).

Thereafter, the etch barrier layer 19 and the first insulating layer 18 on the portion scheduled as the charge storage electrode contact hole on the contact plug 17 are sequentially removed to form the first contact hole 20. After the etching barrier layer 19 has a thickness of 50 kPa or more, an insulating spacer 21 made of a nitride film is formed on the sidewall of the first contact hole 20 and insulated from other wirings, and then TEOS is formed on the entire surface of the structure. The second insulating film 22 is formed of an oxide film, a USG film, a PSG film, a BPSG film, a medium temperature oxide film, or the like. At this time, the height of the second insulating layer 22 determines the height of the charge storage electrode formed later. (See FIG. 1B).

Thereafter, the second contact hole exposing the contact plug 17 is removed by removing a portion of the second insulating layer 22, which is intended as the charge storage electrode region on the contact plug 17, using the charge storage electrode mask. 23). In this case, the etch barrier layer 19 is etched with the second insulating layer 22 under high etching selectivity. (See FIG. 1C).

After the process, a natural oxide film or an impurity remaining in the contact base may be removed by a wet etching method, and a polysilicon layer, W or ruthenium doped with an impurity doped conductive layer 24 for the charge storage electrode on the entire surface of the structure. It is formed of a conductive material such as an oxide film, and a planarization film 25 made of an oxide film material or a photosensitive film material is formed on the entire surface of the structure. (See FIG. 1D).

After that, the planarization layer 25 is removed by CMP or etch back to remove the planarization layer 25 and the conductive layer 24 on the second insulating layer 22 and separate the charge storage electrode. (24) After the patterns are separated (see FIG. 1E), the remaining portions of the second insulating film 22 pattern are removed, and an oxide film, a nitride film, a nitride film / oxide film, an oxide film / nitride film / oxide film is formed on the entire surface of the structure. And a dielectric film 26 made of TaO ₅ or PZT, or the like, and a doped polysilicon layer or plate electrode 27 made of W, Ti, TiN or TiW is formed to form a capacitor. The surface of the conductive layer 24 pattern may be increased by HSG, and the first insulating layer 18 may be formed by the etching barrier layer 19 and the spacer 21 during the second insulating layer 22 pattern removing process. ) Is protected and not damaged. (See FIG. 1F).

By the above method, the charge storage electrodes can be reliably separated from each other.

2A and 2B are diagrams illustrating a manufacturing process of a semiconductor device according to another exemplary embodiment of the present invention, in which a first contact hole 20 is formed after the process of FIG. 1A, and a separate etching barrier is formed on the front surface instead of the insulating spacer 21. A layer 30 is formed (see FIG. 2A), a second insulating film 22 is formed, and a second contact hole 23 is formed to expose the contact plug 17 (see FIG. 2B), Subsequent processes proceed to form the capacitor.

3 is a cross-sectional view of a semiconductor device formed in accordance with another embodiment of the present invention. A third insulating film (not shown) made of an oxide film or the like is formed on the etching barrier layer 19 after the process of FIG. 1A, and an insulating spacer (21) forming, forming second insulating film 22, forming second contact hole 23, forming conductive layer 24 and planarizing film 25, separating conductive layer 24, removing residual planarizing film 25, and The insulating layer is removed to form an undercut under the conductive layer 24 pattern to maximize the surface area of the exposed conductive layer 24 pattern, and then the dielectric layer 26 and the entire surface of the exposed conductive layer 24 pattern are formed. The plate electrode 27 is formed.

As described above, in the method of manufacturing a semiconductor device according to the present invention, after forming a contact plug connected to a source / drain region and applying an insulating film for determining the height of the charge storage electrode, the insulating film is transferred from the insulating film to the charge storage electrode region. Remove the predetermined part to form a contact hole exposing the contact plug, and remove the conductive layer on the insulating film pattern in the state that the conductive layer is applied on the entire surface, to separate the conductive layer patterns, and to proceed with the subsequent process Since the bridge of the charge storage electrode is prevented, and the bridge failure of the charge storage electrode does not increase even if the HSG process is performed to increase the effective surface area of the charge storage electrode, the process yield and the reliability of device operation can be improved. There is an advantage to that.

Claims (16)

Forming a gate oxide film, a gate electrode, a mask oxide film pattern, a source / drain region, and a spacer on the semiconductor substrate; Forming a contact plug for a charge storage electrode in contact with a portion of the source / drain region that is intended as a charge storage electrode contact; Sequentially forming a first insulating film and an etch barrier layer on the entire surface of the structure; Forming a first contact hole by sequentially removing the etch barrier layer and the first insulating layer, which are intended as the charge storage electrode contact holes on the contact plug, sequentially; Forming an insulating spacer on sidewalls of the contact hole; Forming a second insulating film on the entire surface of the structure; Forming a second contact hole exposing the contact plug by removing a portion of the second insulating layer, which is defined as the charge storage electrode region on the contact plug; Forming a conductive layer for a charge storage electrode on the entire surface of the structure; Forming a planarization film on the entire surface of the structure; Sequentially removing the planarization layer and the conductive layer on the second insulating layer to separate the conductive layer patterns serving as charge storage electrodes; Removing the remaining planarization film; And forming a dielectric film and a plate electrode on the structure. The method of claim 1, wherein the contact plug for the charge storage electrode is formed of one material arbitrarily selected from the group consisting of a doped polycrystalline silicon layer, a ruthenium oxide film, and tungsten. The method of manufacturing a semiconductor device according to claim 1, wherein the first insulating film is formed of one material arbitrarily selected from the group consisting of a TEOS oxide film, a USG film, a PSG film, a BPSG film, and a medium temperature oxide film. The method of claim 1, wherein the etching barrier layer is formed of an oxynitride layer or a nitride layer to have a thickness of 50 to 1000 μm. The method of claim 1, wherein the thickness of the etch barrier layer remaining after the formation of the first contact hole is 50 kV or more. The method of claim 1, wherein the insulating spacer formed on the sidewall of the first contact hole is formed of a nitride film. The method of manufacturing a semiconductor device according to claim 1, wherein the second insulating film is formed of one material arbitrarily selected from the group consisting of a TEOS oxide film, a USG film, a PSG film, a BPSG film, and a medium temperature oxide film. The method of claim 1, further comprising removing a natural oxide film or impurities that may remain in the contact base part by the wet etching method after the second contact hole is formed. 2. The method of claim 1, wherein the conductive layer is formed of one material arbitrarily selected from the group consisting of an impurity doped polysilicon layer, W, and a ruthenium oxide film. The method of manufacturing a semiconductor device according to claim 1, wherein the planarization film is formed of an oxide film or a photosensitive film. The method of manufacturing a semiconductor device according to claim 1, wherein said planarization film removal and conductive layer patterning are performed by a CMP or etch back method. The method of manufacturing a semiconductor device according to claim 1, wherein the dielectric film is formed of one material arbitrarily selected from the group consisting of oxide film, nitride film, nitride film / oxide film, oxide film / nitride film / oxide film, TaO ₅ and PZT. The method of claim 1, wherein the plate electrode is formed of one material arbitrarily selected from the group consisting of a doped polycrystalline silicon layer, W, Ti, TiN, and TiW. The method of manufacturing a semiconductor device according to claim 1, further comprising the step of increasing the surface area of the conductive layer pattern by an HSG method. Forming a gate oxide film, a gate electrode, a mask oxide film pattern, a source / drain region, and a spacer on the semiconductor substrate; Forming a contact plug for a charge storage electrode in contact with a portion of the source / drain region that is intended as a charge storage electrode contact; Sequentially forming a first insulating film and a first etch barrier layer on the entire surface of the structure; Forming a first contact hole by sequentially removing the first etch barrier layer and the first insulating layer, which are intended as the charge storage electrode contact holes on the contact plug; Sequentially forming a second etching barrier layer and a second insulating film on the entire surface of the structure; Forming a second contact hole exposing the contact plug by removing a portion of the second insulating layer, which is defined as the charge storage electrode region on the contact plug, wherein the second etching barrier layer becomes a spacer of the first contact hole; , Forming a conductive layer for a charge storage electrode on the entire surface of the structure; Forming a planarization film on the entire surface of the structure; Sequentially removing the planarization layer and the conductive layer on the second insulating layer to separate the conductive layer patterns serving as charge storage electrodes; Removing the remaining flattening film; And forming a dielectric film and a plate electrode on the structure. Forming a gate oxide film, a gate electrode, a mask oxide film pattern, a source / drain region, and a spacer on the semiconductor substrate; Forming a contact plug for a charge storage electrode in contact with a portion of the source / drain region that is intended as a charge storage electrode contact; Sequentially forming a first insulating film, an etching barrier layer and an oxide film on the entire surface of the structure; Forming a first contact hole by sequentially removing an oxide film, an etch barrier layer, and a first insulating layer, which are intended as a charge storage electrode contact hole on the contact plug; Forming a second insulating film on the entire surface of the structure; Forming a second contact hole exposing the contact plug by removing a portion of the second insulating layer, which is defined as the charge storage electrode region on the contact plug; Forming a conductive layer for a charge storage electrode on the entire surface of the structure; Forming a planarization film on the entire surface of the structure; Sequentially removing the planarization layer and the conductive layer on the second insulating layer to separate the conductive layer patterns serving as charge storage electrodes; Removing the remaining planarization film; Removing the oxide film using an etching method having an etching selectivity with an etch barrier layer to form an undercut under the conductive layer pattern; And forming a dielectric film and a plate electrode on the structure.