KR20000027616A - Method of manufacturing semiconductor device - Google Patents
Method of manufacturing semiconductor device Download PDFInfo
- Publication number
- KR20000027616A KR20000027616A KR1019980045571A KR19980045571A KR20000027616A KR 20000027616 A KR20000027616 A KR 20000027616A KR 1019980045571 A KR1019980045571 A KR 1019980045571A KR 19980045571 A KR19980045571 A KR 19980045571A KR 20000027616 A KR20000027616 A KR 20000027616A
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- Prior art keywords
- forming
- semiconductor device
- ion implantation
- threshold voltage
- film
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823892—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
Abstract
Description
본 발명은 반도체소자 제조방법에 관한 것으로, 특히 문턱전압을 안정화시킬수 있도록 하는 반도체소자 제조방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device to stabilize the threshold voltage.
일반적으로 반도체 소자에 널리 사용되는 CMOS 트랜지스터(Transistor) 제조방법에서는 트랜지스터 특성을 최적화시키기 위해 이온주입 공정을 한다. 특히 pMOS는 일반적으로 버리드 채널(Buried Channel) 구조가 이용되며 nMOS에 비해 후속 공정에 의해 영향을 많이 받기 때문에 초기 공정에서 문턱전압(Threshold Voltage)을 결정하는데 있어서 안정된 공정을 하는 것이 중요하다.In general, a CMOS transistor manufacturing method widely used in semiconductor devices performs an ion implantation process to optimize transistor characteristics. In particular, since pMOS generally uses a buried channel structure and is more affected by subsequent processes than nMOS, it is important to have a stable process in determining threshold voltage in the initial process.
pMOS 트랜지스터를 종래 기술에 의해 제조하는 공정을 첨부된 도1 내지 도3을 참조하여 설명하기로 한다.A process for manufacturing a pMOS transistor according to the prior art will be described with reference to FIGS.
도1은 실리콘 기판(1)의 필드영역에 소자분리막(2)을 열산화 공정에 의해 형성한다음, well 형성을 위해 산화막으로된 희생막(3)을 형성한 것이다.FIG. 1 shows that a device isolation film 2 is formed in a field region of a silicon substrate 1 by a thermal oxidation process, and then a sacrificial film 3 made of an oxide film is formed to form wells.
도2는 n/p-type well 을 형성하기 위해 마스크로 이용되는 감광막(4)을 형성한 단면도이다.FIG. 2 is a cross-sectional view of the photosensitive film 4 used as a mask to form n / p-type wells.
도3은 n/p type 불순물을 기판으로 이온 주입하여 well 을 형성한다음, 상기 감광막(4)을 제거한 것을 도시한 단면도이다. 이와같이 마스크로 이용되는 감광막을 형성하고, 이온주입 공정을 진행한다음, 상기 감광막을 제거하는 공정을 여러번 거치는 동안 상기 희생막(3)의 표면이 울퉁불퉁하게 변하게 되며 이후에 문턱전압을 맞추기 위해 p-채널 문턱전압 이온주입(5) 공정을 진행하게 된다FIG. 3 is a cross-sectional view showing that the photoresist film 4 is removed after ion implantation of n / p type impurities into the substrate to form wells. In this way, the photoresist film used as a mask is formed, the ion implantation process is performed, and then the surface of the sacrificial film 3 is unevenly changed during the process of removing the photoresist film several times. Channel Threshold Ion Implantation (5)
그러나 일반적인 CMOS 공정에서는 희생막 형성후 n/p-type well 을 형성하기 위해 마스크(Mask) 공정과 이온 주입 공정 그리고 감광막제거(P/R Strip) 공정을 하며 감광막 제거 공정에 들어가는 왯 크리닝(Wet Cleaning) 공정에서 희생막이 조금씩 제거되면서 최종적으로 채널 문턱 전압 (Channl Vt) 이온 주입시에는 희생막의 두께가 불균일하게 된다. 특히 보통 Channel Vt 이온주입시 에너지(Energy)가 작아 Rp가 작으므로 이에 의한 문턱전압이 웨이퍼의 위치에 따라 심한 차이를 보이게 된다.However, in general CMOS process, mask cleaning, ion implantation, and P / R strip process are performed to form n / p-type well after sacrificial film formation. As the sacrificial film is removed little by little in the) process, the thickness of the sacrificial film becomes uneven when the channel threshold voltage (Channl Vt) is finally implanted. In particular, the channel voltage due to the implantation of Vt ion is small and the Rp is small. Therefore, the threshold voltage caused by this is very different depending on the position of the wafer.
따라서, 본 발명은 상기한 문제점인 문턱전압을 안정화 시키기 위한 공정 방법을 제공하는데 그 목적이 있다.Accordingly, an object of the present invention is to provide a process method for stabilizing a threshold voltage, which is the above problem.
도 1 내지 도 3은 종래 기술에 의해 MOS 트랜지스터를 제조하는 공정을 도시한 단면도이다.1 to 3 are cross-sectional views showing a process for manufacturing a MOS transistor according to the prior art.
도 4 내지 도 7은 본 발명에 의해 MOS 트랜지스터를 제조하는 공정을 도시한 단면도이다.4 to 7 are cross-sectional views showing a process for manufacturing a MOS transistor according to the present invention.
<도면의 주요부분에 대한 부호 설명><Description of Signs of Major Parts of Drawings>
1, 11 : 기판 2, 12 : 소자분리막1, 11 substrate 2, 12 device isolation film
3, 13 : 희생막 4 : 감광막3, 13: sacrificial film 4: photosensitive film
5, 15 : 이온 주입 14 : 희생막5, 15: ion implantation 14: sacrificial film
상기 목적을 달성하기 위한 본 발명은 반도체소자 제조방법에 있어서,The present invention for achieving the above object in the semiconductor device manufacturing method,
실리콘 기판의 필드영역에 소자분리막을 형성하는 단계와,Forming an isolation layer in the field region of the silicon substrate;
희생막을 형성하는 단계와,Forming a sacrificial layer,
감광막 마스크를 이용한 이온 주입 공정으로 원하는 기판 지역에 well 영역을 형성하는 단계와,Forming a well region in a desired substrate region by an ion implantation process using a photoresist mask;
상기 공정에서 표면이 균일하지 않게 된 희생막을 제거하는 단계와,Removing the sacrificial film whose surface is uneven in the process;
희생막을 다시 형성한다음, 문턱전압을 조절하기 위한 이온 주입 공정을 진행하는 것을 포함하는 것을 특징으로 한다.After the sacrificial layer is formed again, the ion implantation process for adjusting the threshold voltage is performed.
상기 well 을 형성하기 위해 이온 주입 공정을 실시한다음 고온에서 well 어닐을 하면서 희생막으로 산화막을 형성한다.An ion implantation process is performed to form the wells, and then an oxide film is formed as a sacrificial film while well annealing at a high temperature.
그리고, 상기 문턱전압 조절 이온주입은 20-50KeV의 에너지에서 실시하며, 상기 희생막은 80-100Å의 두께로 형성한다.The threshold voltage control ion implantation is performed at an energy of 20-50 KeV, and the sacrificial film is formed to a thickness of 80-100 kW.
본발명은 문턱전압 조절 이온 주입전 well 어닐(Anneal) 공정시 기존의 희생막을 크리닝 과정에서 제거하고 well 어닐 과정과 동시에 희생막을 고르게 생장시켜 P-채널 문턱전압 조절 이온주입시 Rp값을 고르게 조절할 수 있어 추가되는 공정없이 pMOS의 문턱전압을 안정적으로 할 수 있다.In the present invention, the conventional sacrificial film is removed from the cleaning process during the well annealing process before the threshold voltage control ion implantation, and the sacrificial film is grown evenly at the same time as the well annealing process, thereby controlling the Rp value evenly during the P-channel threshold voltage control ion implantation. As a result, the threshold voltage of the pMOS can be stabilized without an additional process.
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
도4 내지 도7은 본 발명의 실시예에 의해 반조체소자를 형성하는 공정을 도시한 단면도이다.4 to 7 are cross-sectional views showing a process for forming a semi-structured device according to an embodiment of the present invention.
도4는 실리콘 기판(11)의 필드영역에 소자분리막(12)을 열산화 공정에 의해 형성한다음, well 형성을 위해 산화막으로된 희생막(13)을 형성한 것이다.4 shows that the device isolation film 12 is formed in the field region of the silicon substrate 11 by a thermal oxidation process, and then a sacrificial film 13 made of an oxide film is formed to form wells.
도5는 n/p-type well 을 형성하기 위해 마스크로 이용되는 감광막(도시안됨)을 형성한후, n/p type 불순물을 기판으로 이온 주입하여 n 또는 p well (도시안됨)을 형성한다음, 상기 감광막을 제거한 것으로, 상기와 같은 공정을 여러번 거치는 동안 상기 희생막(13)의 표면이 울퉁불퉁하게 변하게 된다.FIG. 5 illustrates the formation of a photoresist film (not shown) used as a mask to form n / p-type wells, followed by ion implantation of n / p type impurities into a substrate to form n or p wells (not shown). By removing the photoresist layer, the surface of the sacrificial layer 13 may be unevenly changed during the above process several times.
도6은 본 발명에 의해 상가 표면이 고르지 않은 희생막(13)을 제거한 단면도이다.6 is a cross-sectional view of the sacrificial film 13 having an uneven top surface removed by the present invention.
도7은 상기 well을 활성화시키기 위하여 고온 예를들어 900-950℃의 온도에서 well 어닐을 하면서 희생막(14)을 다시 형성한다음, MOSFET의 채널을 형성하기 위하여 마스크 공정을 이용하여 n-well 또는 p-well에 p-타입 불순물을 작은 에너지 예를들어 20-50KeV로 이온 주입 공정을 진행한 것을 도시한 단면도이다.Figure 7 re-forms the sacrificial layer 14 while well annealing at a high temperature, e.g. Alternatively, a cross-sectional view showing an ion implantation process of p-type impurities in a p-well with small energy, for example, 20-50 KeV.
상기 p-타입 불순물은 B11 또는 BF2를 이용한다.The p-type impurity uses B11 or BF2.
이후의 공정은 일반적인 공정과 동일한 것으로, 게이트 산화막과 게이트전극을 형성하여 MOS 트랜지스터를 형성한다. 본 발명은 N-MOS, P-MOS에도 함께 적용되는 기술이다.The subsequent process is the same as the general process, and the MOS transistor is formed by forming a gate oxide film and a gate electrode. The present invention is also applied to N-MOS and P-MOS.
본발명에서는 채널 문턱전압 조절 이온 주입전 well 어닐(Anneal) 공정시 기존의 희생막을 크리닝 과정에서 제거하고 well 어닐 과정과 동시에 희생막을 고르게 성장시켜 채널 문턱전압 조절 이온주입시 Rp값을 고르게 조절할 수 있어 추가되는 공정없이 MOS의 문턱전압을 안정적으로 할 수 있다.In the present invention, it is possible to adjust the Rp value evenly during the channel threshold voltage control ion implantation by removing the existing sacrificial film during the cleaning process during the well annealing process before the channel threshold voltage control ion implantation, and evenly growing the sacrificial film simultaneously with the well annealing process. The threshold voltage of the MOS can be stabilized without an additional process.
상기한 본 발명의 사상의 범위 내에서 당업자가 용이하게 변경하는 것은 본 발명의 범위에 포함된다.It is within the scope of the present invention to be easily changed by those skilled in the art within the scope of the spirit of the present invention described above.
Claims (5)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980045571A KR20000027616A (en) | 1998-10-28 | 1998-10-28 | Method of manufacturing semiconductor device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980045571A KR20000027616A (en) | 1998-10-28 | 1998-10-28 | Method of manufacturing semiconductor device |
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| KR20000027616A true KR20000027616A (en) | 2000-05-15 |
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| KR1019980045571A KR20000027616A (en) | 1998-10-28 | 1998-10-28 | Method of manufacturing semiconductor device |
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1998
- 1998-10-28 KR KR1019980045571A patent/KR20000027616A/en not_active Application Discontinuation
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