KR20000027402A - Semiconductor device and manufacturing method using silicon on insulator substrate - Google Patents

Abstract

PURPOSE: A semiconductor device and method for manufacturing the same are provided to reduce a junction capacitance and prevent a well pick up and a punch-through by forming a buried insulator only at bottom portion of source and drain junction using SOI(silicon on insulator) substrate. CONSTITUTION: A buried insulator(21) is formed on a silicon substrate(20), and then selectively etched using a first etching mask(M1). Thereby, the buried insulator(21) pattern is only formed at bottom portion of source/drain junction. After removing the first etching mask(M1), an epitaxial silicon layer(22) is grown. Using a second etching mask(M2), the epitaxial silicon layer(22) formed on the buried insulator pattern is exposed. Then, a trench(t) is formed by sequentially etching the exposed epitaxial silicon layer(22), buried insulator(21) and silicon substrate(20). Finally, a gate oxide(23) is filled into the trench and flattened.

Description

Semiconductor device using silicon on insulator substrate and manufacturing method thereof

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the field of semiconductor device manufacturing, and more particularly, to a semiconductor device using a silicon on insulator (hereinafter referred to as SOI) substrate and a method of manufacturing the same.

1 is a cross-sectional view showing a transistor formed on an SOI substrate according to the prior art. As shown in FIG. 1, the SOI substrate is composed of a silicon substrate 10, a buried oxide 11 formed on the silicon substrate, and a silicon layer 12 formed on the buried oxide film 11. In FIG. 1, reference numeral 14 denotes a gate oxide film, 15 a gate electrode, and 16 a source / drain junction, respectively.

The SOI substrate has parasitic bipolarity because it is not easy to secure a well-pick up space because the buried oxide film 11 is formed on the silicon layer where the transistor is to be formed, that is, the entire bottom surface of the active region. Problems arise from the parasitic bipolar junction transistor and the kink effect. In addition, heat dissipation is not easy due to difficulty in securing a well-pick-up formation space, and the investment oxide film formed of SiO ₂ has a lower thermal conductivity than Si, and thus the problem of failing to release heat becomes more serious. .

In addition, deterioration of device characteristics occurs due to the parasitic capacitance of the source and drain junctions, and punch-through occurs between neighboring device isolation regions as the integration of devices increases.

The present invention devised to solve the above problems simultaneously solves the well pick up and heat dissipation problem, reduces the source and drain junction capacitance and punch-through between the device isolation region. SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device using an SOI substrate capable of suppressing through, and a manufacturing method thereof.

1 is a cross-sectional view showing a transistor formed on an SOI substrate according to the prior art;

2A to 2G are cross-sectional views of a semiconductor device manufacturing process using an SOI substrate in accordance with an embodiment of the present invention;

3A to 3E are cross-sectional views of a semiconductor device manufacturing process using an SOI substrate in accordance with another embodiment of the present invention.

* Explanation of reference numerals for the main parts of the drawings

20, 30, 40: silicon substrate 21, 31: investment oxide film

22: epitaxial silicon layer 23, 33: gate oxide film

24, 34: gate electrode 32: oxide film

25A, 25B, 35A, 35B: Source-drain junction M1, M2: Etch mask

t: trench S: source electrode

D: drain electrode G: gate electrode

The present invention for achieving the above object is a semiconductor substrate; A buried insulating film pattern formed on the semiconductor substrate to expose the semiconductor substrate in the center of an active region; A silicon layer in contact with the semiconductor substrate and the buried insulating film pattern; A trench formed in the device isolation region; An isolation layer formed in the trench; A gate oxide film and a gate electrode formed on the silicon layer in the active region; And a source region and a drain region formed in the silicon layer at both ends of the gate electrode, and each bottom thereof contacts the buried insulating layer.

In addition, the present invention for achieving the above object is a first step of forming a buried insulating film pattern for exposing the semiconductor substrate in the center of the active region on the semiconductor substrate; Forming a silicon layer in contact with the semiconductor substrate and the buried insulating film pattern; Forming a trench by selectively etching the silicon layer, the buried insulating film pattern, and the semiconductor substrate in the device isolation region, and filling an insulating film in the trench; Forming a gate oxide film and a gate electrode on the silicon layer in the active region; And implanting ions into the silicon layers across the gate electrodes, and forming a source junction and a drain junction, each bottom of which contacts the buried insulating layer pattern.

The present invention solves the well pick-up problem, which is a problem of the conventional SOI substrate, by forming a buried insulating film only at the bottom portion of the source / drain junction, and simultaneously reduces the source and drain junction capacitance and reduces the trench. It is a method of forming a device isolation film by forming a trench and filling an insulating film in a trench to improve the device isolation effect and to suppress punch-through.

Hereinafter, a semiconductor device manufacturing method using an SOI substrate according to an exemplary embodiment of the present invention will be described with reference to the accompanying drawings.

2A through 2G are cross-sectional views illustrating a semiconductor device manufacturing process using an SOI substrate in accordance with an embodiment of the present invention.

First, a buried oxide film 21 is formed on the silicon substrate 20 as shown in FIG. 2A.

Next, as shown in FIG. 2B, a first etching mask M1 exposing a portion of the buried oxide film 21 positioned at the center of the active region is formed, and the buried oxide film 21 is selectively etched to form a silicon substrate ( 20). In this case, the portion of the buried oxide film 21 to be etched is a region between the source and drain junctions.

Next, as shown in FIG. 2C, the first etching mask M1 is removed to grow the epitaxial silicon layer 22.

Next, as shown in FIG. 2D, after the epitaxial silicon layer 22 having the desired thickness is grown, a second etching mask M2 for opening the trench formation region for device isolation on the epitaxial silicon layer 22 is performed. ). In this case, the second etching mask M2 exposes the epitaxial silicon layer 22 on the buried oxide film 21.

Next, as shown in FIG. 2E, the epitaxial silicon layer 22, the buried oxide film 22, and the silicon substrate 20 exposed after the formation of the second etching mask M2 are etched into the silicon substrate 20. The trench t is formed. In this case, the epitaxial silicon layer 22, the buried oxide film 22, and the silicon substrate 20 are exposed on the sidewalls of the trench t.

Next, as shown in FIG. 2F, an oxidation process is performed to fill the oxide film 23 in the trench t, and a chemical mechanical polishing (CMP) process is performed to planarize the film.

Next, as shown in FIG. 2G, the gate oxide film 23 and the gate electrode 24 are formed on the epitaxial silicon layer 22, and an ion implantation process is performed to form the source and drain junctions 25A and 25B. Form. At this time, the bottoms of the source and drain junctions 25A and 25B are in contact with the investment oxide film 21, and the epitaxial silicon layer 22 between the investment and oxide films 21 in contact with the source and drain junctions 25A and 25B, respectively. The silicon substrate 20 may come into contact with each other to secure the well-pickup area A to form an electrode. In FIG. 2G, reference numeral S denotes a source electrode, D denotes a drain electrode, and G denotes a gate electrode.

A transistor manufacturing method using an SOI substrate according to another exemplary embodiment of the present invention will be described with reference to FIGS. 3A to 3E.

First, as shown in FIG. 3A, an anti-oxidation mask M covering the center of the active region is formed on the entire surface of the first silicon substrate 30, and an oxidation process is performed to form a buried oxide film 31.

Next, as illustrated in FIG. 3B, the anti-oxidation mask M is removed, and a chemical mechanical polishing (CMP) process or an entire surface etching process is performed to planarize.

Next, as shown in FIG. 3C, the entire surface of the first silicon substrate 30 on which the planarization of the investment oxide film 31 is completed and the second silicon substrate 40 are bonded by using a Si direct bonding technique.

Next, as shown in FIG. 3D, after the bonding between the first silicon substrate 30 and the second silicon substrate 40 is completed, a trench forming region for device isolation may be opened on the second silicon substrate 40. An etching mask (not shown) is formed, the second silicon substrate 40, the buried oxide film 31, and the first silicon substrate 30 are selectively etched to form a trench, and then an oxidation process is performed to perform internal trenches. The oxide film 32 is filled in, and a chemical mechanical polishing (CMP) process is performed to planarize.

Next, as shown in FIG. 3E, the gate oxide film 33 and the gate electrode 34 are formed on the second silicon substrate 40, and an ion implantation process is performed to form the source / drain junctions 35A and 35B. Form. At this time, the bottoms of the source / drain junctions 35A and 35B are in contact with the investment oxide film 31, and the second silicon substrate 40 and the buried oxide films 31, which are in contact with the source / drain junctions 35A and 35B, respectively. The first silicon substrate 30 may come into contact with each other to secure the well-pickup area A to form an electrode. In FIG. 3E, reference numeral S denotes a source electrode, D denotes a drain electrode, and G denotes a gate electrode.

According to the present invention as described above, it is possible to secure a well pickup region, thereby preventing the occurrence of parasitic bipolar junction transistors and kink effects, and enabling heat dissipation. . In addition, the bottom of the source / drain junction comes into contact with the buried insulating film, so that parasitic capacitance of the source / drain junction can be reduced, and the occurrence of punch-through can be suppressed by embedding the insulating film in the trench to increase the device isolation effect.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary knowledge.

Claims (9)

In a semiconductor device, Semiconductor substrates; A buried insulating film pattern formed on the semiconductor substrate to expose the semiconductor substrate in the center of an active region; A silicon layer in contact with the semiconductor substrate and the buried insulating film pattern; A trench formed in the device isolation region; An isolation layer formed in the trench; A gate oxide film and a gate electrode formed on the silicon layer in the active region; And A source region and a drain region formed in the silicon layer across the gate electrode and each bottom thereof contacts the buried insulating layer. A semiconductor device comprising a. The method of claim 1, And the semiconductor substrate and the silicon layer in the center of the active region are well-pick up regions. The method according to claim 1 or 2, And the trench exposes a sidewall of the silicon layer, the buried insulating film pattern, and the semiconductor substrate. In the semiconductor device manufacturing method, Forming a buried insulating film pattern exposing the semiconductor substrate at the center of an active region on the semiconductor substrate; Forming a silicon layer in contact with the semiconductor substrate and the buried insulating film pattern; Forming a trench by selectively etching the silicon layer, the buried insulating film pattern, and the semiconductor substrate in the device isolation region, and filling an insulating film in the trench; Forming a gate oxide film and a gate electrode on the silicon layer in the active region; Implanting ions into the silicon layer across the gate electrode to form a source junction and a drain junction, each bottom thereof contacting the buried insulating layer pattern A semiconductor device manufacturing method comprising a. The method of claim 4, wherein And forming a well-pick up electrode in the semiconductor substrate and the silicon layer in the center of the active region. The method according to claim 4 or 5, The first step, Forming a buried insulating film on the semiconductor substrate; And And selectively etching the buried insulating film in the central portion of the active region to form the buried insulating film pattern. The method of claim 6, In the second step, And growing the silicon layer epitaxially. The method according to claim 4 or 5, The first step, Forming an anti-oxidation mask on the semiconductor substrate to cover a central portion of an active region; Performing an oxidation process to form a buried oxide film constituting the buried insulating film; Removing the antioxidant mask; And And planarizing the buried oxide film. The method of claim 8, In the second step, And the silicon substrate is formed by bonding the semiconductor substrate and the silicon substrate.