KR20000027379A - Ferroeelctric random access memory devices having improved sensing margin - Google Patents

Abstract

PURPOSE: An FRAM device is provided to improve a sensing margin and extend a life of the memory by pre charging a bit line to a power supplied voltage(Vcc) and setting a reference voltage for sensing to the Vcc. CONSTITUTION: A memory cell(650) includes a first and a second ferroelectric capacitors(FC1,FC2) connected in serial between a first and a second plate lines(PL1,PL2), and an NMOS transistor(TR) connected to a node between the plate lines(PL1,PL2). A sensing amplifier(640) senses and amplifies voltage differency between a positive bit line(BL) and a negative bit line(/BL). A data input part(610) is transferred a positive and a negative data to the BL and /BL corresponding to a write enable signal. A bit line precharge part(620) pre charges the BL and /BL to a power supplied voltage(Vcc) corresponding to a second control signal. A high voltage driver(660) operates a word line(WL) and the first plate line(PL1) by 2Vcc.

Description

Ferroelectric memory device with improved sensing margin

The present invention relates to a ferroelectric memory (Ferroelectric RAM, FeRAM), and more particularly to a ferroelectric memory device with improved data sensing margin.

As is well known, capacitors using ferroelectric materials have a hysteresis curve in the relationship between the voltage across the capacitor and the amount of charged charge. FIG. 1A shows a symbol of a ferroelectric capacitor formed between terminals a and b, and FIG. 1B shows an equivalent of a ferroelectric capacitor, and FIG. 1C shows a relationship of charge amount according to voltage between both terminals a and b of a capacitor. It is. Referring to FIGS. 1A, 1B, and 1C, when there is no potential difference across the ferroelectric capacitors a and b, the amount of charge maintained by polarization exists in two states, 'a' and 'b', so that no power is supplied. It can store binary data. When the information of '1' is stored as 'A' when there is no potential difference between a and b terminals, and the information of '0' is displayed as 'I', the terminal b is read to read the stored information. When a certain voltage (V) is applied, the polarization at the 'ga' position is dragged to the 'da' state to generate the amount of charge as Q1. At this time, since the state of polarization changes beyond the voltage (Vc) that can cause switching, as shown in FIG. 1B, the nonlinear capacitance (Csw) component during switching and the linear capacitance (Cln) component when not switching are simultaneously present. . In addition, the polarization at the 'I' position is also dragged to the 'D' state, and since no switching occurs, only the linear capacitance (Cln) exists and generates a charge amount as Q0. Due to the difference in the amount of charge caused by these two state changes, the ferroelectric capacitor is used as a storage means for the nonvolatile memory device.

Currently, various types of memory cells using ferroelectric capacitors have been proposed, and one of them is to construct a memory cell using one transistor and two ferroelectric capacitors (A High Density 1T / 2C Cell with Vcc / 2 Reference Level for High Stable FeRAM: IEDM 97-863-866). However, in the conventional driving of such a memory cell, since the Vcc / 2 voltage is used as the reference voltage, the inherent aging phenomenon of the ferroelectric capacitor causes a problem in reliability as a memory. It will be described in detail below.

The configuration of a memory cell using one transistor and two ferroelectric capacitors, and the problems in the related art and the driving method for driving the same in the configuration will be described in order.

First, the configuration of a memory cell using one transistor and two ferroelectric capacitors will be described. The technical principle of this configuration is that when two capacitors C1 and C2 having different capacitances are connected in series, as shown in Fig. 2, when one end is grounded and a specific voltage Vcc is applied to the other end, When the capacitance of capacitor C1 is large, the voltage induced at node V0 between both capacitors C1 and C2 becomes lower than Vcc / 2, and when the capacitance of capacitor C2 is larger, the voltage induced at node V0 is greater than Vcc / 2. High voltage. 3 shows a cell circuit diagram of a memory cell using this principle. As shown in FIG. 3, the first and second ferroelectric capacitors FC1 and FC2 having capacitances of the same value are connected in series between the first and second plate lines PL1 and PL2, and the memory A node V0 between both capacitors FC1 and FC2 is connected to a source of a memory cell transistor TR, a bit line BL is connected to a drain of the transistor TR, and a gate of the transistor TR is connected. When the word line WL is connected, it can be used as a memory cell.

Next, in reading and driving a ferroelectric memory device having such a configuration, a reference voltage Vref for sensing data in a sense amplifier is conventionally used as Vcc / 2 (that is, the "bit line Vcc / Precharge to 2), and drive the word line at Vcc + Vtn (threshold voltage of the cell transistor), and drive the first plate PL1 to Vcc and the second plate line PL2 to ground voltage, respectively. Used. 4 is a diagram briefly illustrating a conventional driving method, and a read operation according to the conventional method will be described in detail with reference to FIGS. 4 and 3. First, the plate line PL1 and the plate line PL2 are grounded to write the information of “1” to the memory cell, and the word line WL is driven to apply Vcc to the node V0. Then, to eliminate the potential difference between both ends of the capacitor FC1 and the capacitor FC2, Ground both ends. Then, the polarization of the capacitor FC1 is located at the point 'I' in FIG. 1C, and the polarization of the capacitor FC2 is located at the point 'I' in FIG. 1C. After that, precharge the bit line to Vcc / 2 (this determines the voltage level of the reference voltage line) to read the information of “1”, then drive the word line to Vcc + Vtn and the plate line PL1 to Vcc. The polarization direction of FC1 is switched and the polarization direction of capacitor FC2 is maintained. As a result, as described above, the capacitor FC1 has both a linear capacitance component and a nonlinear capacitance component, and the capacitor FC2 has only a linear capacitance component, so that the capacitance of the capacitor FC1 becomes larger than that of the capacitor FC2. Thus, the voltage V0 induced at the node between the capacitors FC1 and FC2 has a potential higher than Vcc / 2, which shares a charge with the parasitic capacitances on the bitline BL, resulting in a voltage higher than Vcc / 2 on the bitline BL. This is amplified to Vcc and ground voltage through the sense amplifier compared to the unselected BL_bar (reference voltage line) precharged to Vcc / 2. On the other hand, in order to write "0" information to the memory cell, the plate line PL1 and the plate line PL2 are set to Vcc voltage, and the word line WL is driven to apply a ground voltage to the node V0. Then, the polarization of the capacitor FC1 is located at the point 'ga' in FIG. 1c, and the polarization of the capacitor FC2 is located at the point 'b' in FIG. 1c. Then, in order to read the information of "0", precharge the bit line to Vcc / 2 in the same manner as the method of reading the information of "1" (this determines the voltage level of the reference voltage line), and sets the word line to Vcc + Vtn. Therefore, when the plate line PL1 is driven to Vcc and the plate line PL2 is driven to the ground voltage, the polarization direction of the capacitor FC1 is maintained, and the polarization direction of the capacitor FC2 is switched. As a result, capacitor FC1 has only a linear capacitance component, and capacitor FC2 has a component of linear capacitance and a nonlinear capacitance component at the same time, so that capacitance of capacitor FC2 becomes larger than that of capacitor FC1. Thus, the voltage V0 induced at the node between capacitors FC1 and FC2 has a potential lower than Vcc / 2, which is compared to the unselected BL_bar (which becomes the reference voltage line) precharged to Vcc / 2. It is amplified to ground voltage and Vcc respectively through.

As described above, conventionally, the Vcc / 2 voltage is used as the reference voltage. As a result, the sensing margin decreases as the number of switching increases. That is, during the read operation, one of the capacitors FC1 and FC2 switches, and since the ferroelectric capacitor has a aging phenomenon in which the charge gradually decreases as shown in FIG. 5, the number of times of use increases. While the sensing margin is falling. This is a big problem for memory reliability.

SUMMARY OF THE INVENTION The present invention has been made to solve the problems of the prior art, and an object thereof is to provide a ferroelectric memory device having an improved data sensing margin.

1A shows a symbol of a ferroelectric capacitor;

1B is an equivalent circuit diagram of a ferroelectric capacitor;

Figure 1c is a hysteresis curve showing the characteristics of the ferroelectric capacitor,

2 is a conceptual diagram illustrating the operation principle of a cell composed of one transistor and two ferroelectric capacitors;

3 is a cell circuit diagram consisting of one transistor and two ferroelectric capacitors;

4 is a diagram showing the driving of a ferroelectric memory device according to the prior art;

5 is a view showing a aging phenomenon, which is a characteristic of a ferroelectric capacitor;

6 is a partial circuit diagram of a ferroelectric memory device according to an embodiment of the present invention;

7 is a timing diagram of each signal when the data of " 1 " is read in FIG. 6, and thus a logic state of both ends of the ferroelectric capacitor and a polarization state of the hysteresis curve;

8 is an exemplary diagram of a pumping circuit for generating a 2 Vcc potential;

9 is a voltage waveform diagram showing a simulation result in the prior art;

Fig. 10 is a voltage waveform diagram showing a simulation result in the present invention.

* Explanation of symbols for main parts of the drawings

610: data input unit 620: bit line precharge unit

630: bit line pull-down unit 640: detection amplifier unit

650: memory cell 660: high voltage driver

The ferroelectric memory device of the present invention for achieving the above object, the first and second ferroelectric capacitors connected in series between the first and the second plate line, the source is the first ferroelectric capacitor and the second ferroelectric capacitor A memory cell comprising an MOS transistor connected to a node therebetween, a gate connected to a word line, and a constant bit line connected to a drain; Sensing amplifying means for sensing and amplifying a voltage difference between the positive bit line and the sub bit line as a reference voltage line; Data input means for transferring positive and negative data to the positive and negative bit lines in response to a write enable signal; Bit line pull-down means for pulling down the positive bit line and the sub bit line to a ground power supply voltage in response to a first control signal; Bit line precharge means for precharging the positive bit line and the sub bit line to the supply power supply voltage Vcc in response to a second control signal; And high voltage driving means for driving the word line and the first plate line at a high voltage of about 2 times the supply power voltage Vcc.

The present invention having such a configuration is characterized in that the word line and the plate line are driven at 2 Vcc, and the bit line is precharged at Vcc (that is, the reference voltage for sensing is set at Vcc). Capacitors with the same area as in the above can induce about twice the voltage on the bit line, which enables more stable sensing operation and longer memory life due to increased sensing margin. That is, as the number of times of use increases, the amount of charges decreases, thereby reducing the potential induced in the bit line, thereby solving the problems of the related art.

In addition, in the prior art, since Vcc / 2 is generated internally and used as a reference voltage, if the potential of Vcc / 2 fluctuates due to internal factors, there is a possibility of malfunction in reading information due to stability problems. In the present invention, since Vcc is used as the reference voltage, this conventional problem can be overcome to achieve stable operation as a memory device.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

6 is a circuit diagram of a part of a ferroelectric memory device according to an embodiment of the present invention. Referring to FIG. 6, in the ferroelectric memory device according to an embodiment of the present invention, two ferroelectric capacitors FC1 and FC2 and one transistor TR form a unit cell 650. That is, the first and second ferroelectric capacitors FC1 and FC2 connected in series between the first play line PL1 and the second play line PL2 and the source are the first ferroelectric capacitor FC1 and the second. The unit cell 650 is formed by an enMOS transistor TR connected to a node V0 between the ferroelectric capacitors FC2, a gate connected to a word line WL, and a positive bit line BL connected to a drain. In addition, the ferroelectric memory device of the present invention includes a sense amplifier 640 for sensing and amplifying a voltage difference between the positive bit line BL and the sub bit line / BL as a reference voltage line, and a write enable signal WE. A data input unit 610 for transmitting positive and negative data Din to the positive and sub bit lines BL and / BL, respectively, and a positive and sub bit line BL in response to the first control signal pbl. , And a bit line pull-down unit 630 for pulling down the / BL to a ground power supply voltage. The bit line pull down unit 630 is connected to the positive bit line BL and the sub bit line / BL in response to the second control signal hpl. The bit line precharge unit 620 for precharging to the supply power supply voltage Vcc, and the word line WL and the first plate line PL1 at a high voltage (2Vcc) that is about twice the supply power supply voltage Vcc. It includes a high voltage driver 660 for driving. The first control signal hpl is activated just before the read drive to enable the bit line precharge unit 620 to precharge the positive and sub bit lines BL and / BL to the supply voltage Vcc just before the read drive. . The second control signal pbl is deactivated during the read driving.

In the ferroelectric memory device according to the embodiment of the present invention having such a configuration, the word line and the plate line are driven at 2 Vcc, and the bit lines are precharged at Vcc (that is, the reference voltage for sensing is set to Vcc). In this regard, the operation of the ferroelectric memory device as shown in FIG. 6 will be described in detail.

FIG. 7 is a timing diagram of each signal when the data of “1” is read in FIG. 6, and a logic state of both ends of the ferroelectric capacitor and a polarization state of the hysteresis curve. FIG. Look specifically at.

The first play line PL1 and the second play line PL2 are grounded to write information of “1”, Vcc is input through the data input unit 610, and the word line WL is driven through the high voltage driver 660 to transmit the transistor (TR). After turning on), apply Vcc to node V0, and remove the potential difference between both ends. do. If the second control signal hpl signal is 'low' to read the stored information, the bit line pair is precharged to Vcc, and the potential of the word line WL1 and the plate line PL1 is driven to 2Vcc. As in, the polarization of capacitor FC1 is located at point d, and the polarization state of capacitor FC2 is located at point h. At this time, the capacitor composed of the ferroelectric has the characteristics of the hysteresis curve as shown in FIG. Since the polarization state of the capacitor FC2 is not changed at the same time, since only the component of the linear capacitance is included, the capacitance of the capacitor FC1 becomes larger than the capacitance of the capacitor FC2. Thus, the voltage V0 of the node induced between the capacitors FC1 and FC2 has a potential higher than Vcc, which shares a charge with the parasitic capacitance of the BL in the bitline, and thus has a voltage higher than Vcc in the bitline BL. The voltage levels of the non-selected sub bit line / BL and the positive bit line BL which are precharged to Vcc are amplified to the ground voltage and Vcc through the sense amplifier 640, respectively. In this case, as shown in Fig. 7, precharging the bit line with Vcc and setting the voltage of the first play line to 2 Vcc, compared with the conventional method of precharging the bit line with Vcc / 2 and driving the plate at Vcc (Fig. 4). In addition, the difference between the voltage induced on the bit line and the reference voltage becomes larger. The reason is that the difference between the sum of the nonlinear capacitance and the linear capacitance of the switched capacitor and the linear capacitance of the unswitched capacitor is larger when driving the plateline at 2 Vcc, so that the induced potential between the two capacitors is higher. It will grow big.

FIG. 8 is an exemplary circuit diagram and timing diagram of a high voltage driver 660 for making the word line WL and the plate line PL 2Vcc. The logic 'high' level input is synchronized with the clock CLK. It consists of a pumping circuit which pumps twice.

9 is a voltage waveform diagram showing simulation results in the prior art, and FIG. 10 is a voltage waveform diagram showing simulation results in the present invention, in which two ferroelectric capacitors have the same area, and capacitors parasitic on the bit line are uniform. After precharging the bit line to Vcc / 2 and driving PL1 to Vcc (prior art, see FIG. 9), about 1.75V is induced in the bit line and the sensing margin with reference voltage is about 0.25V. do. However, if the bit line is precharged to Vcc and the plate line PL1 is driven to 2Vcc (see FIG. 11, the present invention), the voltage induced in the bitline becomes about 3.5V, and is precharged to Vcc (3V). The difference from the reference voltage is 0.5V and the sensing margin is doubled. The operation after the sensing is completed is the same as described above.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

The present invention is characterized in that the word line and the plate line are driven at 2 Vcc, and the bit lines are precharged at Vcc (i.e., the reference voltage for sensing is set at Vcc). With the capacitor having about twice the voltage can be induced to the bit line, the increased sensing margin allows more stable sensing operation and can extend the life of the memory.

In addition, in the prior art, since Vcc / 2 is generated inside the chip and used as a reference voltage, if the potential of Vcc / 2 fluctuates due to internal factors, there is a problem in stability and malfunction in reading information. There is a possibility, but in the present invention, since Vcc is used as the reference voltage, this conventional problem can be overcome to achieve stable operation as a memory device.

Claims (3)

In ferroelectric memory device, A first and a second ferroelectric capacitor connected in series between the first and second plate lines, a source connected to a node between the first ferroelectric capacitor and the second ferroelectric capacitor, a gate connected to a word line, and a drain A memory cell comprising an MOS transistor having a constant bit line connected thereto; Sensing amplifying means for sensing and amplifying a voltage difference between the positive bit line and the sub bit line as a reference voltage line; Data input means for transferring positive and negative data to the positive and negative bit lines in response to a write enable signal; Bit line pull-down means for pulling down the positive bit line and the sub bit line to a ground power supply voltage in response to a first control signal; Bit line precharge means for precharging the positive bit line and the sub bit line to the supply power supply voltage Vcc in response to a second control signal; And High voltage driving means for driving the word line and the first plate line at a high voltage (2 Vcc) approximately twice the supply power voltage (Vcc). Ferroelectric memory device comprising a. The method of claim 1, And the high voltage driving means comprises a pumping circuit configured to pump a logic 'high' level twice in synchronization with a clock. The method according to claim 1 or 2, And the first control signal is initially activated during read driving, and the second control signal is a control signal deactivated during read driving.