KR20000026808A - Method for forming fuse of semiconductor devices - Google Patents
Method for forming fuse of semiconductor devices Download PDFInfo
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- KR20000026808A KR20000026808A KR1019980044512A KR19980044512A KR20000026808A KR 20000026808 A KR20000026808 A KR 20000026808A KR 1019980044512 A KR1019980044512 A KR 1019980044512A KR 19980044512 A KR19980044512 A KR 19980044512A KR 20000026808 A KR20000026808 A KR 20000026808A
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- 238000000034 method Methods 0.000 title claims abstract description 22
- 239000004065 semiconductor Substances 0.000 title claims description 18
- 229910052751 metal Inorganic materials 0.000 claims abstract description 61
- 239000002184 metal Substances 0.000 claims abstract description 61
- 230000004888 barrier function Effects 0.000 claims abstract description 22
- 239000000758 substrate Substances 0.000 claims abstract description 20
- 238000005530 etching Methods 0.000 claims abstract description 12
- 238000001039 wet etching Methods 0.000 claims description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 14
- 229920005591 polysilicon Polymers 0.000 abstract description 14
- 238000004519 manufacturing process Methods 0.000 abstract description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 6
- 229910052710 silicon Inorganic materials 0.000 abstract description 6
- 239000010703 silicon Substances 0.000 abstract description 6
- 238000004544 sputter deposition Methods 0.000 abstract description 6
- 238000005520 cutting process Methods 0.000 abstract description 5
- 229910052782 aluminium Inorganic materials 0.000 abstract description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 3
- 238000001312 dry etching Methods 0.000 abstract description 3
- 230000015572 biosynthetic process Effects 0.000 abstract description 2
- 239000011248 coating agent Substances 0.000 abstract description 2
- 238000000576 coating method Methods 0.000 abstract description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 15
- 239000000047 product Substances 0.000 description 6
- 230000002950 deficient Effects 0.000 description 5
- 229910016006 MoSi Inorganic materials 0.000 description 4
- 230000010354 integration Effects 0.000 description 3
- 238000012360 testing method Methods 0.000 description 3
- 230000007547 defect Effects 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 239000000523 sample Substances 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 1
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000007598 dipping method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010292 electrical insulation Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 239000013589 supplement Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
- H01L23/5256—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32134—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by liquid etching only
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
Description
본 발명은 반도체장치의 제조방법에 관한 것으로서 특히, 반도체장치의 기억소자 제조에 있어서 펩(FAB)공정중 발생하는 불량부위를 수리하기 위하여 통상적으로 메모리 어레이의 끝 부분과 리던던시 라인(redundancy line)을 연결하는 퓨즈를 폴리실리콘 대신에 전기적으로 동작하는 금속 퓨즈를 형성하므로서 회로의 고집적화 및 단순화를 가져오며 퓨즈 절단용 레이저장비가 필요하지 아니하도록한 반도체장치의 퓨즈 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device. In particular, in order to repair a defective portion generated during a PAB process in manufacturing a memory device of a semiconductor device, an end portion of a memory array and a redundancy line are typically used. The present invention relates to a method of forming a fuse of a semiconductor device in which a fuse to be connected is formed instead of polysilicon to form a metal fuse which is electrically operated, thereby bringing high integration and simplification of a circuit and eliminating the need for a fuse cutting laser device.
종래 기술에 따른 반도체장치의 퓨즈 형성방법은 실리콘기판에 산화막을 형성한 후 그 위에 도핑된 폴리실리콘을 증착한 다음 패터닝하여 퓨즈를 형성하고, 그 위에 퓨즈와 금속배선을 절연시키기 위한 절연층을 형성한 후, 퓨즈와 굼속배선을 연결할 콘택홀을 절연층의 소정 부위를 제거하여 형성하고, 다시 전 표면에 다중 금속층을 스퍼터링 방법으로 형성한다. 이때 다중 금속층은 MoSi/Al/MoSi로 이루어지며 그 두께는 약 600/8000/400 Å이다. 이후, 금속배선을 형성하기 위한 사진식각공정을 실시하켠 폴리실리콘으로 이루어진 퓨즈가 형성되며, 이러한 퓨즈는 레이저를 이용하여 필요에 따라 절단된다.According to the conventional method of forming a fuse of a semiconductor device, an oxide film is formed on a silicon substrate, and then a doped polysilicon is deposited thereon, and then patterned to form a fuse, and an insulating layer for insulating the fuse and the metal wiring is formed thereon. After that, a contact hole for connecting the fuse and the slug wiring is formed by removing a predetermined portion of the insulating layer, and the multi-metal layer is formed on the entire surface by sputtering. At this time, the multi-metal layer is made of MoSi / Al / MoSi and the thickness is about 600/8000/400 mm 3. Thereafter, a fuse made of polysilicon having a photolithography process for forming a metal wiring is formed, and the fuse is cut as needed using a laser.
이때 반도체장치의 펩공정은 일반적으로 페시베이션층 형성 후 패드부를 개방시키는 단계까지의 공정을 말한다.In this case, the pep process of the semiconductor device generally refers to a process of forming a passivation layer and then opening the pad part.
종래의 기술에서 반도체장치의 소자 등이 형성된 칩을 완성한 다음 불량품을 검사하고 불량 발생 부위를 수리하는 과정은 다음과 같다.In the prior art, a process of inspecting a defective product and repairing a defective part after completing a chip on which a device of a semiconductor device is formed is as follows.
먼저, 웨이퍼에 소자 등이 형성된 칩을 제조하고 불량 유무를 확안하기 위하여 프로브 테스트(probe test)를 실시한다. 이러한 테스트 결과 불량품임이 판정되면 수리가능 여부를 검토한 다음 수리 가능한 제품은 다음 단계로 진입하고 수리 불능인 제품은 폐기 처리한다. 수리 가능한 제품은 수리 데이타를 생성한 다음 불량부위를 찾아내어 수리 데이타(repair data)가 생성된 특정 퓨즈를 레이저로 정확히 조사하여 절단하므로서 수리한다. 따라서 수리된 불량 칩은 양질의 제품으로 변환된다.First, a probe test is performed in order to manufacture a chip having an element or the like formed on a wafer and to check for defects. If such a test determines that a defective product is found to be defective, the repairable product is entered into the next stage and the non-repairable product is disposed of. Repairable products are repaired by generating repair data, finding faulty parts, and precisely irradiating and cutting laser-specific fuses for which repair data have been generated. Thus, the repaired bad chip is converted into a good product.
도 1a 내지 도 1d는 종래의 기술에 따른 반도체장치의 퓨즈(fuse) 형성방법을 도시한 공정단면도이다.1A to 1D are cross-sectional views illustrating a method of forming a fuse of a semiconductor device according to the related art.
도 1a를 참조하면, 실리콘기판(1)의 소정부위에 필드산화막(2)을 성장시켜 형성한다. 이러한 필드산화막(2)은 이후 형성되는 폴리실리콘 퓨즈와 기판의 실리콘 사이에 발생하는 누설전류를 차단하기 위한 것이다.Referring to FIG. 1A, a field oxide film 2 is grown on a predetermined portion of a silicon substrate 1. The field oxide film 2 is intended to block leakage current generated between the polysilicon fuse formed thereafter and the silicon of the substrate.
필드산화막(2) 표면을 포함하는 기판(1) 표면에 불순물이 도핑된 폴리실리콘층(3)을 CVD 방법으로 증착하여 약 2000Å 두께로 형성한다.An impurity doped polysilicon layer 3 is deposited on the surface of the substrate 1 including the surface of the field oxide film 2 by CVD to form a thickness of about 2000 mm 3.
그리고, 폴리실리콘층(3) 위에 포토레지스트를 도포한 후 필드산화막(2) 형성 부위에 포함되도록 정의되는 폴리실리콘층(3)을 노출시키는 포토레지스트패턴(40)을 노광 및 현상으로 정의한다.After the photoresist is applied on the polysilicon layer 3, the photoresist pattern 40 exposing the polysilicon layer 3 defined to be included in the field oxide film 2 formation site is defined as exposure and development.
도 1b를 참조하면, 포토레지스트패턴을 식각마스크로 이용하여 이로 부터 보호되지 아니하는 부위의 폴리실리콘층을 식각하여 필드산화막(2) 위에 잔류한 폴리실리콘층(3)으로 이루어진 퓨즈(3)를 형성한다. 이때, 필드산화막(2) 표면의 일부와 기판(1) 표면이 노출된다. 이어서, 포토레지스트패턴을 제거한다.Referring to FIG. 1B, a fuse 3 made of a polysilicon layer 3 remaining on the field oxide layer 2 by etching a polysilicon layer of a portion not protected from the photoresist pattern as an etch mask is used. Form. At this time, a part of the surface of the field oxide film 2 and the surface of the substrate 1 are exposed. Next, the photoresist pattern is removed.
도 1c를 참조하면, 노출된 퓨즈(3) 표면과 필드산화막(2) 표면을 포함하는 기판(1) 표면에 퓨즈와 이후 형성될 금속배선과의 전기적 절연용 절연층(4)을 산화막 등으로 증착하여 형성한다.Referring to FIG. 1C, an insulating layer 4 for electrical insulation between a fuse and a metal wiring to be formed on the surface of a substrate 1 including an exposed fuse 3 surface and a field oxide film 2 surface is formed of an oxide film or the like. By vapor deposition.
그 다음 퓨즈(3)의 소정 부위를 노출시키는 금속배선과 퓨즈(3) 연결용 콘택홀을 사진식각공정으로 절연층(4)의 소정 부위를 제거하여 형성한다.Next, a metal wiring exposing a predetermined portion of the fuse 3 and a contact hole for connecting the fuse 3 are formed by removing a predetermined portion of the insulating layer 4 by a photolithography process.
콘택홀 내부를 포함하는 절연층(4) 위에 하부 배리어 금속층(5)으로 MoSi를 스퍼터링 방법으로 약 600Å의 두께를 갖도록 형성한 다음, 그 위에 알루미늄층(6)을 역시 스퍼터링 방법으로 약 8000Å 두께로 증착하여 형성하고, 다시 그 위에 상부 배리어 금속층(7)으로 MoSi를 스퍼터링 방법으로 약 400Å의 두께를 갖도록 형성하여 금속배선(5,6,7)을 형성한다.MoSi is formed on the insulating layer 4 including the inside of the contact hole by the lower barrier metal layer 5 so as to have a thickness of about 600 kPa by the sputtering method, and thereafter, the aluminum layer 6 is also formed on a thickness of about 8000 kPa by the sputtering method. It is formed by evaporation, and again, MoSi is formed on the upper barrier metal layer 7 so as to have a thickness of about 400 mm by the sputtering method to form metal wirings 5, 6, and 7.
그 다음 상부 배리어 금속층(7) 표면을 포함하는 기판의 전면에 포토레지스트를 도포한 다음 필드산화막(2) 상부에 위치한상부 배리어 금속층(7)의 대부분을 노출시키는 포토레지스트패턴(8)을 노광 및 현상으로 정의하여 형성한다.Then, a photoresist is applied to the entire surface of the substrate including the surface of the upper barrier metal layer 7, and then the photoresist pattern 8 is exposed to expose most of the upper barrier metal layer 7 located above the field oxide film 2. It is defined as a phenomenon and formed.
도 1d를 참조하면, 포토레지스트패턴(8)을 식각마스크로 이용하는 건식식각을 실시하여 이로 부터 보호되지 아니하는 부위의 금속배선(5,6,7)을 제거하여 절연층(4)의 일부 표면을 노출시킨다. 이때, 금속배선(5,6,7)이 확실하게 절단되도록 과도식각을 실시하여 노출된 절연층(4)의 표면 일부를 제거한다. 따라서, 이 때부터 금속배선(5,6,7)은 퓨즈(3)에 의해서만 전기적으로 연결된다.Referring to FIG. 1D, a part of the surface of the insulating layer 4 is formed by performing dry etching using the photoresist pattern 8 as an etching mask to remove metal wirings 5, 6, and 7 of the portions that are not protected therefrom. Expose At this time, a portion of the surface of the exposed insulating layer 4 is removed by performing excessive etching so that the metal wirings 5, 6, and 7 are cut reliably. Therefore, from this point on, the metal wires 5, 6 and 7 are electrically connected only by the fuse 3.
이후, 폴리실리콘 퓨즈(3)를 웨이퍼 검사와 프로브 테스트를 거쳐 필요한 경우 셀을 보완해 주기 위하여 레이저로 절단한다.After that, the polysilicon fuse 3 is subjected to a wafer inspection and a probe test, and then cut with a laser to supplement the cell if necessary.
그러나, 상술한 종래 기술에 따른 반도체장치의 퓨즈 형성방법은 폴리실리콘을 퓨즈로 사용하기 때문에 소자설계시 넓은 영역을 차지하게 되어 고집적소자의 제조에 불리하며, 퓨즈형성을 위한 폴리실리콘 증착공정이 추가로 실시되어야하고, 또한 퓨즈를 절단하여야 할 경우 고가의 레이저 장비를 필요로하는 문제점이 있다.However, the method of forming a fuse of the semiconductor device according to the related art described above uses polysilicon as a fuse, thus occupying a large area when designing a device, which is disadvantageous in the manufacture of highly integrated devices, and a polysilicon deposition process for forming a fuse is added. To be carried out, and also to cut the fuse there is a problem that requires expensive laser equipment.
따라서, 본 발명의 목적은종래의 폴리실리콘 퓨즈 대신에 금속배선을 이용한 퓨즐르 형성하므로서 소자의 고집적화 및 설계의 단순화를 도모하며, 또한 퓨즈 절단용 레이저 등의 장비가 필요하지 않는 반도체장치의 퓨즈 형성방법을 제공하는데 있다.Accordingly, an object of the present invention is to form fuses using metal wiring instead of conventional polysilicon fuses, thereby facilitating high integration and design of devices, and forming fuses of semiconductor devices that do not require equipment such as a laser for cutting fuses. To provide a method.
상기 목적들을 달성하기 위한 본 발명에 따른 반도체장치의 퓨즈 형성방법은 반도체 기판의 소정 부위에 절연막을 형성하는 단계와, 절연막 상부를 포함하는 기판의 소정 부위에 배리어금속층/메인금속층/아크금속층으로 이루어진 금속배선을 형성하는 단계와, 절연막 상부에 위치한 배리어금속층과 메인금속층을 제거하는 단계를 포함하여 이루어진다.A fuse forming method of a semiconductor device according to the present invention for achieving the above object comprises the step of forming an insulating film on a predetermined portion of the semiconductor substrate, and a barrier metal layer / main metal layer / arc metal layer on a predetermined portion of the substrate including an upper portion of the insulating film Forming a metal wiring; and removing the barrier metal layer and the main metal layer on the insulating film.
도 1a 내지 도 1d는 종래의 기술에 따른 반도체장치의 퓨즈(fuse) 형성방법을 도시한 공정단면도1A to 1D are cross-sectional views illustrating a method of forming a fuse of a semiconductor device according to the related art.
도 2a 내지 도 2d는 본 발명에 따른 반도체장치의 퓨즈(fuse) 형성방법을 도시한 공정단면도2A through 2D are cross-sectional views illustrating a method of forming a fuse of a semiconductor device according to the present invention.
반도체장치의 기억소자 제조에 있어서 펩(FAB)공정중 발생하는 불량부위를 수리하기 위하여 통상적으로 메모리 어레이의 끝 부분에 리던던시 라인(redundancy line)을 구비시켜 특정한 퓨즈부를 레이저로 절단하여 불량한 특정한 비트라인 등을 수리한다. 이러한 퓨즈를 본 발명에서는 전기적으로 퓨즈 역할을 하는 금속 퓨즈를 형성한다.In order to repair defects occurring during the PAB process in the manufacture of memory devices in semiconductor devices, redundancy lines are typically provided at the ends of the memory array to cut specific fuse parts with a laser, thereby causing a specific bad bit line. Repair your back. In the present invention, such a fuse forms a metal fuse that serves as a fuse.
이하, 첨부한 도면을 참조하여 본 발명을 상세히 설명한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2d는 본 발명에 따른 반도체장치의 퓨즈(fuse) 형성방법을 도시한 공정단면도이다.2A to 2D are cross-sectional views illustrating a method of forming a fuse of a semiconductor device according to the present invention.
도 2a를 참조하면, 반도체기판인 실리콘기판(20)의 소정부위에 필드산화막(21)을 성장시켜 형성한다. 이러한 필드산화막(21)은 이후 형성되는 퓨즈와 기판의 실리콘 사이에 발생하는 누설전류를 차단하기 위한 것이다.Referring to FIG. 2A, a field oxide film 21 is grown on a predetermined portion of a silicon substrate 20, which is a semiconductor substrate. The field oxide film 21 is intended to block a leakage current generated between the fuse to be formed later and the silicon of the substrate.
그리고 필드산화막(21) 표면을 포함하는 기판(20) 위에 적층금속배선(22,23,24)을 스퍼터링 방법으로 증착하여 형성한다. 이러한 적층금속배선은 먼저 하부 배리어금속층(22)으로 TiW를 200Å 두께로 형성하고 그 위에 Al층(23)을 8000Å의 두께로 증착한 후 아크금속층(Anti-Reflection Coating,24)으로 TiW를 750Å 두께로 증착하여 형성한다. 즉, 소자간의 전기적연결을 위한 금속배선 형성시 퓨즈를 동시에 디자인한다.The multilayer metallization lines 22, 23, and 24 are formed on the substrate 20 including the surface of the field oxide film 21 by sputtering. This laminated metal wiring is formed by first forming TiW into the lower barrier metal layer 22 with a thickness of 200Å, depositing an Al layer 23 thereon with a thickness of 8000Å, and then depositing TiW with the arc metal layer (Anti-Reflection Coating, 24). It is formed by vapor deposition. That is, fuses are designed simultaneously when forming metal wiring for electrical connection between devices.
필드산화막(21)의 상부에 위치하는 상부 배리어금속층(24)의 소정 부위를 노출시키는 포토레지스트패턴(25)을 형성한다. 이러한 포토레지스트패턴(25)은 금속배선(22,23,24)의 패터닝 후 금속배선을 포함하는 기판의 전면에 포토레지스트를 20000-23000Å 두께로 도포한 후 상기 정의된 부위를 노출시키는 마스크를 이용한 노광 및 현상으로 형성한다.A photoresist pattern 25 is formed to expose a predetermined portion of the upper barrier metal layer 24 positioned on the field oxide film 21. The photoresist pattern 25 is formed by applying a photoresist to the entire surface of the substrate including the metal wirings after patterning of the metal wirings 22, 23, and 24 to a thickness of 20000-23000Å, and then using a mask to expose the defined portions. It is formed by exposure and development.
도 2b를 참조하면, 포토레지스트패턴(25)으로 보호되지 아니하는 부위의 아크금속층(24)을 건식식각으로 제거한다. 이때, 식각조건은 BCl347 sccm, SF628 sccm 그리고 35 W이다.Referring to FIG. 2B, the arc metal layer 24 of the portion not protected by the photoresist pattern 25 is removed by dry etching. At this time, the etching conditions are BCl 3 47 sccm, SF 6 28 sccm and 35 W.
그 다음, 동일한 장비에서 포토레지스트패턴(25)으로 보호되지 아니하는 부위의 주 금속배선인 Al층(23)을 BCl360 sccm, Cl265 sccm에 82W의 조건으로 타임 에칭(time etch)한다. 이때 식각되는 두께는 원래의 두께에서 70-95%이며 나머지 부분(26)이 하부 배리어금속층(22) 위에 잔류하게 된다.Next, in the same equipment, the time-etched Al layer 23, which is the main metal wiring of the portion not protected by the photoresist pattern 25, is subjected to 82 W at a condition of BCl 3 60 sccm and Cl 2 65 sccm. . At this time, the thickness to be etched is 70-95% from the original thickness and the remaining portion 26 remains on the lower barrier metal layer 22.
도 2c를 참조하면, 계속하여 기판의 포토레지스트패턴으로 보호되지 아니하는 부위의 Al층(23)의 노출 부위를 언더 에치하기 위하여 노출부위에 습식식각을 실시하여 하부 배리어금속층(22)의 일부 표면(26)을 노출시키며, 또한 노출된 Al층(23)의 하부측면(27)이 언더 에치된다. 이때, 식각조건은 CPD-18 식각제에 30-120″ 딥(dip)하여 실시하며, 기판의 나머지 부위는 역시 포토레지스트패턴(25)으로 여전히 보호된다.Referring to FIG. 2C, a portion of the lower barrier metal layer 22 is wet-etched by performing wet etching on the exposed portion to underetch the exposed portion of the Al layer 23 at the portion not protected by the photoresist pattern of the substrate. (26) is exposed, and the lower side 27 of the exposed Al layer 23 is under etched. At this time, the etching conditions are performed by dipping 30-120 "into the CPD-18 etchant, and the rest of the substrate is still protected by the photoresist pattern 25.
도 2d를 참조하면, 포토레지스트패턴(25)을 제거한다. 이후, 금속배선의 부식방지를 위하여 오존처리를 하여 노출된 Al층(23)의 표면에 부동태막(도시 안함)인 Al2O3를 형성한다.Referring to FIG. 2D, the photoresist pattern 25 is removed. Subsequently, in order to prevent corrosion of the metal wiring, Al 2 O 3 , which is a passivation film (not shown), is formed on the surface of the exposed Al layer 23 by ozone treatment.
따라서 노출된 배리어 금속층(26)이 본 발명에 따른 퓨즈가 되며, 여기에 약 7.5V의 전압을 인가하면 브레이크다운(breakdown)효과에 의하여 퓨즈로서 동작한다.Accordingly, the exposed barrier metal layer 26 becomes a fuse according to the present invention, and when a voltage of about 7.5V is applied thereto, the barrier metal layer 26 operates as a fuse due to a breakdown effect.
본 발명의 다른 실시예로, 도 2b단계에서, 퓨즈 형성시 하부 배리어금속층과 Al층의 식각건택비를 이용하여 퓨즈부 상부의 Al층만을 제거하는 방법도 본 발명은 포함한다.In another embodiment of the present invention, in the step of FIG. 2B, the method includes removing only the Al layer on the upper portion of the fuse unit by using an etching dry ratio between the lower barrier metal layer and the Al layer when forming the fuse.
따라서, 본 발명에 따라 형성된 퓨즈는 금속배선 형성시 하부 배리어금속으로 제조하므로서 소자의 고집적화 및 설계의 단순화에 유리하고, 퓨즈 절단시 레이저 등의 고가 장비가 필요하지 않아 비용면에서도 유리한 장점이 있다.Therefore, the fuse formed in accordance with the present invention is advantageous in terms of high integration of the device and simplifying the design by manufacturing the lower barrier metal when the metal wiring is formed, and it is advantageous in terms of cost since no expensive equipment such as a laser is required when cutting the fuse.
Claims (5)
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|---|---|---|---|
| KR1019980044512A KR20000026808A (en) | 1998-10-23 | 1998-10-23 | Method for forming fuse of semiconductor devices |
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| KR1019980044512A KR20000026808A (en) | 1998-10-23 | 1998-10-23 | Method for forming fuse of semiconductor devices |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7923307B2 (en) | 2007-12-27 | 2011-04-12 | Hynix Semiconductor Inc. | Semiconductor device with fuse and method for fabricating the same |
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1998
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7923307B2 (en) | 2007-12-27 | 2011-04-12 | Hynix Semiconductor Inc. | Semiconductor device with fuse and method for fabricating the same |
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