KR100309904B1 - Method for manufacturing metal interconnection of semiconductor device - Google Patents
Method for manufacturing metal interconnection of semiconductor device Download PDFInfo
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- KR100309904B1 KR100309904B1 KR1019940019529A KR19940019529A KR100309904B1 KR 100309904 B1 KR100309904 B1 KR 100309904B1 KR 1019940019529 A KR1019940019529 A KR 1019940019529A KR 19940019529 A KR19940019529 A KR 19940019529A KR 100309904 B1 KR100309904 B1 KR 100309904B1
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- metal wiring
- layer
- contact hole
- metal layer
- metal
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- 229910052751 metal Inorganic materials 0.000 title claims abstract description 107
- 239000002184 metal Substances 0.000 title claims abstract description 107
- 238000000034 method Methods 0.000 title claims abstract description 30
- 239000004065 semiconductor Substances 0.000 title claims abstract description 30
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 15
- 230000004888 barrier function Effects 0.000 claims abstract description 31
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 22
- 238000005530 etching Methods 0.000 claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 239000010410 layer Substances 0.000 claims description 62
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 8
- 229910000838 Al alloy Inorganic materials 0.000 claims description 2
- 229910000881 Cu alloy Inorganic materials 0.000 claims description 2
- 239000010953 base metal Substances 0.000 claims description 2
- 239000002356 single layer Substances 0.000 claims description 2
- 229920000642 polymer Polymers 0.000 abstract description 5
- 238000002955 isolation Methods 0.000 abstract description 3
- 238000001465 metallisation Methods 0.000 abstract description 3
- 230000002708 enhancing effect Effects 0.000 abstract 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 7
- 229910052721 tungsten Inorganic materials 0.000 description 7
- 239000010937 tungsten Substances 0.000 description 7
- 239000012535 impurity Substances 0.000 description 6
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 3
- 229910052731 fluorine Inorganic materials 0.000 description 3
- 239000011737 fluorine Substances 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000002904 solvent Substances 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000005012 migration Effects 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 230000007261 regionalization Effects 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
본 발명은 반도체소자의 금속배선 제조방법에 관한 것으로서, 특히 금속배선의 하부에 개재되는 접합 스파이크 방지용 장벽금속층을 금속배선 콘택 부분만 남기고 제거하여 금속배선에 의한 단차를 감소시켜 후속 공정여유도를 증가시키고, 금속배선 식각 공정을 용이하게 하여 공정수율 및 소자동작의 신뢰성을 향상시킬 수 있는 반도체소자의 금속배선 제조방법에 관한 것이다.The present invention relates to a method for manufacturing a metal wiring of a semiconductor device, and in particular, to remove the junction spike prevention barrier metal layer interposed on the lower portion of the metal wiring, leaving only the metal wiring contact portion to reduce the step by metal wiring to increase the subsequent process margin. The present invention relates to a method for manufacturing a metal wiring of a semiconductor device, which facilitates a metal wiring etching process to improve process yield and reliability of device operation.
최근 반도체 소자의 고집적화 추세는 미세 패턴 형성기술의 발전에 많은 영향을 받고 있다. 특히 사진 공정에 의해 형성되는 감광막 패턴은 반도체 소자의 제조 공정중에서 식각 또는 이온 주입 공정 등의 마스크로 매우 폭 넓게 사용되고 있다.Recently, the trend of high integration of semiconductor devices has been greatly influenced by the development of fine pattern formation technology. In particular, the photosensitive film pattern formed by the photolithography process is widely used as a mask such as an etching process or an ion implantation process in a semiconductor device manufacturing process.
도시되어 있지는 않으나, 종래 반도체소자의 미세패턴 제조방법을 살펴보면 다음과 같다.Although not shown, a method of manufacturing a fine pattern of a conventional semiconductor device is as follows.
먼저, 미세패턴이 되는 피식각 도전층이 형성되어 있는 반도체 웨이퍼 상에 감광제와 수지(resin) 등이 용제인 솔벤트에 일정 비율로 용해되어 있는 감광액을 균일하게 도포하고, 상기 감광막을 선택적으로 노광한 후, 알카리성 현상액으로 처리하여 감광막패턴을 형성하고, 상기 감광막패턴을 마스크로 도전층을 식각하여 미세패턴을 형성한다.First, a photosensitive solution dissolved in a fixed ratio in a solvent in which a photosensitive agent, a resin, and the like is dissolved in a solvent on a semiconductor wafer on which an etched conductive layer serving as a fine pattern is formed is uniformly exposed, and the photosensitive film is selectively exposed. Subsequently, the photoresist pattern is formed by treating with an alkaline developer, and the conductive layer is etched using the photoresist pattern as a mask to form a fine pattern.
상기와 같은 종래 도전배선 미세패턴은 (배선의 폭)/ (배선간 간격) 즉 라인/스페이스가 상기 감광막패턴의 분해능에 따라 좌우된다.In the conventional conductive wiring fine pattern as described above, (width of wiring) / (interval between wirings), that is, the line / space depends on the resolution of the photoresist pattern.
따라서 감광막 패턴의 미세화, 공정 진행의 안정성, 공정 완료 후의 깨끗한 제거 그리고 잘못 형성된 감광막 패턴을 제거하고 다시 형성하는 재작업의 용이성등이 필요하게 되었다.Accordingly, there is a need for miniaturization of the photoresist pattern, stability of process progression, clean removal after completion of the process, and ease of rework to remove and re-form incorrectly formed photoresist pattern.
일반적인 감광막패턴 형성 기술은 노광장치의 정밀도, 광의 파장 등과 같은 많은 제약요인에 의해 어느 정도, 예를 들어, 광파장이 각각 436, 365 및 248nm인 G-라인, i-라인 및 엑시머 레이저를 광원으로 사용하는 축소노광장치의 공정분해능으로는 약 0.7μm, 0.5μm, 0.3μm 정도 크기의 패턴을 형성하는 것이 한계이다.The general photoresist pattern forming technique uses, for example, G-line, i-line, and excimer lasers having a light wavelength of 436, 365, and 248 nm, respectively, to some extent due to many constraints such as the accuracy of the exposure apparatus and the wavelength of light. The process resolution of the reduced exposure apparatus is limited to forming a pattern having a size of about 0.7 μm, 0.5 μm, and 0.3 μm.
현재 64M 디램급 이상의 고집적 반도체 소자에서는 0.5μm 이하의 금속배선이 사용되는데, 이러한 금속배선으로 단차피복성과 전자이주(electron migration) 특성이 우수한 텅스텐을 알루미늄 대신 사용하며, 상기 텅스텐의 접합 스파이크를 방지하기 위하여 Ti, TiN 또는 Ti/TiN 적층 구조로된 장벽금속층을 개재시키며, 식각 마스크인 감광막패턴 두께를 감소시키기 위하여 하드 마스크를 사용하기도 한다.Currently, high-density semiconductor devices of less than 0.5μm are used in high-density semiconductor devices of 64M DRAM or more.Tungsten, which has excellent step coverage and electron migration characteristics, is used instead of aluminum to prevent junction spikes of the tungsten. In order to interpose a barrier metal layer having a Ti, TiN or Ti / TiN laminated structure, a hard mask may be used to reduce the thickness of the photoresist pattern which is an etching mask.
도시되어 있지는 않으나, 종래 반도체소자의 금속배선 콘택 제조방법을 살펴보면 다음과 같다.Although not shown, a method of manufacturing a metallization contact of a conventional semiconductor device is as follows.
먼저, 반도체기판 상에 소정구조를 형성하고, 전 표면에 절연막을 도포한다. 그 다음 상기 반도체기판에서 금속배선 콘택으로 예정되어 있는 부분상의 절연막을 제거하여 금속배선 콘택홀을 형성하고, 상기 구조의 전표면에 접합 스파이트 방지용으로 장벽금속층과 텅스텐층을 각각 소정 두께 형성한 후, 상기 텅스텐층의 패턴으로 예정되어 있는 부분 상에 감광막패턴을 형성한다.First, a predetermined structure is formed on a semiconductor substrate, and an insulating film is coated on the entire surface. Then, the insulating film on the portion of the semiconductor substrate, which is supposed to be a metal wiring contact, is removed to form a metal wiring contact hole, and a barrier metal layer and a tungsten layer are formed on the entire surface of the structure to prevent bonding spikes, respectively, and then a predetermined thickness is formed. A photosensitive film pattern is formed on a portion of the tungsten layer.
그 후 상기 감광막패턴에 의해 노출되어 있는 텅스텐층과 장벽금속층을 SF6/Ar 혼합가스를 사용한 불소 플라즈마로 건식 이방성식각하여 순차적으로 제거하여 텅스텐층 및 장벽금속층 패턴으로 된 금속배선을 형성한 후, 잔존하는 폴리머를 NH4OH나 현상액 등의 유기용액으로 제거한다.Thereafter, the tungsten layer and the barrier metal layer exposed by the photoresist pattern are dry anisotropically etched by fluorine plasma using a SF 6 / Ar mixed gas to sequentially remove the tungsten layer and the barrier metal layer pattern to form a metal wiring. The remaining polymer is removed with an organic solution such as NH 4 OH or a developing solution.
이때 상기 텅스텐층은 불소 플라즈마에 식게 제거되나, Ti, TiN 또는 Ti/TiN으로 된 장벽금속층은 불소 플라즈마에서 TiFx 이나 TiNFx로 된 비휘발성 폴리머가 생성되어 패턴의 측벽에 붙게 된다.At this time, the tungsten layer is coolly removed in the fluorine plasma, but the barrier metal layer made of Ti, TiN, or Ti / TiN forms a nonvolatile polymer made of TiFx or TiNFx in the fluorine plasma and adheres to the sidewall of the pattern.
상기 폴리머성 잔류물은 식각조건이나 사용 가스에 따라 생성되는 정도가 조금씩은 다르나, NH4OH 나 현상액 등의 유기용액으로 쉽게 제거되지 않아, 금속배선의 측벽을 경사지게 하여 패턴의 임계크기(critical dimension)가 커지고, 심한 경우 금속배선이 단락되는 브릿지 현상이 발생하거나, 후속 절연막 공정 전에 별도로 폴리머 세척 공정을 실시하여야 하므로 공정수율 및 소자동작의 신뢰성이 떨어지는 문제점이 있다.The polymeric residue is slightly different depending on the etching conditions and the gas used, but is not easily removed with an organic solution such as NH 4 OH or a developing solution, so that the sidewall of the metal wiring is inclined to form a critical dimension of the pattern. ), And in severe cases, a bridge phenomenon in which a metal wiring is shorted, or a polymer cleaning process must be performed separately before a subsequent insulating film process, has a problem in that process yield and device operation reliability are deteriorated.
또한 상기 장벽금속층은 식각비가 금속층에 비해 매우 낮아 감광막의 두께를 그만큼 두껍게 형성하여야 하는 등 공정에 많은 제약을 주어 후속 공정의 공정여유도가 감소되는 문제점이 있다.In addition, the barrier metal layer has a problem that the etch ratio is much lower than that of the metal layer, so that the thickness of the photoresist film needs to be formed so much that the process margin is reduced.
본 발명은 상기와 같은 문제점을 해결하기 위한 것으로서, 본 발명의 목적은 금속배선 콘택홀의 내부에만 장벽금속층이 남도록 하고 나머지 부분은 금속층 형성전에 제거하여 금속배선에 의한 단차를 감소시키고, 장벽금속층 식각 시 생성되는 폴리머성 잔류물에 의한 금속배선의 불량을 방지하여 공정수율 및 소자동작의 신뢰성을 향상시킬 수 있는 반도체소자의 금속배선 제조방법에 관한 것이다.The present invention is to solve the above problems, an object of the present invention is to leave the barrier metal layer only inside the metal wiring contact hole and to remove the remaining portion before forming the metal layer to reduce the step by the metal wiring, when barrier metal layer etching The present invention relates to a method for manufacturing a metal wiring of a semiconductor device, which can prevent defects in the metal wiring caused by the resulting polymeric residue, thereby improving process yield and device operation reliability.
상기와 같은 목적을 달성하기 위한 본 발명에 따른 반도체소자의 금속배선 제조방법의 특징은,Features of the metallization manufacturing method of a semiconductor device according to the present invention for achieving the above object,
소정의 하부구조물이 구비되는 반도체기판 상부에 절연막을 형성하는 공정과, 상기 반도체기판에서 금속배선 콘택으로 예정되는 부분을 노출시키는 금속배선 콘택마스크를 식각마스크로 상기 절연막을 식각하여 금속배선 콘택홀을 형성하는공정과, 전체표면 상부에 소정 두께의 장벽금속층을 형성하는 공정과, 상기 장벽금속층 상부에 상기 금속배선 콘택홀이 매립되도록 감광막을 도포하는 공정과, 상기 감광막을 전면 이방성식각하여 상기 금속배선 콘택홀 내부에 감광막패턴을 플러그형태로 형성하는 공정과, 상기 감광막패턴을 식각마스크로 상기 장벽금속층을 식각하여 상기 금속배선 콘택홀 내부 표면에 장벽금속층패턴을 형성하는 공정과, 상기 감광막패턴을 제거하는 공정과, 전체표면 상부에 상기 금속배선 콘택홀이 매립되도록 금속층을 형성하는 공정과,Forming an insulating film on the semiconductor substrate provided with a predetermined lower structure, and etching the insulating film with a metal wiring contact mask that exposes a portion of the semiconductor substrate to be a metal wiring contact. Forming a barrier metal layer having a predetermined thickness over the entire surface, applying a photoresist film so as to fill the metal wiring contact hole on the barrier metal layer, and anisotropically etching the photosensitive film to the metal wiring. Forming a barrier metal layer pattern on the inner surface of the metal wiring contact hole by etching the barrier metal layer using an etch mask using the photoresist pattern as an etch mask; and removing the photoresist pattern. And a metal layer so that the metal wiring contact hole is buried in the entire surface. Forming process,
상기 금속층을 금속배선 마스크를 식각마스크로 사용하여 식각해서 상기 금속배선 콘택홀을 통하여 반도체기판에 접속되는 장벽금속층 및 금속배선의 적층 구조와 절연막 상의 금속배선을 형성하는 공정을 구비함에 있다.And etching the metal layer using a metal wiring mask as an etch mask to form a stacked structure of a barrier metal layer and a metal wiring connected to the semiconductor substrate through the metal wiring contact hole and a metal wiring on the insulating film.
이하, 본 발명에 따른 반도체소자의 금속배선 제조방법에 관하여 첨부도면을 참조하여 상세히 설명한다.Hereinafter, a method for manufacturing a metal wiring of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.
제 1A 도 내지 제 1E 도는 본 발명에 따른 반도체소자의 금속배선 제조 공정도이다.1A to 1E are process diagrams for manufacturing metal wirings of a semiconductor device according to the present invention.
먼저, 반도체기판(1)상에 소자분리 절연막(2)과 불순물 접합층(3)을 형성하고, 도시되지 않은 소정구조, 예를 들어 게이트전극이나 비트라인 또는 캐패시터 등을 순차적으로 형성한 후, 상기 구조의 전 표면에 산화막이나 질화막으로 된 절연막(4)을 도포하여 평탄화시킨다.First, the element isolation insulating film 2 and the impurity bonding layer 3 are formed on the semiconductor substrate 1, and then a predetermined structure, for example, a gate electrode, a bit line, a capacitor, or the like is sequentially formed, An insulating film 4 made of an oxide film or a nitride film is coated and planarized on the entire surface of the structure.
그 다음 상기 불순물 접합층(3)에서 금속배선 콘택으로 예정되어 있는 부분상의 절연막(4)을 제거하여 금속배선 콘택홀(8)을 형성하고, 상기 구조의 전 표면에 Ti, TiN 단일막 또는 Ti/TiN 적층막으로 된 장벽금속층(5)을 형성한다. (제 1A 도 참조).Then, the insulating film 4 on the part scheduled as the metal wiring contact is removed from the impurity bonding layer 3 to form the metal wiring contact hole 8, and Ti, TiN single film or Ti is formed on the entire surface of the structure. A barrier metal layer 5 made of a / TiN laminated film is formed. (See also FIG. 1A).
그후, 상기 구조의 전 표면에 감광막(6)을 도포하여 상기 금속배선 콘택홀(8)을 메우고, 전면 이방성식각으로 에치백하여 상기 감광막(6)의 소정두께를 제거하여 상기 금속배선 콘택홀(8)의 내부에만 감광막(6) 패턴이 남도록하여 금속배선 콘택홀(8) 상측의 장벽금속층(5)을 노출시킨다. (제 1B 도 참조).Thereafter, the photoresist film 6 is applied to the entire surface of the structure to fill the metal wiring contact hole 8, and is etched back with a front anisotropic etch to remove the predetermined thickness of the photoresist film 6 to remove the predetermined thickness of the metal wiring contact hole ( The photoresist film 6 pattern remains only inside the 8) to expose the barrier metal layer 5 above the metal wiring contact hole 8. (See also FIG. 1B).
그 다음 상기 노출되어 있는 장벽금속층(5)을 에치백으로 제거하여 금속배선 콘택홀(8) 이외 부분의 절연막(4)을 노출시키고, 상기 감광막(6)을 제거한다. (제 IC 도 참조).The exposed barrier metal layer 5 is then removed with an etch back to expose the insulating film 4 in a portion other than the metal wiring contact hole 8, and the photosensitive film 6 is removed. (See also IC).
그 후 상기 구조의 전 표면에 소정재질, 예를 들어 Al, Cu, Al과 Cu 합금 베이스 금속 등으로 된 금속층(7)을 도포하여 상기 금속배선 콘텍홀(8)을 통하여 불순물 접합층(3)과 접촉시킨다. (제 1D 도 참조).The impurity bonding layer 3 is then applied to the entire surface of the structure by applying a metal layer 7 made of a predetermined material, for example, Al, Cu, Al and Cu alloy base metals, through the metal wiring contact hole 8. Contact with. (See also FIG. 1D).
그 다음 금속배선용 마스크(도시되지 않음)를 사용하여 상기 금속층(7)을 패턴닝하여 상기 금속배선 콘택홀(8)에서는 금속층(7) 패턴과 장벽금속층(5)의 적층 구조로 되어 불순물 접합층(3)과 접촉되는 금속배선과, 절연막(4)의 상측에서 금속층(7) 패턴으로된 금속배선을 형성한다. (제 1E 도 참조).Then, the metal layer 7 is patterned by using a metal wiring mask (not shown). In the metal wiring contact hole 8, the metal layer 7 pattern and the barrier metal layer 5 are laminated to form an impurity bonding layer. Metal wiring in contact with (3) and metal wiring in a pattern of the metal layer 7 on the insulating film 4 are formed. (See also FIG. 1E).
이상에서 설명한 바와 같이, 본 발명에 따른 반도체소자의 금속배선 제조방범은 소정구조의 반도체기판 상에 금속배선 콘택홀을 구비하는 절연막을 형성하고 상기 구조의 전 표면에 접합 스파이크를 방지하기 위한 장벽금속층을 형성한 후, 콘택홀을 메운 감광막 패턴을 마스크로하여 절연막 상의 장벽금속층을 제거하여 콘택홀의 내부에만 장벽금속층이 남도록 하고 상기 콘택홀을 통하여 불순물 접합층과 접촉되는 장벽금속층 및 금속층 패턴의 적층구조의 금속배선을 형성하고, 상기 절연막 상에는 금속층 패턴 단일막으로 된 금속배선을 형성하였으므로, 절연막 상에서는 금속배선에 의한 단차가 감소되고, 장벽금속층 식각 시 생성되는 폴리머성 잔류물에 의한 금속배선의 불량을 방지하여 후속공정시의 공정여유도가 증가되고 공정수율 및 소자동작의 신뢰성을 향상시킬 수 있는 이점이 있다.As described above, in the manufacture of metal wiring of the semiconductor device according to the present invention, a barrier metal layer for forming an insulating film having a metal wiring contact hole on a semiconductor substrate having a predetermined structure and preventing junction spikes on the entire surface of the structure After the formation, the barrier metal layer on the insulating layer is removed by using the photoresist pattern filling the contact hole as a mask so that the barrier metal layer remains only inside the contact hole, and the stacked structure of the barrier metal layer and the metal layer pattern contacting the impurity bonding layer through the contact hole. Since metal wirings were formed, and metal wirings formed of a single layer of metal layer pattern were formed on the insulating film, the step difference caused by the metal wiring was reduced on the insulating film, and the defects of the metal wiring due to the polymer residue generated during etching of the barrier metal layer were reduced. Process margin in the subsequent process by increasing the process yield There is an advantage that can improve the reliability of the operation.
제 1A 도 내지 제 1E 도는 본 발명에 따른 반도체소자의 금속배선 제조 공정도.1A to 1E are diagrams illustrating a process for manufacturing metal wiring of a semiconductor device according to the present invention.
< 도면의 주요부분에 대한 부호의 설명 ><Description of Symbols for Major Parts of Drawings>
1 : 반도체기판 2 : 소자분리 절연막1: semiconductor substrate 2: device isolation insulating film
3 : 불순물 접합층 4 : 절연막3: impurity bonding layer 4: insulating film
5 : 장벽금속층 6 : 감광막5: barrier metal layer 6: photosensitive film
7 : 금속층 8 : 금속배선 콘택홀7: metal layer 8: metal wiring contact hole
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| KR1019940019529A KR100309904B1 (en) | 1994-08-08 | 1994-08-08 | Method for manufacturing metal interconnection of semiconductor device |
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| Application Number | Priority Date | Filing Date | Title |
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| KR1019940019529A KR100309904B1 (en) | 1994-08-08 | 1994-08-08 | Method for manufacturing metal interconnection of semiconductor device |
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| KR960009119A KR960009119A (en) | 1996-03-22 |
| KR100309904B1 true KR100309904B1 (en) | 2003-09-06 |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03236238A (en) * | 1990-02-13 | 1991-10-22 | Fujitsu Ltd | Semiconductor device and manufacture thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03236238A (en) * | 1990-02-13 | 1991-10-22 | Fujitsu Ltd | Semiconductor device and manufacture thereof |
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