KR20000025559A - Method for compressing and restoring direct memory access controller - Google Patents

Abstract

PURPOSE: A method for compressing and restoring data is provided to embody a DMA(Direct Memory Access) controller having a compressing function and a restoring function in a hardware. CONSTITUTION: A DMA(Direct Memory Access) controller includes a controller receiving a control signal and data from a CPU(Central Processing Unit) and an input/output unit, and outputting a transmission data column by compressing or restoring the control signal and the data. A method for compressing and restoring data comprises the steps of: selecting one operation of a compressing operation and a restoring operation, by receiving the control signal and the data; reading data of an original data column among the data from the CPU and the input/output unit, in a control section in order, and temporarily storing to a first buffer and a second buffer; examining whether a redundancy is generated in data of the first buffer and the second buffer, transmitting data corresponding to the redundancy number of times and redundant data only, and compressing when the compressing operation is performed; repeating the redundant data as the redundant number of times by the data corresponding to the redundant number of times, transmitted by the compressing process, and restoring the data.

Description

How to compress and restore a direct memory access controller

The present invention relates to a direct memory access controller, and more particularly, to a direct memory access controller having compression and recovery functions.

Direct memory access (hereinafter referred to as "DMA") refers to peripheral devices, such as the first memory on the system board, without being processed by a central processing unit (hereinafter referred to as "CPU"). When data is transferred between the second memories, the data is directly accessed by transferring the data. In fact, the data transfer control by the direct memory access operation is performed by the DMA controller.

The data transfer method of the DMA controller is largely divided into the following two types.

First, using a fly-by-mode that reads data from the source memory area and keeps it on the bus inside the device, writing to the destination memory area. Second, using an internal buffer. It is a buffered mode that fills the buffer with data read from the source memory area and writes to the destination memory once the buffer is full.

However, the above two methods have the following problems in terms of transmission efficiency when a large amount of data is to be transmitted.

The first method, fly-by mode, keeps data on the bus, which reduces the efficiency of the bus and limits data transfer depending on the data structure of the bus. In addition, in the second mode, the buffer mode is limited in the amount of data transmitted in accordance with the size of the buffer, and when the size of the buffer is small, a large transfer time is required by the large amount of data to be transmitted.

The above problems are further raised in the transmission of data by office equipment, in particular printers or scanners or multifunction devices resulting from the recent integration of office environments. In the source memory of these office equipments, the same data such as blanks or lines is often repeated. The transfer operation of the DMA controller that transfers the same data is similarly repeated.

Therefore, the DMA controller in such a case occupies the system bus for a long time while repeating the same operation for data transmission, and thus has an undesired result in terms of data transmission efficiency.

Accordingly, an object of the present invention is to implement a DMA controller having a function of compressing a redundant data string in a data string transmitted from a source memory and a function of restoring the compressed data in hardware to increase data transmission efficiency and more efficiently memory. To use it.

1 is an external view of a direct memory access controller having a compression and decompression function according to an embodiment of the present invention.

2 is a block diagram of a direct memory access controller having compression and decompression functions in accordance with an embodiment of the present invention.

3 is a detailed block diagram of the controller of FIG. 2.

4 is a state table showing the internal state of the direct memory access controller compressing the original data string " 1a, 22, 22, 33, 1a, la, la " according to an embodiment of the present invention.

5 is a flowchart illustrating a compression process according to an embodiment of the present invention.

6 is a flowchart illustrating a restoration process according to an embodiment of the present invention.

In order to achieve the above object, the present invention includes a control unit for outputting a transmission data string by receiving an original data string from a direct memory access controller for transmitting data in a buffer mode with an internal buffer and a local bus, and compressing or restoring the original data string.

Here, the control unit compares the data of the original data sequence in turn, checks whether the data is compressed and overlapped, and compresses or restores the original data sequence by changing the internal state, and decodes according to the result data to decode the clock signal and the control signal. It consists of a finite state machine that outputs

The present invention may further include an input unit for receiving data and control signals for initialization from a central processing unit and an input / output device and outputting the data and control signals to a corresponding functional unit, and a register unit for receiving the data and control signals and setting a plurality of registers. .

The present invention may further include a bus interface unit controlling the memory controller to transfer the transfer data sequence to the target memory according to a control signal of the controller.

The present invention may further include a buffer unit which receives the transmission data string and temporarily stores the transmission data string and outputs the transmission data string to the local bus by a control signal of the controller.

The algorithm for implementing the compression and decompression function of the present invention is modified run length encoding (MRLE), which is applied to the run length encoding (RLE) algorithm applied in the extended capability port (ECP) mode of the Institute of Electrical and Electronic Engineers (IEEE) 1284. The algorithm decided to limit the run length counter (RLC) from -N to + N.

The MRLE algorithm is as follows.

When there is an original data string that is a series of data streams, the compressed transmission data string inserts one byte data and a signed RLC value in front of the redundant byte data. Here, a positive sign of the RLC value indicates that (N + 1) different data are consecutive, and a negative sign indicates that the same data is consecutive (N + 1) times.

For example, suppose the original data string is 1a, 1a, 1a, 1a, ..., 1a (16th iteration), 22, 33. In this case, since 1a is repeated 16 times, it is represented by -15 and 1a in the transmission data string.

The operation reads the first data 1a from the original data string and then compares it by reading the second data 1a. Here, since the two data are the same, the RLC value becomes -1, and the third data 1a is read and compared with the second data. Since both data are still the same, the RLC value decreases. In this way, if the same 16 1a data is read and the next data 22 is read, the two data are different, so the RLC value stops at -15 and -15 and 1a are written in the transmission data string. Again, after reading 22, the next data 33, and comparing the two data, the data is different, and 1, 22, and 33 are written in the transmission data string.

As described above, the DMA controller operating according to the compression algorithm described above has an internal buffer of (M + 1) bytes so that the redundant data stream is compressed into 2 bytes, so the maximum compression ratio is (1-2 / (1 + M). )) * 100%. Thus, the 16 consecutive 1a data sequences given above have a compression ratio of 87.5%, which is (1- (2/16)) * 100%.

A hardware controller designed to operate according to this MRLE algorithm is described.

1 is an external view of a DMA controller having a compression and decompression function according to an embodiment of the present invention.

The DMA controller receives a reset signal RESET, a clock signal CLK, an address signal AS, a chip select signal CS, a DMA request signal DREQ, and a bus enable signal BACK as input signals. The DMA controller also outputs a DMA enable signal DACK, a bus request signal BREQ, an interrupt signal INT, an address signal SAS, and the like as output signals.

2 is a block diagram of a direct memory access controller having a compression and decompression function according to an embodiment of the present invention.

The DMA controller 100 is connected to an external bus XD to exchange data and control signals with a CPU or peripheral devices. In particular, the DMA controller 100 accesses the memories 300 and 400 via the memory controller 200. Therefore, the memory controller 200 is located between the memory 300, 400 and the DMA controller 100, and exchanges data and control signals with the memory 300, 400 through the external bus XD and transfers the data and control signals to the DMA controller 100.

The DMA controller 100 includes an input unit 110, a register unit 120, a controller 130, a bus interface unit 140, and a buffer unit 150.

The input unit 110 is connected to the system bus SD in the DMA controller 100 and buffers the input signal to the register unit 120 or the control unit 130.

The register unit 120 has a source address register, a destination address register, a word count register or a control register for the DMA controller 100 to operate. Here, these registers are initialized and operated by the CPU, thereby setting the bits of the control register to control the operation of the DMA controller.

Since the controller 130 includes a finite state machine and a decoder, the controller 130 outputs the data output from the input unit 110 and the register unit 120, the input signal, and the previous state output from the controller 130. It works by receiving input. The outputs are input to the bus interface unit 140 and the buffer unit 150, respectively.

3 is a detailed block diagram of the controller of FIG. 2.

The control unit includes a first buffer 131, a second buffer 132, a comparator 133, a first register 134, a second register 135, a third register 136, and a finite state machine 137. It is done by Here, the first buffer 131 and the second buffer 132 temporarily stores data read from the original data string. The values stored in these two buffers 131, 132 are then compared by the comparator 133, and then the result is input to the finite state machine 137. In addition, the first register 134, the second register 135 and the third register 136 stores the result output from the comparator. Thus, this result is used by the finite state machine 137 to calculate the number of duplicate data. The finite state machine 137 receives the inputs of the comparator 133 and the first register 134 to the third register 136 to perform data compression, and then generates a transmission data string and stores the transmission data string in the buffer unit 150.

The bus interface unit 140 controls the memory controller 200 to transmit the transmission data string in the buffer unit 150 to the destination memory 400 according to the output of the controller 130.

The buffer unit 150 is connected to the local bus LD in the DMA controller 100 to store the transmission data string generated by the output of the controller 130. In addition, the buffer unit 150 outputs the transmission data string to the local bus according to the control signal of the controller.

Hereinafter, the operation according to the configuration of the present invention shown in Figures 1 to 3 will be described in detail. Suppose there is a data transfer request from the source memory 300 to the target memory 400, and the data strings to which transfer is requested are " la, 22, 22, 33, la, la, la. &Quot;

The DMA controller 100 receives a DMA request signal through an input pin DREQ, and thus sends a bus request signal to the CPU through an output pin BREQ. Upon receiving this signal, the CPU outputs a bus permission signal to the DMA controller 100. The DMA controller 100 receives the signal through the input pin BACK, occupies the bus, and outputs a response signal for the DMA request signal through the output pin DACK.

The CPU transfers the source memory address, the target memory address, the number of data bytes, and the like to the DMA controller 100. Then, the input unit 110 of the DMA controller 100 sends this to the register unit 120 and sets the values in a register inside the DMA controller 100 so that the DMA controller 100 starts to operate.

Next, the DMA controller 100 reads the original data string from the source memory address through the memory controller 200. The input unit 110 transmits the original data string read in this manner to the control unit 130. The controller 130 first places the input data in the first buffer 131. Accordingly, la, which is the first data of the original data string, is input to the first buffer 131 and 22, which is the next data, is input to the second buffer 132. After the values of the first buffer 131 and the second buffer 132 are compared in the comparator 133, the result is input to the finite state machine 137 and the first register 134. The first register 134 to the third register 136 sequentially latch the output values of the comparator 133, and the values of the first register 134 are sequentially latched to the second register 135. This register value is also input to the finite state machine 137. The finite state machine 137 receives the output value of the comparator 133 and the values of the first register 134 to the third register 136 and changes the state to generate the transmission data string according to the MRLE algorithm described above. Also, a buffer read / write signal to be output to the bus interface unit 140 is output through the decoder in the finite state machine 137. The completed transmission data string is output to the buffer unit 150 and the transmission data string of the buffer unit 150 is stored at the target memory address via the memory controller 200 under the control of the buffer interface unit 140.

4 is a state table showing an internal state in the compression process according to the original data strings " 1a, 22, 22, 33, 1a, la, la " input to the DMA controller 100. FIG.

In the state table of FIG. 4, fData is data of the first 1 byte of the original data string input to the first buffer 131 of the control unit 130 of the DMA controller 100, and ffData is the data of the second buffer 132 indicating previous data. When fDate is updated with a value, it has the value of the previous fData.

L / M represents the buffer unit 150, which is an internal buffer, and EQ has a value of 1 if fData and ffData are the same as a result of the comparator 133, and a value of 0 if not equal. . rEQ is the value of the first register 134 having the value of the previous EQ as a result of the comparator 133. rrEQ is the value of the second register 135 having the value of the previous rEQ, and rrrEQ is the value of the third register 136 having the value of the previous rrEQ. rlc is a count value indicating the number of overlaps. When the data string is duplicated once, it has a value of -1, and when the three duplicated data strings are input to the controller 130 of the DMA controller 100, rlc has a value of -2. .

5 is a flow chart illustrating a compression process based on the MRLE algorithm.

In the embodiment of the present invention, the compression process of the original data string "1a, 22, 22, 33, 1a, 1a, 1a" will be described using the state table of FIG. 4 and the flowchart of FIG.

As shown in FIG. 5, the first two bytes 1a and 22 are read from the original data string (S500 and S510). Accordingly, as shown in the state table of FIG. 4, fData and ffDate have values of 1a and 22, respectively, and the EQ value has a value of 0 since the two data are not equal. Since the value of the EQ is 0, rEQ becomes 0 when the state check step is reached. When the original data string is first input, the EQ value is set to 0, so the value of rrEQ in the status check step becomes 0.

The state check step in the flowchart of FIG. 5 is divided into four steps by rEQ, rrEQ, rrrEQ and rlc. The four steps are branched when expressed by the following logical expression.

[Logical expression 1]

① ~ rEQ & rrEQ

② (rEQ & ~ rrEQ & rrrEQ) | (rEQ & rrEQ) | (rEQ & ~ rrEQ & ~ rrrEQ & (rlc = 0))

③ rEQ & ~ rrEQ & ~ rrrEQ & (rlc ≠ 0)

④ ~ rEQ & ~ rrEQ

For example, when rEQ is 1, rrEQ and rrrEQ are 0, and rlc has a value of 1, the branch by status check branches to ③.

The following describes compression by taking the original data string "1a, 22, 22, 33, 1a, 1a, 1a" as an example.

Since the values of rEQ and rrEQ are both 0 by the input two byte values 1a and 22, the fourth branching is performed (S520). Here, rlc is increased (S530), and the initial rlc value is designated as 0, so the rlc value is 1. Then, it is compared whether the rlc value is the maximum value (S531). The maximum value is determined by the size of the internal buffer. When the size of the buffer is M + 1, the maximum value is M and the minimum value is -M. Since rlc is not the maximum value, the next byte 22 of the original data string is read again (S520). Thus, the fData and ffData values are 22 and 22, respectively, so that the state of the EQ is 1 by the comparator, and the state of the rEQ is 1 as the next step proceeds. Since the state of the previous rEQ and the state of rrEQ were 0, the state of rrEQ and rrrEQ becomes 0.

Therefore, by this state, in the state checking step, branching is to the third (S520).

By the branch, 1, which is the value of rlc, and 1a indicated by the address of the internal buffer in which the original data string is stored are stored in the memory (S540, S541). The rlc is cleared to a value of 0, and the address of the internal buffer is increased to point to the next data (22) (S542, S543). And since EQ is 1, rlc decreases to a value of -1, and the address of the internal buffer increases to point to the third data, 22 (S550). Since rlc is not the minimum value, 33 is accepted as the next byte of the original data string (S551). S510).

In the state chunk phase, fData is 33 and ffData becomes 22, so the EQ has a value of 0, so the state of rEQ is 0, the state of rrEQ and the state of rrrEQ are 1 because the state of previous rEQ is 1 and the state of previous rrEQ is 0. 1 and 0 respectively. Therefore, the first branch by the state check (S520).

The rlc value -1 and the 22 value designated by the address of the internal buffer are stored in the memory (S552). After that, rlc becomes 0 and the address increases to point to the fourth data 33 (S553), and it is determined whether the state is ⑤ as shown in the flowchart of FIG. 5 (S554). ⑤ state is as shown in the following logical formula 2.

[Logical formula 2]

⑤ (rEQ & ~ rrEQ & rrrEQ) | (rEQ & rrEQ)

According to the determination, since it does not correspond to the state ⑤, the data 1a of 1 byte is received again (S510).

In the state check step again, fData is 1a and ffData becomes 33, so the EQ has a value of 0, so the state of rEQ is 0, the state of rrEQ and the state of rrrEQ because the state of previous rEQ is 0 and the state of previous rrEQ is 1. Are 0 and 1 respectively. Therefore, the fourth branch by the state check (S520).

rlc is incremented to 1 (S530), and if it is not the maximum value M, 1 byte is accepted again (S531 and S510).

In the state chunk phase, fData is la and ffData becomes la, so the EQ has a value of 1, so the state of rEQ is 1, the state of rrEQ and the state of rrrEQ are 0 because the state of previous rEQ is 0 and the state of previous rrEQ is 0. 0 and 0 respectively. Therefore, the third branch by the state check (S520).

The value 1 of rlc and 33 indicated by the address of the internal buffer are stored in the memory (S540 and S541). The address increases to point 1a and rlc becomes 0 (S542, S543). Since the EQ is 1 (S544), rlc is reduced to -1 in the next step (S550), and since rlc is not the minimum value, the next one byte 1a is read again (S551, S510).

In the state chunk phase, fData is 1a and ffData becomes 1a, so the EQ has a value of 1, so the state of rEQ is 1, the state of rrEQ and the state of rrrEQ are 1 because the state of previous rEQ is 1 and the state of previous rrEQ is 0. 1 and 0 respectively. Therefore, the second branch by the state check (S520).

The rlc value decreases to have a value of -2, and the address increases to point to the next address 1a (S550). Since the original data strings are all output, the rlc value and the data 1a indicated by the address are finally stored in the memory (S552 to S555).

Through this process, data is output in a compressed form of 1, 1a, -1, 22, -2, and 1a.

Next, a process of restoring the compressed data strings "1, 1a, -1, 22, -2, 1a" will be described with reference to the flowchart of FIG.

As shown in Fig. 6, the first rlc value 1 and data 1a of the original data string are read (S500 and S510). First, data of 1a is written into the memory (S520), and then the rlc value is compared with 0 (S530). According to the flowchart of Fig. 6, since the rlc value is greater than 0, rlc is decreased in the next step (S560).

Since rlc is 0 (S570, S580) and all original data strings have not been transmitted (S590), the process proceeds to the start again and the next rlc -1 and data 22 are read (S500, S510). 22 is written to the memory (S520), and since rlc is less than 0, rlc is increased to 0 (S540). Since the value of the increased rlc is equal to 0 (S550), 22 is written to the memory again, and as a result, duplicate data is restored and two 22 are written (S520). Since the rlc value of the comparison is equal to 0 (S530 and S580), the process returns to the start step and reads the new rlc values -2 and 1a (S590, S500 and S510).

First, if 1a is written to memory (S520) and rlc is increased (S530, S540), rlc is -1 and is still less than 0 (S550), so 1a is written to memory again (S520) and rlc is increased to 0 ( S530 and S540 Write 1a once again (S520), and thus all of the original data strings are output, thereby restoring the operation (S530, S580, and S590).

As a result, the restored data becomes "1a, 22, 22, 33, 1a, 1a, 1a" which are data strings before compression.

As described above, the present invention incorporates a compression and recovery function in the DMA controller using the MRLE algorithm, and various compression algorithms may be used in addition to the MRLE algorithm.

As described above, according to the present invention, the built-in compression and recovery functions of the DMA controller can improve the system performance by reducing the time that the DMA controller occupies the bus when a large amount of the same data in the source memory is transferred to the target memory. It has an effect.

Claims (5)

In the direct memory access controller including a control unit for receiving a control signal and data from the central processing unit and the input and output unit to compress or restore the output data sequence, Receiving a control signal and the data from the central processing unit and the input / output device and selecting one of compression and restoration operations; A second step of sequentially reading the data of the original data sequence among the data from the central processing unit and the input / output unit by the controller and temporarily storing the data in the first buffer and the second buffer in the controller; When the compression operation is performed by the first step, A third step of compressing by sequentially checking whether the data of the first buffer and the data of the second buffer are overlapped and transmitting only the data corresponding to the number of duplicates and one data duplicated; When the restoration operation is performed by the first step, And compressing and restoring the memory by directly restoring the duplicated data by the number of duplicates by the data corresponding to the number of duplicates transmitted by the three-stage compression process. In claim 1, The third step, Comparing the data inputted to the first buffer and the second buffer one by one and outputting a case value of 1 and 0, respectively, if not equal to each other; An eleventh step of sequentially shifting the state values sequentially output by the tenth step into a first register, a second register, and a third register in the memory access controller; 12. A method of compressing and restoring a direct memory access controller comprising 12 steps of determining a number of overlaps according to state values of the first register, the second register, and the third register; In claim 1, Data corresponding to the number of overlaps of the third step, The counter in the controller is decremented every time the data strings that are sequentially introduced into the first buffer and the second buffer are duplicated. Compression and restoration method of a direct memory access controller, characterized in that the. In claim 1, In the third step, the maximum and minimum values of the data corresponding to the number of overlaps are The maximum value is M and the minimum value is -M when the size of the internal buffer is M + 1, and the minimum value is -M, which is determined according to the size of the internal buffer of the controller. How to restore. In claim 1, In the fourth step, The data corresponding to the number of duplicates transmitted is Whenever the duplicated data is inputted to the internal buffer of the controller by a repetitive operation and increases to 0, the duplicated data is finally inputted to the internal buffer and the restoration operation ends. How to compress and restore memory access controllers.