KR20000021388A - Method for forming plug of semiconductor device - Google Patents

Method for forming plug of semiconductor device Download PDF

Info

Publication number
KR20000021388A
KR20000021388A KR1019980040426A KR19980040426A KR20000021388A KR 20000021388 A KR20000021388 A KR 20000021388A KR 1019980040426 A KR1019980040426 A KR 1019980040426A KR 19980040426 A KR19980040426 A KR 19980040426A KR 20000021388 A KR20000021388 A KR 20000021388A
Authority
KR
South Korea
Prior art keywords
plug
contact hole
layer
forming
wiring layer
Prior art date
Application number
KR1019980040426A
Other languages
Korean (ko)
Other versions
KR100294973B1 (en
Inventor
류재식
Original Assignee
김영환
현대반도체 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김영환, 현대반도체 주식회사 filed Critical 김영환
Priority to KR1019980040426A priority Critical patent/KR100294973B1/en
Publication of KR20000021388A publication Critical patent/KR20000021388A/en
Application granted granted Critical
Publication of KR100294973B1 publication Critical patent/KR100294973B1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics

Abstract

PURPOSE: A method for forming a plug of a semiconductor device is provided to simplify fabrication process, to prevent the generation of particles and fabricate a highly integrated device by selectively forming the plug only in a contact hole. CONSTITUTION: An interlayer insulating layer(23) is formed on a first wiring layer(22)formed on a substrate(21). A predetermined region of the interlayer insulating layer(23) is etched, therefore a contact hole exposing a predetermined region of the first wiring layer is formed. An impurity ion buried layer is formed in the first wiring layer(22) exposed by the contact hole. A plug filling the contact hole is formed with a conductive material using the impurity ion as a seed.

Description

반도체장치의 플러그 형성방법Plug Formation Method of Semiconductor Device

본 발명은 반도체장치의 플러그 형성방법에 관한 것으로서, 특히, 각각 상이한 층에 형성되는 배선간의 연결을 위한 플러그를 접촉홀 내에만 선택적으로 형성시키므로서 공정의 단순화와 이물질 발생을 방지하고 고집적 소자에 적합하도록 한 반도체장치의 플러그 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a plug of a semiconductor device, and in particular, by selectively forming a plug for connection between wirings formed in different layers only in a contact hole, thereby simplifying the process and preventing generation of foreign substances and suitable for a highly integrated device. A method of forming a plug of a semiconductor device is provided.

도 1a 내지 도 1d는 종래 기술에 따른 반도체장치의 플러그 형성방법을 도시하는 공정도이다.1A to 1D are process diagrams illustrating a method for forming a plug of a semiconductor device according to the prior art.

도 1a를 참조하면, 층간절연층이 상측 표면에 형성된 반도체 기판(1) 위에 하부배선층(2)을 형성한 후, 기판(1) 상에 층간절연층(3)을 형성한다. 그리고, 층간절연층(3)의 소정 부분을 포토리쏘그래피 방법으로 패터닝하여 하부배선층(2)을 노출시키는 접촉홀을 형성한다. 상기에서, 기판(1)은 불순물 확산영역(도시되지 않음)이 형성된 반도체기판이거나, 또는, 하부의 배선일 수도 있다.Referring to FIG. 1A, after forming the lower wiring layer 2 on the semiconductor substrate 1 on which the interlayer insulating layer is formed, the interlayer insulating layer 3 is formed on the substrate 1. Then, a predetermined portion of the interlayer insulating layer 3 is patterned by a photolithography method to form a contact hole exposing the lower wiring layer 2. In the above description, the substrate 1 may be a semiconductor substrate having an impurity diffusion region (not shown) or a lower wiring.

도 1b를 참조하면, 층간절연층(3) 상에 접촉홀을 통해 하부배선층(2)과 접촉되도록 질화티타늄(TiN) 등을 스퍼터링 방법으로 순차적으로 증착하여 확산장벽층(4)을 형성한다.Referring to FIG. 1B, a diffusion barrier layer 4 is formed by sequentially depositing titanium nitride (TiN) or the like through a sputtering method on the interlayer insulating layer 3 so as to contact the lower wiring layer 2 through a contact hole.

도 1c를 참조하면, 확산장벽층(4) 상에 SiF4, H2 및 WF6 등의 가스를 흘리면서 화학기상증착(Chemical Vapor Deposition : 이하, CVD라 칭함) 방법으로 텅스텐(W) 등을 접촉홀을 채우도록 증착하여 플러그층(5)을 형성한다.Referring to FIG. 1C, tungsten (W) or the like is filled with a contact hole by chemical vapor deposition (CVD) while flowing gases such as SiF 4, H 2, and WF 6 on the diffusion barrier layer 4. To form a plug layer 5.

도 1d를 참조하면, 플러그층(5)을 SiF6 가스를 이용한 반응성이온식각(Reactive Ion Etching : 이하, RIE라 칭함) 방법으로 확산장벽층(4) 표면이 노출되도록 에치백(etchback)한다. 이 때, 플러그층(5)의 접촉홀 내에 잔류하는 부분은 플러그(5)가 된다.Referring to FIG. 1D, the plug layer 5 is etched back so that the surface of the diffusion barrier layer 4 is exposed by reactive ion etching (hereinafter referred to as RIE) using SiF 6 gas. At this time, the part remaining in the contact hole of the plug layer 5 becomes the plug 5.

도 1e를 참조하면, 플러그층(5) 표면을 포함하는 확산장벽층(4) 표면에 상부배선층(6)을 형성하여 층간 배선을 전기적으로 연결한다.Referring to FIG. 1E, the upper wiring layer 6 is formed on the surface of the diffusion barrier layer 4 including the surface of the plug layer 5 to electrically connect the interlayer wiring.

그러나, 상술한 플러그 형성방법은 플러그를 형성하기 위한 에치백시 플러그층을 이루는 텅스텐은 확산장벽층을 이루는 질화티타늄(TiN) 보다 식각 속도가 빠르므로 텅스텐의 손실에 의해 접촉홀 내의 플러그는 상부의 가운데 부분이 움푹파여 이 후에 형성되는 금속 배선의 평탄도 및 신뢰성이 저하되고, 이물질이 다량 발생하며, 소자가 고집적화됨에 따라 종횡비가 커지므로 확산방지층의 질화티타늄막의 증착이 곤란한 문제점이 있다.However, in the plug forming method described above, tungsten forming the plug layer for etching the plug has a faster etching rate than titanium nitride (TiN) forming the diffusion barrier layer. Since the flatness and reliability of the metal wirings formed after the recessed portions are lowered, a large amount of foreign matter is generated, and the aspect ratio increases as the device is highly integrated, it is difficult to deposit the titanium nitride film of the diffusion barrier layer.

따라서, 본 발명의 목적은 각각 상이한 층에 형성되는 배선간의 연결을 위한 플러그를 접촉홀 내에만 선택적으로 형성시키므로서 공정의 단순화와 이물질 발생을 방지하고 고집적 소자에 적합하도록 한 반도체장치의 플러그 형성 방법을 제공함에 있다.Accordingly, an object of the present invention is to selectively form a plug for interconnection between wires formed in different layers only in a contact hole, thereby simplifying the process, preventing foreign matters from occurring, and making the plug suitable for a highly integrated device. In providing.

상기 목적을 달성하기 위한 본 발명에 따른 반도체장치의 플러그 형성방법은 기판 표면에 형성된 제 1 배선층 위에 층간절연막을 형성하는 단계와, 층간절연막의 소정 부위를 제거하여 제 1 배선층의 소정 부위를 노출시키는 콘택홀을 형성하는 단계와, 콘택홀에 의하여 노출된 제 1 배선층에 불순물이온 매몰층을 형성하는 단계와, 불순물이온을 성장 씨드로 이용하는 도전물질로 콘택홀을 매립하는 플러그를 형성하는 단계를 포함하여 이루어진다.The plug forming method of the semiconductor device according to the present invention for achieving the above object is to form an interlayer insulating film on the first wiring layer formed on the substrate surface, and to remove a predetermined portion of the interlayer insulating film to expose a predetermined portion of the first wiring layer. Forming a contact hole, forming a buried impurity ion buried layer in the first wiring layer exposed by the contact hole, and forming a plug to fill the contact hole with a conductive material using impurity ions as a growth seed; It is done by

도 1a 내지 도 1e는 종래 기술에 따른 반도체장치의 플러그 형성방법을 도시하는 공정도1A to 1E are process diagrams illustrating a method for forming a plug of a semiconductor device according to the prior art.

도 2a 내지 도 2d는 본 발명에 따른 반도체장치의 플러그 형성 방법을 도시하는 공정도2A to 2D are process charts showing a plug forming method of a semiconductor device according to the present invention.

이하, 첨부한 도면을 참조하여 본 발명을 상세히 설명한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

도 2a 내지 도 2d는 본 발명에 따른 반도체장치의 플러그 형성방법을 도시하는 공정도이다.2A to 2D are process diagrams illustrating a method for forming a plug of a semiconductor device according to the present invention.

도 2a를 참조하면, 층간절연층이 상측 표면에 형성된 반도체 기판(21) 위에 하부배선층(22)을 형성한 후, 기판(21) 상에 층간절연층(23)을 형성한다. 그리고, 층간절연층(23)의 소정 부분을 포토리쏘그래피 방법으로 패터닝하여 하부배선층(22)을 노출시키는 접촉홀을 형성한다. 상기에서, 기판(21)은 불순물 확산영역(도시되지 않음)이 형성된 반도체기판이거나, 또는, 하부의 배선일 수도 있다.Referring to FIG. 2A, after forming the lower wiring layer 22 on the semiconductor substrate 21 on which the interlayer insulating layer is formed, the interlayer insulating layer 23 is formed on the substrate 21. Then, a predetermined portion of the interlayer insulating layer 23 is patterned by photolithography to form a contact hole exposing the lower wiring layer 22. In the above description, the substrate 21 may be a semiconductor substrate having an impurity diffusion region (not shown) or a lower wiring.

도 2b를 참조하면, 노출된 하부배선층(22)에 실리콘 이온 매몰층을 형성하기 위하여 기판의 전면에 실리콘 이온주입을 실시하여 매몰층(24)을 접촉홀 하부에 위치한 하부배선층(22)에 형성한다.Referring to FIG. 2B, in order to form the silicon ion buried layer on the exposed lower wiring layer 22, silicon ion implantation is performed on the entire surface of the substrate to form the buried layer 24 in the lower wiring layer 22 positioned below the contact hole. do.

도 2c를 참조하면, 노출된 하부배선층(22) 상에 SiF4, H2 및 WF6 등의 가스를 흘리면서 화학기상증착(Chemical Vapor Deposition : 이하, CVD라 칭함) 방법으로 텅스텐(W) 등을 접촉홀을 채우도록 증착하여 플러그층(25)을 형성한다. 이때, 플러그층(25)은 매몰층(24)에 있는 실리콘을 선택적 성장 씨드(seed)로 이용하여 텅스텐이 성장하도록 하므로서 형성되며, 이러한 선택적 성장 때문에 텅스텐층이 콘택홀에만 형성되므로 추후 에치백공정이 필요하지 않다.Referring to FIG. 2C, tungsten (W) or the like may be contacted by chemical vapor deposition (CVD) while flowing gases such as SiF 4, H 2, and WF 6 on the exposed lower wiring layer 22. The plug layer 25 is formed by depositing to fill. At this time, the plug layer 25 is formed by using tungsten to grow using the silicon in the buried layer 24 as a selective growth seed (seed). This is not necessary.

도 2d를 참조하면, 플러그층(25) 표면을 포함하는 층간절연층(23) 표면에 상부배선층(26)을 형성하여 층간 배선을 전기적으로 연결한다.Referring to FIG. 2D, the upper wiring layer 26 is formed on the surface of the interlayer insulating layer 23 including the surface of the plug layer 25 to electrically connect the interlayer wiring.

따라서, 본 발명은 각각 상이한 층에 형성되는 배선간의 연결을 위한 플러그를 접촉홀 내에만 실리콘을 성장 씨드로 이용하여 선택적으로 형성시키므로서 공정의 단순화와 이물질 발생을 방지하고 고집적 소자에 적합하도록 한 장점이 있다.Accordingly, the present invention selectively forms a plug for interconnection between wires formed in different layers by using silicon as a growth seed only in a contact hole, thereby simplifying the process and preventing foreign substances, and making it suitable for highly integrated devices. There is this.

Claims (6)

기판 표면에 형성된 제 1 배선층 위에 층간절연막을 형성하는 단계와,Forming an interlayer insulating film on the first wiring layer formed on the substrate surface; 상기 층간절연막의 소정 부위를 제거하여 상기 제 1 배선층의 소정 부위를 노출시키는 콘택홀을 형성하는 단계와,Removing a predetermined portion of the interlayer insulating layer to form a contact hole exposing a predetermined portion of the first wiring layer; 상기 콘택홀에 의하여 노출된 상기 제 1 배선층에 불순물이온 매몰층을 형성하는 단계와,Forming an impurity ion buried layer in the first wiring layer exposed by the contact hole; 상기 불순물이온을 성장 씨드로 이용하는 도전물질로 상기 콘택홀을 매립하는 플러그를 형성하는 단계로 이루어진 반도체장치의 플러그 형성방법.And forming a plug to fill the contact hole with a conductive material using the impurity ions as a growth seed. 청구항 1에 있어서, 상기 제 1 배선층은 텅스텐으로 형성하는 것이 특징인 반도체장치의 플러그 형성방법.The method according to claim 1, wherein the first wiring layer is formed of tungsten. 청구항 1에 있어서, 상기 불순물이온은 실리콘인 것이 특징인 반도체장치의 플러그 형성방법.The method according to claim 1, wherein the impurity ion is silicon. 청구항 1에 있어서, 상기 플러그는 상기 접촉홀에 SiF4, H2 및 WF6 등의 가스를 흘리면서 화학기상증착방법으로 텅스텐 등을 접촉홀을 채우도록 증착하여 형성하는 것이 특징인 반도체장치의 플러그 형성방법.The method of claim 1, wherein the plug is formed by depositing tungsten or the like to fill the contact hole by chemical vapor deposition while flowing gases such as SiF 4, H 2, and WF 6 in the contact hole. 청구항 1에 있어서, 상기 플러그 형성단계 이후,The method according to claim 1, After the plug forming step, 상기 플러그 표면을 포함하는 상기 층간절연막 위에 제 2 배선층을 형성하는 단계를 더 포함하여 이루어진 것이 특징인 반도체장치의 플러그 형성방법.And forming a second wiring layer on the interlayer insulating film including the plug surface. 청구항 1에 있어서, 상기 불순물이온 매몰층은 실리콘 이온주입으로 형성하는 것이 특징인 반도체장치의 플러그 형성방법.The method of claim 1, wherein the impurity ion buried layer is formed by implanting silicon ions.
KR1019980040426A 1998-09-29 1998-09-29 Plug Formation Method of Semiconductor Device KR100294973B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019980040426A KR100294973B1 (en) 1998-09-29 1998-09-29 Plug Formation Method of Semiconductor Device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019980040426A KR100294973B1 (en) 1998-09-29 1998-09-29 Plug Formation Method of Semiconductor Device

Publications (2)

Publication Number Publication Date
KR20000021388A true KR20000021388A (en) 2000-04-25
KR100294973B1 KR100294973B1 (en) 2001-10-26

Family

ID=19552303

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019980040426A KR100294973B1 (en) 1998-09-29 1998-09-29 Plug Formation Method of Semiconductor Device

Country Status (1)

Country Link
KR (1) KR100294973B1 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20000066124A (en) * 1999-04-13 2000-11-15 김영환 Manufacturing method for plug in semiconductor device
KR20220026559A (en) * 2019-09-20 2022-03-04 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 Bottom-up formation of contact plugs

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0645210A (en) * 1992-07-27 1994-02-18 Nec Corp Method of forming multi-layer wiring

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20000066124A (en) * 1999-04-13 2000-11-15 김영환 Manufacturing method for plug in semiconductor device
KR20220026559A (en) * 2019-09-20 2022-03-04 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 Bottom-up formation of contact plugs
US11469139B2 (en) 2019-09-20 2022-10-11 Taiwan Semiconductor Manufacturing Company, Ltd. Bottom-up formation of contact plugs

Also Published As

Publication number Publication date
KR100294973B1 (en) 2001-10-26

Similar Documents

Publication Publication Date Title
KR100215846B1 (en) Method for forming interconnector of semiconductor device
US6090700A (en) Metallization method for forming interconnects in an integrated circuit
KR100715389B1 (en) Boron-doped titanium nitride layer for high aspect ratio semiconductor devices
KR100283109B1 (en) Metal wiring formation method of semiconductor device
US6083832A (en) Method of manufacturing semiconductor device
US5607878A (en) Contact plug forming method
JP3027946B2 (en) Semiconductor device and manufacturing method thereof
KR100294973B1 (en) Plug Formation Method of Semiconductor Device
KR100221656B1 (en) Process for forming interconnector
KR100196228B1 (en) Interconnection manufacturing method of semiconductor integrated circuit
KR100186509B1 (en) Method of forming metal interconnector in semiconductor device
GB2245759A (en) Method of forming a tungsten interconnection pattern on a semiconductor device
KR20020058430A (en) Method for fabricating a wire in semiconductor device
JP2729769B2 (en) Method for manufacturing semiconductor device
KR100339026B1 (en) Method for forming metal wiring in semiconductor device
JPH06268077A (en) Manufacture of semiconductor device
KR100260817B1 (en) Method for forming plug of semiconductor device
KR100396684B1 (en) Method for forming metal interconnection of semiconductor device
JPH05217940A (en) Manufacture of semiconductor device
KR100192184B1 (en) Method of manufacturing contact plug
KR100236071B1 (en) Interconnector of semiconductor device and method of forming the same
JPH0499317A (en) Manufacture of semiconductor device
KR0168162B1 (en) Method of forming metal wire of semiconductor device
JPH07153843A (en) Contact preparation of semiconductor device
KR20000040722A (en) Method for forming plug of semiconductor device

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20090406

Year of fee payment: 9

LAPS Lapse due to unpaid annual fee