JP2729769B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of simultaneously filling contact holes having different depths by using selective tungsten in the manufacture of a semiconductor device.

[0002]

2. Description of the Related Art As semiconductor devices become more highly integrated, it becomes necessary to form a three-dimensional structure of individual elements formed on an active region, thereby increasing the height of the elements from the surface of a substrate.
As the height difference between the elements further increases, planarization using an insulating layer becomes important for interconnection between the elements.

[0003] However, such planarization causes a difference in the depth of each contact hole for wiring to individual elements having different heights from the substrate. For example, transistor gate strapping
Such differences include the depth difference between the contact and the source and drain contact, and the depth difference between the buried bit line contact and the source and drain contact.

[0004] Such a difference in the depth of the contact hole makes non-uniform filling of the contact hole by selective chemical vapor deposition of a metal material. That is, as shown in FIG. 1, a predetermined conductive wire formed on the substrate 1 via the planarized insulating layer 4, for example, a contact hole for exposing the surface of the gate 2 and the impurity diffusion region 3 of the transistor is formed. Then, a difference occurs in the depth of the contact holes due to the difference in height between the gate 2 and the impurity diffusion region 3 from the surface of the substrate. In the case of burying at the same time, burying is not completely performed in a deep contact hole, but is buried excessively in a thin contact hole.

In general, when a metal is selectively deposited to fill a contact hole in an element having various contact depths, the maximum thickness of the deposited metal is limited by the depth of the thinnest contact hole. (Ref.
J. Saia, et al. , Tungsten an
d other refractory metals
for VLSI application III,
edited byV. L. Wells (MRS, Pi
ttsburgh. PA) pp. 349, 198
7 ”). Therefore, even if the thinnest contact hole is completely buried, the deep contact hole is not completely buried, which makes the subsequent metal wiring process difficult. For this reason, as a method of completely filling contact holes having different depths existing in one element at the same time, a method using chemical vapor deposition polycrystalline silicon (“KK Choi, ct a”).
l. Proc. VLSI Multilevel I
interconnection Conf. Pp. 2
86, 1992]).

In the above method, as shown in FIG. 2, contact holes having different depths are completely filled simultaneously using chemical vapor deposition polycrystalline silicon. This method is illustrated in FIG.
As shown in FIG. 2A, after a predetermined conductive line formed on the substrate, for example, a contact hole exposing the surface of the bit line 6 and the impurity diffusion region 3 is formed via the planarized insulating layer 4 (this At this time, as shown in the figure, the difference in height between the bit line 6 and the impurity diffusion region 3 from the surface of the substrate causes
A difference occurs in the depth of the contact hole), and polycrystalline silicon 7a is deposited over the entire surface of the insulating layer 4 including the contact hole.

Next, as shown in FIG. 2B, anisotropic dry etching is performed to selectively deposit tungsten 5 while leaving the polycrystalline silicon layer 7b only on the side walls of the contact holes. At the same time, tungsten grows on the side surface and the contact hole is filled regardless of the depth of the contact hole.

[0008]

However, in the above method, since polycrystalline silicon must be deposited and subjected to anisotropic dry etching, the process is complicated, and the bottom surface of the contact hole by etching is complicated. There is a problem that the exposed lower conductive layer is damaged.

An object of the present invention is to solve such a problem, and an object of the present invention is to provide a method capable of simultaneously completely filling contact holes having different depths in a semiconductor device.

[0010]

According to the present invention, there is provided a method of manufacturing a semiconductor device, comprising: forming a first insulating layer on a semiconductor substrate having a first conductive line formed thereon; Etching a first insulating layer corresponding to a first region of one conductive line to form a first contact hole; forming a TiN layer on the conductive layer; Patterning a conductive line pattern, forming a second insulating layer on the second conductive line and the first insulating layer to planarize the surface of the substrate, and forming a second region on the first conductive line. Forming a second contact hole and a third contact hole by simultaneously etching the corresponding first insulating layer, the second insulating layer, and the second insulating layer of the second conductive line; The second contact hole and the second A step of filling the contact holes simultaneously completely consist.

The tungsten has a WF ₆ chemistry (ce)
and WF ₆ chemistry involves H ₂ reduction and SiH ₄ reduction. The second conductive line is a gate of a transistor or a buried bit line, and the first conductive line is
Conductive lines are the source and drain regions or wiring strapping portions of the transistor. In addition, the source and drain regions may be formed of impurity doping regions of silicon single crystal, or may be regions in which metal silicide (self-aligned silicide) serving as a barrier is formed.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings. Generally, when tungsten is deposited on a TiN layer, WF
Chemical action of ₆ -H ₂ (chemistry) about 7 under
It is reported that there is a deposition delay time of about 10 minutes (see the reference "VVS Rana, et. Al., Wor").
kshopon Tungsten and the other
r refractory metals for V
LSI Appl. II, pp. 187, 1987],
[E. K. Broadbent, J.M. Vac. Sci.
Technol. , B5 (6), pp. 1661, 19
87 ”).

Such an initial deposition delay is not observed from silicon, other metals, metal silicides, and the like, and is known to be caused by a very low reactivity of TiN to WF ₆ gas. . The present invention relates to a technique for simultaneously filling at least two types of contact holes having different depths by utilizing such characteristics of tungsten.

According to the present invention, a TiN layer is formed in advance on the surface of a conductive line on which a relatively thin contact hole is formed, and then tungsten is selectively deposited in contact holes having different depths. TiN described above
The contact holes having different depths are simultaneously buried depending on the characteristics of the initial deposition delay of tungsten on the layer.

In particular, since the depth of the contact hole differs according to the type or grade of the device to be manufactured, the deposition delay time and the tungsten deposition in the TiN layer by the tungsten deposition method are taken into account in consideration of the difference in the contact hole depth. By combining speeds, contact holes of different depths are completely filled simultaneously.

Referring to FIG. 3, a method of filling a contact hole by selective deposition of tungsten according to an embodiment of the present invention will be described as follows. First, as shown in FIG. 3A, a source and a drain region (first conductive line (or lower conductive line)) of a transistor including an impurity diffusion region 3 are formed on a semiconductor substrate 1 formed in a predetermined region. After forming the first insulating layer 4A, the first insulating layer 4A at a position corresponding to the first region of the first conductive line is etched to expose the impurity diffusion region 3 and form a first contact hole. Next, a second conductive line, for example, a bit line (or a transistor gate) 8 connected to the impurity diffusion region via the first contact hole is formed. After depositing any one of polycrystalline silicon, metal silicide, and polycide, reactive sputtering, physical vapor deposition (PVD), or chemical vapor deposition (CVD) such as LPCVD or MOCVD is performed thereon. The TiN layer 10 has a thickness of about 3
Vapor deposition is performed at about 0 to 300 nm. At this time, the TiN layer can be replaced with TiW, a tungsten nitride film, a metal silicide, or the like.

Next, as shown in FIG.
0 and bit line 8 are patterned into a desired bit line pattern by a photo-etching process.

Thereafter, as shown in FIG. 3C, after a second insulating layer 4B is formed over the entire surface of the substrate and planarized, the first insulating layer 4A corresponding to the second region of the first conductive line is formed. The second contact layer 9A and the third contact hole 9B exposing the TiN layer 10 and the impurity diffusion region 3 above the bit line 8 by simultaneously etching the second insulating layer 4B and the second insulating layer 4B of the second conductive line are formed. Form. At this time, the second contact hole 9A on the TiN layer 10 above the bit line is formed shallower than the third contact hole 9B above the impurity diffusion region 3, as shown.

Next, as shown in FIG. 3D, the surface of the conductive line exposed by forming the contact hole, that is,
On the surfaces of the TiN layer 10 and the impurity diffusion region 3, for example, W
Tungsten 5 is deposited by a selective chemical vapor deposition method using F ₆ chemistry, and second tungsten 5 having different depths is deposited.
The contact hole 9A and the third contact hole 9B are buried at the same time. The contact holes may be filled with a metal material such as Al or Cu instead of the tungsten.

Generally, the selective deposition of tungsten at a silicon contact such as the impurity diffusion region 3 is performed by:
In order to maintain the selectivity between the insulating layer and the conductive wires, about 300
C. at a deposition temperature of ± 30 ° C. to minimize erosion of tungsten deposition on silicon contacts.
The vapor deposition is performed by using the chemical action of WF ₆ -SiH ₄ rather than the chemical action of F ₆ -H ₂ .

When utilizing the WF ₆ -SiH ₄ chemistry, the tungsten deposition delay time on the TiN layer is about 1 to 3.5 minutes (this is due to the deposition temperature, SiH ₄ / WF ₆ fraction and TiN (Depending on the surface condition and the like).
For example, as shown in FIG. 4A, the difference between the depths of the two contact holes is set to 0.75 μm, the depth of the contact hole on the n ⁺ impurity diffusion region 3 is set to 1.75 μm,
The deposition delay time is 3 minutes, and the tungsten deposition rate is 1
At a rate of 0.25 μm per minute, two contact holes of different depths are completely buried after tungsten deposition for about 7 minutes.

As another example, as shown in FIG. 4B, a silicide (self-align) is previously formed in a silicon contact.
ed silicide) is formed,
First, using WF ₆ -H ₂ , a deep contact hole is buried until the same height as a thin contact hole.
Using WF ₆ -SiH ₄ , two contact holes having different depths are completely buried by simultaneously depositing tungsten at the same deposition rate. This utilizes the property that tungsten is hardly deposited on TiN in the range of tungsten deposition temperature for selective deposition. When tungsten is deposited using WF ₆ -H ₂ , a TiN layer is formed. Since tungsten is not deposited on the upper side and tungsten is deposited only on the silicide layer 11, first, the contact hole on the deep silicide layer 11 is made to have the same depth as the contact hole on the thin TiN layer 10. After the burying, two contact holes are simultaneously buried using WF ₆ -SiH ₄ .

In this case, since the activation is sufficiently performed while the TiN surface is exposed to the gaseous mixture of WF ₆ -H ₂ , the subsequent deposition of tungsten using WF ₆ -SiH ₄ is immediately performed without time delay. You.

[0024]

As described above, the present invention does not require the formation of the side wall as in the above-described conventional method of burying the contact hole using the polycrystalline silicon side wall. The tungsten is deposited while being maintained. Therefore, the contact hole can be easily buried. Since the etching process for forming the side wall is not required, the surface of the underlying layer under the contact is not damaged, and thus the characteristics of the device can be prevented from deteriorating and the insulating layer can be prevented from being damaged. Selectivity does not decrease.

It is to be noted that the contact holes having different depths can be buried at the same time without any additional step other than the step of simply depositing TiN in advance on the conductive line on which the contact is to be formed. Has advantages.

[Brief description of the drawings]

FIG. 1 shows a method of embedding contact holes having different depths in a semiconductor device according to a conventional technique.

FIG. 2 is a process sequence diagram showing a method of burying contact holes having different depths in a semiconductor device according to the related art using sidewalls of polycrystalline silicon.

FIG. 3 is a process sequence diagram showing a method of embedding contact holes having different depths in a semiconductor device according to the present invention.

FIG. 4 shows a method of embedding contact holes having different depths in a semiconductor device according to an embodiment of the present invention.

[Explanation of symbols]

Reference numeral 1 denotes a semiconductor substrate, 3 denotes a first conductive line (impurity diffusion region),
4A: first insulating layer, 4B: second insulating layer, 5: tungsten, 8: second conductive line (bit line), 10: TiN
Layer, 11: silicide layer.

Claims (5)

(57) [Claims] A step of forming a first insulating layer on the semiconductor substrate having the first conductive line formed thereon, and etching the first insulating layer at a position corresponding to a first region of the first conductive line. Forming a contact hole; forming a conductive layer on the first insulating layer having the contact hole formed therein; forming a TiN layer on the conductive layer; and forming the TiN layer and the conductive layer. Patterning the second conductive line into a pattern, forming a second insulating layer on the second conductive line and the first insulating layer to planarize the surface of the substrate, Forming a second contact hole and a third contact hole by simultaneously etching a portion of the first insulating layer, the second insulating layer, and the second conductive line of the second insulating layer corresponding to the two regions; Selective deposition and each A step of embedding the second contact hole and the third contact hole at the same time, when the silicide on the surface of the first conductive line exposed in the second contact hole is formed, to the height of the second conductive line H After filling the second contact hole on the first conductive line using WF ₆ chemistry using ₂ reduction, the first conductive line is filled using WF ₆ chemistry using SiH ₄ reduction. Filling the second contact hole above and the third contact hole above the second conductive line. Wherein said TiN layer, a method of manufacturing a semiconductor device according to claim 1, wherein the formed by reactive <br/> deposited to a thickness 30~300nm by sputtering method or CVD method. 3. The method according to claim 1, wherein the second conductive line is a gate of a transistor or a buried bit line. 4. The method according to claim 1, wherein the first conductive line is a source / drain region of a transistor or a wiring strapping portion. 5. The method according to claim 1, wherein the depth of the second contact hole is greater than the depth of the third contact hole.
The manufacturing method of the semiconductor device described in the above.