KR20000020372A - Method for manufacturing semiconductor - Google Patents
Method for manufacturing semiconductor Download PDFInfo
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- KR20000020372A KR20000020372A KR1019980038972A KR19980038972A KR20000020372A KR 20000020372 A KR20000020372 A KR 20000020372A KR 1019980038972 A KR1019980038972 A KR 1019980038972A KR 19980038972 A KR19980038972 A KR 19980038972A KR 20000020372 A KR20000020372 A KR 20000020372A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 43
- 238000000034 method Methods 0.000 title claims abstract description 28
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 15
- 239000012535 impurity Substances 0.000 claims abstract description 43
- 239000010410 layer Substances 0.000 claims description 106
- 230000002093 peripheral effect Effects 0.000 claims description 28
- 239000011229 interlayer Substances 0.000 claims description 27
- 239000000758 substrate Substances 0.000 claims description 27
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 13
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 13
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 13
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 13
- 238000005530 etching Methods 0.000 claims description 12
- 239000000463 material Substances 0.000 claims description 6
- 239000011810 insulating material Substances 0.000 claims description 5
- 238000000059 patterning Methods 0.000 claims description 5
- 230000000694 effects Effects 0.000 abstract description 6
- 238000009792 diffusion process Methods 0.000 abstract description 2
- 238000009413 insulation Methods 0.000 abstract 1
- 238000000151 deposition Methods 0.000 description 10
- 238000000206 photolithography Methods 0.000 description 7
- 238000005229 chemical vapour deposition Methods 0.000 description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 238000001020 plasma etching Methods 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Semiconductor Memories (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
본 발명은 반도체장치의 반도체장치의 제조방법에 관한 것으로서, 특히, 셀영역과 주변회로영역에 비트 라인을 형성하기 위한 접촉홀을 동시에 형성할 수 있는 반도체장치의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device of a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device capable of simultaneously forming contact holes for forming bit lines in a cell region and a peripheral circuit region.
도 1a 내지 도 1f는 종래 기술에 따른 반도체장치의 제조방법을 도시하는 공정도이다.1A to 1F are process drawings showing a method of manufacturing a semiconductor device according to the prior art.
도 1a를 참조하면, 셀영역(C1) 및 주변회로영역(P1)을 갖는 P형의 반도체기판(11)의 소정 부분에 STI(Shallow Trench Isolation) 또는 LOCOS(Local Oxidation of Silicon) 등의 방법에 의해 소자의 활성영역을 한정하는 필드산화막(13)을 형성한다. 상기에서 반도체기판(11) 상의 필드산화막(13)이 형성되지 않은 부분은 활성영역이 된다.Referring to FIG. 1A, a predetermined portion of a P-type semiconductor substrate 11 having a cell region C1 and a peripheral circuit region P1 may be used in a method such as shallow trench isolation (STI) or local oxide of silicon (LOCOS). As a result, a field oxide film 13 defining an active region of the device is formed. The portion where the field oxide film 13 is not formed on the semiconductor substrate 11 becomes an active region.
반도체기판(11) 상의 활성영역에 열산화 방법에 의해 게이트산화막(15)을 형성한다. 그리고, 필드산화막(13) 및 게이트산화막(15) 상에 불순물이 도핑된 다결정실리콘을 증착하여 게이트층(17)을 형성하고, 이 게이트층(17) 상에 질화실리콘 또는 산화실리콘을 증착하여 캡층(19)을 형성한다. 상기에서 게이트층(17) 및 캡층(19)은 화학기상증착(Chemical Vapor Deposition : 이하, CVD라 칭함) 방법에 의해 형성된다.The gate oxide film 15 is formed in the active region on the semiconductor substrate 11 by a thermal oxidation method. The gate layer 17 is formed by depositing polycrystalline silicon doped with impurities on the field oxide film 13 and the gate oxide film 15, and by depositing silicon nitride or silicon oxide on the gate layer 17, a cap layer is formed. (19) is formed. In the above, the gate layer 17 and the cap layer 19 are formed by a chemical vapor deposition (hereinafter, referred to as CVD) method.
도 1b를 참조하면, 캡층(19), 게이트층(17) 및 게이트산화막(15)을 반도체기판(11)이 노출되도록 포토리쏘그래피 방법으로 패터닝한다. 이 때, 게이트층(17)의 제거되지 않고 잔류하는 부분은 게이트(18)가 된다.Referring to FIG. 1B, the cap layer 19, the gate layer 17, and the gate oxide film 15 are patterned by a photolithography method so that the semiconductor substrate 11 is exposed. At this time, the remaining portion of the gate layer 17 without being removed becomes the gate 18.
캡층(19)을 마스크로 사용하여 반도체기판(11)의 노출된 부분에 N형 불순물을 저농도로 이온 주입하여 제 1 불순물영역(21)을 형성한다. 상기에서 제 1 불순물영역(21)은 셀영역(C1)에서 트랜지스터의 소오스 및 드레인영역으로 이용되며 주변회로영역(P1)에서 구동트랜지스터의 LDD(Lightly Doped Drain)영역으로 이용된다.The first impurity region 21 is formed by ion implanting N-type impurities at low concentration into the exposed portion of the semiconductor substrate 11 using the cap layer 19 as a mask. The first impurity region 21 is used as a source and a drain region of the transistor in the cell region C1 and is used as a lightly doped drain (LDD) region of the driving transistor in the peripheral circuit region P1.
도 1c를 참조하면, 반도체기판(11) 상에 질화실리콘 또는 산화실리콘을 CVD 방법으로 증착한 후 에치백하여 게이트(18) 및 캡층(19)의 측면에 측벽을 형성한다.Referring to FIG. 1C, silicon nitride or silicon oxide is deposited on the semiconductor substrate 11 by CVD and then etched back to form sidewalls on the side surfaces of the gate 18 and the cap layer 19.
반도체기판(11) 상에 감광막(25)을 도포한 후 셀영역(C1) 상에만 잔류되도록 패터닝하여 주변회로영역(P1)을 노출시킨다. 그리고, 감광막(25) 및 캡층(19)을 마스크로 사용하여 N형의 불순물을 고농도로 이온주입하여 제 2 불순물영역(27)을 형성한다. 상기에서 제 2 불순물영역(27)은 반도체기판(11)의 주변회로영역(P1)에만 제 1 불순물영역(21)과 중첩되게 형성되는 것으로 구동트랜지스터의 소오스 및 드레인영역으로 이용된다.The photosensitive film 25 is coated on the semiconductor substrate 11 and then patterned to remain only on the cell region C1 to expose the peripheral circuit region P1. Then, using the photosensitive film 25 and the cap layer 19 as a mask, ion implantation of N-type impurities at high concentration is performed to form the second impurity region 27. The second impurity region 27 is formed to overlap the first impurity region 21 only in the peripheral circuit region P1 of the semiconductor substrate 11 and is used as a source and drain region of the driving transistor.
도 1d를 참조하면, 감광막(25)을 제거한다. 그리고, 상술한 구조의 전 표면에 게이트(18) 및 캡층(19)을 덮는 제 1 층간절연층(29)을 형성한다. 상기에서 제 1 층간절연층(29)은 캡층(19) 및 측벽(23)과 식각선택비가 다른 산화실리콘 또는 질화실리콘을 CVD 방법으로 증착하므로써 형성된다.Referring to FIG. 1D, the photosensitive film 25 is removed. Then, the first interlayer insulating layer 29 covering the gate 18 and the cap layer 19 is formed on the entire surface of the above-described structure. The first interlayer insulating layer 29 is formed by depositing silicon oxide or silicon nitride having an etch selectivity different from that of the cap layer 19 and the sidewalls 23 by the CVD method.
셀영역(C1) 내의 제 1 층간절연층(29)을 포토리쏘그래피 방법으로 패터닝하여 제 1 불순물영역(21)을 노출시키는 제 1 접촉홀(31)을 형성한다. 상기에서 제 1 접촉홀(31)은 제 1 불순물영역(21) 중 인접하는 트랜지스터들이 공유하지 않는 영역을 노출시킨다. 이 때, 제 1 층간절연층(29)이 캡층(19) 및 측벽(23)과 식각선택비가 서로 다르므로 제 1 접촉홀(31)은 자기 정렬되게 형성된다.The first interlayer insulating layer 29 in the cell region C1 is patterned by photolithography to form a first contact hole 31 exposing the first impurity region 21. The first contact hole 31 exposes an area of the first impurity region 21 that is not shared by adjacent transistors. In this case, since the etch selectivity of the first interlayer insulating layer 29 and the cap layer 19 and the sidewall 23 are different from each other, the first contact hole 31 is formed to be self-aligned.
제 1 접촉홀(31) 내에 제 1 불순물영역(21)과 접촉되어 전기적으로 연결되는 플러그(33)를 형성한다. 상기에서 플러그(33)는 금속 등의 도전성 물질을 제 1 층간절연층(29) 상에 제 1 접촉홀(31)을 채우도록 증착한 후 제 1 접촉홀(31) 내부에만 잔류되게 에치백하므로써 형성된다. 플러그(33)는 제 1 불순물영역(21)을 이후에 형성될 캐패시터의 스토리지전극과 전기적으로 연결시킨다.A plug 33 is formed in the first contact hole 31 in contact with the first impurity region 21 to be electrically connected to the first impurity region 21. The plug 33 is formed by depositing a conductive material such as a metal to fill the first contact hole 31 on the first interlayer insulating layer 29 and then etching back so as to remain only inside the first contact hole 31. Is formed. The plug 33 electrically connects the first impurity region 21 to the storage electrode of the capacitor to be formed later.
도 1e를 참조하면, 제 1 층간절연층(29) 상에 플러그(33)를 덮는 제 2 층간절연층(35)을 형성한다. 상기에서 제 2 층간절연층(35)도 캡층(19) 및 측벽(23)과 식각선택비가 다른 산화실리콘 또는 질화실리콘을 CVD 방법으로 증착하므로써 형성된다.Referring to FIG. 1E, a second interlayer insulating layer 35 covering the plug 33 is formed on the first interlayer insulating layer 29. The second interlayer insulating layer 35 is also formed by depositing silicon oxide or silicon nitride having an etch selectivity different from that of the cap layer 19 and the sidewalls 23 by the CVD method.
셀영역(C1) 내의 제 1 및 제 2 층간절연층(29)(35)을 포토리쏘그래피 방법으로 패터닝하여 제 1 불순물영역(21) 중 인접하는 트랜지스터들이 공유하는 영역, 즉, 제 1 접촉홀(31)이 형성되지 않은 영역을 노출시키는 제 2 접촉홀(37)을 형성한다. 이 때에도, 제 1 층간절연층(29)이 캡층(19) 및 측벽(23)과 식각선택비가 서로 다르므로 제 2 접촉홀(37)은 자기 정렬되게 형성된다.The first and second interlayer dielectric layers 29 and 35 in the cell region C1 are patterned by a photolithography method so that adjacent transistors among the first impurity regions 21 are shared, that is, the first contact holes. A second contact hole 37 exposing a region where no 31 is formed is formed. Also in this case, since the etch selectivity is different from that of the cap layer 19 and the sidewall 23, the second contact hole 37 is formed to be self-aligned.
도 1f를 참조하면, 주변회로영역(P1)의 소정 게이트(18)가 노출되도록 제 1 및 제 2 층간절연층(29)(35)과 캡층(19)을 패터닝하여 제 3 접촉홀(39)을 형성한다. 상기에서 제 3 접촉홀(39)은 제 2 접촉홀(37)이 노출되지 않도록 덮는 마스크를 사용한 포토리쏘그래피 방법으로 형성한다. 상기에서 제 2 및 제 3 접촉홀(37)(39)를 순서를 바꾸어 형성할 수도 있다. 즉, 주변회로영역(P1)에 게이트(18)를 노출시키는 제 3 접촉홀(39)을 먼저 형성한 후 셀영역(C1)에 제 2 접촉홀(37)을 형성할 수도 있다.Referring to FIG. 1F, the first and second interlayer insulating layers 29 and 35 and the cap layer 19 are patterned so that the predetermined gate 18 of the peripheral circuit region P1 is exposed to form a third contact hole 39. To form. In the above, the third contact hole 39 is formed by a photolithography method using a mask covering the second contact hole 37 so as not to be exposed. The second and third contact holes 37 and 39 may be formed in a reverse order. That is, the third contact hole 39 exposing the gate 18 may be formed first in the peripheral circuit region P1, and then the second contact hole 37 may be formed in the cell region C1.
그리고, 제 2 층간절연층(35) 상에 셀영역(C1)에서 제 2 접촉홀(37)을 통해 제 1 불순물영역(21)과 접촉되며, 주변회로영역(P1)에서 제 3 접촉홀(39)을 통해 게이트(18)와 접촉되어 전기적으로 연결되는 비트라인(41)(43)을 형성한다.The first impurity region 21 is contacted on the second interlayer insulating layer 35 through the second contact hole 37 in the cell region C1, and the third contact hole is formed in the peripheral circuit region P1. 39 form bit lines 41 and 43 that are in electrical contact with gate 18.
그러나, 상술한 종래 기술에 따른 반도체장치의 제조방법은 주변회로영역 내의 구동트랜지스터는 저농도영역을 형성하고 고농도영역을 형성할 때 저농도영역의 불순물이 확산되어 채널의 길이가 짧아져 단채널효과(short channel effect)가 발생되는 문제점이 있었다. 또한, 비트라인을 형성하기 위한 접촉홀을 셀영역과 주변회로영역에 별도의 공정으로 형성하여 공정이 복잡해지는 문제점이 있었다.However, in the semiconductor device manufacturing method according to the related art described above, when the driving transistor in the peripheral circuit region forms the low concentration region and the high concentration region, impurities in the low concentration region are diffused to shorten the channel length, thereby shortening the channel effect. channel effect) has occurred. In addition, the contact hole for forming the bit line is formed in a separate process in the cell region and the peripheral circuit region has a problem that the process is complicated.
따라서, 본 발명의 목적은 단채널효과를 방지할 수 있는 반도체장치의 제조방법을 제공함에 있다.Accordingly, it is an object of the present invention to provide a method for manufacturing a semiconductor device capable of preventing short channel effects.
본 발명의 다른 목적은 셀영역과 주변회로영역에 비트라인을 형성하기 위한 접촉홀을 동시에 형성하여 공정 수를 감소시킬 수 있는 반도체장치의 제조방법을 제공함에 있다.Another object of the present invention is to provide a method of manufacturing a semiconductor device which can reduce the number of processes by simultaneously forming contact holes for forming bit lines in a cell region and a peripheral circuit region.
상기 목적들을 달성하기 위한 본 발명에 따른 반도체장치의 제조방법은 셀영역과 주변회로영역을 갖는 제 1 도전형의 반도체기판 상에 게이트산화막, 게이트층, 제 1 및 제 2 캡층을 순차적으로 형성하고 상기 주변회로영역의 상기 제 2 캡층을 제거하는 공정과, 상기 제 1 및 제 2 캡층, 게이트층 및 게이트산화막을 패터닝하여 게이트를 한정하고 상술한 구조의 표면에 상기 제 1 캡층과 식각선택비가 다른 물질로 마스크층을 형성하는 공정과, 상기 마스크층의 상기 게이트와 대응하는 부분에 상기 측벽과 식각선택비가 다른 물질로 제 1 측벽을 상기 셀영역에서 상기 마스크층이 노출되지 않도록 인접하는 것들이 연결되게 형성하고 상기 반도체기판의 상기 주변회로영역에 제 2 도전형의 고농도영역을 형성하는 공정과, 상기 제 1 측벽을 선택적으로 제거하고 상기 반도체기판의 상기 셀영역 및 상기 주변회로영역에 제 2 도전형의 저농도영역을 형성하는 공정과, 상기 마스크층을 상기 반도체기판이 노출되도록 에치백하여 상기 게이트의 측면에 제 2 측벽을 형성하는 공정과, 상술한 구조의 전 표면에 상기 제 2 캡층 및 상기 제 2 측벽과 식각선택비가 다른 절연물질을 증착하여 제 1 층간절연층을 형성하고 상기 셀영역의 상기 제 2 불순물영역 중 인접하는 트랜지스터들이 공유하지 않는 영역이 노출되도록 패터닝하여 제 1 접촉홀을 형성하는 공정과, 상기 제 1 접촉홀 내에 플러그를 형성하며 상기 제 1 층간절연층 상에 상기 플러그를 덮는 제 2 층간절연층을 형성하는 공정과, 상기 셀영역 내의 상기 제 2 불순물영역 중 상기 플러그와 접촉되지 않는 영역을 노출시키는 제 2 접촉홀과 상기 주변회로영역 내의 소정 게이트을 노출시키는 제 3 접촉홀을 동시에 형성하는 공정을 구비한다.A semiconductor device manufacturing method according to the present invention for achieving the above objects is formed by sequentially forming a gate oxide film, a gate layer, the first and second cap layer on a semiconductor substrate of the first conductivity type having a cell region and a peripheral circuit region Removing the second cap layer of the peripheral circuit region; patterning the first and second cap layers, the gate layer, and the gate oxide layer to define a gate; and having an etch selectivity different from that of the first cap layer on the surface of the structure described above. Forming a mask layer with a material, and connecting the first sidewall to a portion corresponding to the gate of the mask layer with a material having a different etch selectivity from the sidewall so that the mask layer is not exposed in the cell region; Forming a high concentration region of a second conductivity type in the peripheral circuit region of the semiconductor substrate; and selectively forming the first sidewall. And forming a low concentration region of a second conductivity type in the cell region and the peripheral circuit region of the semiconductor substrate, and etching the mask layer to expose the semiconductor substrate to form second sidewalls on the side of the gate. And depositing an insulating material having an etch selectivity different from that of the second cap layer and the second sidewall on the entire surface of the above-described structure to form a first interlayer insulating layer and adjacent ones of the second impurity regions of the cell region. Forming a first contact hole by patterning a region not shared by the transistors, and forming a plug in the first contact hole and forming a second interlayer insulating layer on the first interlayer insulating layer to cover the plug. And a second contact hole and the peripheral circuit region exposing a region which is not in contact with the plug among the second impurity regions in the cell region. And simultaneously forming a third contact hole for exposing a predetermined gate in the chamber.
도 1a 내지 도 1f는 종래 기술에 따른 반도체장치의 제조방법을 도시하는 공정도1A to 1F are process drawings showing a method for manufacturing a semiconductor device according to the prior art.
도 2a 내지 도 2f는 본 발명에 따른 반도체장치의 제조방법을 도시하는 공정도2A to 2F are process drawings showing a method of manufacturing a semiconductor device according to the present invention.
이하, 첨부한 도면을 참조하여 본 발명을 상세히 설명한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2f는 본 발명에 따른 반도체장치의 제조방법을 도시하는 공정도이다.2A to 2F are process charts showing the manufacturing method of the semiconductor device according to the present invention.
도 2a를 참조하면, 셀영역(C2) 및 주변회로영역(P2)을 갖는 P형의 반도체기판(51)의 소정 부분에 STI 또는 LOCOS 등의 방법에 의해 소자의 활성영역을 한정하는 필드산화막(53)을 형성한다. 상기에서 반도체기판(51) 상의 필드산화막(53)이 형성되지 않은 부분은 활성영역이 된다.Referring to FIG. 2A, a field oxide film that defines an active region of an element by a method such as STI or LOCOS in a predetermined portion of a P-type semiconductor substrate 51 having a cell region C2 and a peripheral circuit region P2 ( 53). The portion where the field oxide film 53 is not formed on the semiconductor substrate 51 becomes an active region.
반도체기판(51) 상의 활성영역에 열산화 방법에 의해 게이트산화막(55)을 형성한다. 그리고, 필드산화막(53) 및 게이트산화막(55) 상에 불순물이 도핑된 다결정실리콘을 CVD 방법으로 증착하여 게이트층(57)을 형성하고, 이 게이트층(57) 상에The gate oxide film 55 is formed in the active region on the semiconductor substrate 51 by a thermal oxidation method. Then, polycrystalline silicon doped with impurities on the field oxide film 53 and the gate oxide film 55 is deposited by CVD to form a gate layer 57, and on the gate layer 57.
산화실리콘 또는 질화실리콘으로 이루어진 제 1 캡층(59)과 질화실리콘 또는 산화실리콘으로 이루어진 제 2 캡층(61)을 순차적으로 형성한다. 상기에서 게이트층(57)을 다결정실리콘으로 형성하였으나 다결정실리콘 및 실리사이드층의 2중층으로 형성할 수도 있다. 또한, 제 1 및 제 2 캡층(59)(61)은 식각선택비가 다른 절연물질을 CVD 방법으로 증착하여 형성하는 데, 예를 들면, 제 1 캡층(59)을 산화실리콘으로 형성하면 제 2 캡층(61)을 질화실리콘으로 형성하며, 또한, 제 1 캡층(59)을 질화실리콘으로 형성하면 제 2 캡층(61)을 산화실리콘으로 형성한다.A first cap layer 59 made of silicon oxide or silicon nitride and a second cap layer 61 made of silicon nitride or silicon oxide are sequentially formed. Although the gate layer 57 is formed of polycrystalline silicon in the above, a double layer of polycrystalline silicon and a silicide layer may be formed. In addition, the first and second cap layers 59 and 61 are formed by depositing an insulating material having a different etching selectivity by the CVD method. For example, when the first cap layer 59 is formed of silicon oxide, the second cap layer is formed. 61 is formed of silicon nitride, and when the first cap layer 59 is formed of silicon nitride, the second cap layer 61 is formed of silicon oxide.
주변회로영역(P2) 상의 제 2 캡층(61)을 포토리쏘그래피 방법으로 제 1 캡층(59)이 노출되도록 패터닝하여 제거한다.The second cap layer 61 on the peripheral circuit region P2 is patterned and removed to expose the first cap layer 59 by a photolithography method.
도 2b를 참조하면, 게이트층(57)을 포토리쏘그래피 방법으로 패터닝하여 게이트(58)을 형성한다. 이 때, 셀영역(C2)의 제 2 캡층(61)을 패터닝한 후 셀영역(C2) 및 주변회로영역(P2)의 제 1 캡층(59), 게이트층(57) 및 게이트산화막(55)을 반도체기판(51)이 노출되도록 패터닝한다.Referring to FIG. 2B, the gate layer 57 is patterned by photolithography to form the gate 58. At this time, after patterning the second cap layer 61 of the cell region C2, the first cap layer 59, the gate layer 57, and the gate oxide layer 55 of the cell region C2 and the peripheral circuit region P2 are patterned. The semiconductor substrate 51 is patterned to expose the semiconductor substrate 51.
반도체기판(51) 상에 게이트(58), 제 1 및 제 2 캡층(59)(61)의 표면에 제 2 캡층(61)과 동일한 물질, 즉, 질화실리콘 또는 산화실리콘을 CVD 방법으로 증착하여 마스크층(63)을 형성한다. 그리고, 마스크층(63)의 게이트(58), 제 1 및 제 2 캡층(59)(61)의 측면과 대응하는 부분 상에 제 1 측벽(65)을 형성한다. 상기에서 제 1 측벽(65)은 마스크층(63) 상에 이 마스크층(63)과 식각선택비가 다른 물질, 산화실리콘 또는 질화실리콘을 증착하고 반응성이온식각(Reactive Ion Etching : 이하, RIE라 칭함) 등의 방법으로 에치백하여 형성하는 데, 셀영역(C2) 내에는 이 제 1 측벽(65)은 마스크층(63)이 노출되지 않도록 인접하는 것들이 연결되게 형성되도록 한다.The same material as the second cap layer 61, that is, silicon nitride or silicon oxide, is deposited on the surfaces of the gate 58, the first and second cap layers 59 and 61 on the semiconductor substrate 51 by CVD. The mask layer 63 is formed. The first sidewall 65 is formed on portions of the mask layer 63 that correspond to the side surfaces of the gate 58 and the first and second cap layers 59 and 61. The first sidewall 65 is formed on the mask layer 63 by depositing a material, silicon oxide or silicon nitride having an etch selectivity different from that of the mask layer 63, and referred to as reactive ion etching (hereinafter referred to as RIE). In the cell region C2, the first sidewall 65 is formed such that adjacent ones are connected to each other so that the mask layer 63 is not exposed.
제 1 및 제 2 캡층(59)(61)과 제 1 측벽(65)을 마스크로 사용하여 인(P) 또는 아세닉(As) 등의 N형 불순물을 고농도로 이온 주입하여 반도체기판(51)의 주변회로영역(P2)에 구동 트랜지스터의 소오스 및 드레인영역으로 이용되는 제 1 불순물영역(67)을 형성한다. 이 때, 반도체기판(51)의 셀영역(C2)은 제 1 측벽(65)에 의해 불순물이 주입되지 않으므로 제 1 불순물영역(67)이 형성되지 않게된다.Using the first and second cap layers 59 and 61 and the first sidewall 65 as a mask, the semiconductor substrate 51 is ion-implanted with a high concentration of N-type impurities such as phosphorus (P) or arsenic (As). The first impurity region 67 used as the source and drain regions of the driving transistor is formed in the peripheral circuit region P2. In this case, since the impurity is not injected into the cell region C2 of the semiconductor substrate 51 by the first sidewall 65, the first impurity region 67 is not formed.
도 2c를 참조하면, 제 1 측벽(65)을 습식식각하여 제거한다. 이 때, 마스크층(63)은 제 1 측벽(65)과 식각선택비가 다르므로 제거되지 않고 제 1 측벽(65)만 선택적으로 제거된다.Referring to FIG. 2C, the first sidewall 65 is removed by wet etching. At this time, since the etching selectivity is different from that of the first sidewall 65, only the first sidewall 65 is selectively removed.
반도체기판(51)에 인(P) 또는 아세닉(As) 등의 N형 불순물을 저농도로 이온 주입하여 제 2 불순물영역(69)을 형성한다. 상기에서 제 2 불순물영역(69)은 셀영역(C2)에서 트랜지스터의 소오스 및 드레인영역으로 이용되며 주변회로영역(P2)에서 제 1 불순물영역(67)과 중첩되게 형성되어 구동트랜지스터의 LDD영역으로 이용된다. 또한, 제 2 불순물영역(69)은 마스크층(63)에 의해 게이트(58)와 중첩되는 것이 억제된다. 상기에서 제 2 불순물영역(69)이 제 1 불순물영역(67)을 형성한 후에 형성하고 마스크층(63)에 의해 게이트(58)와 중첩되는 것이 억제되게 형성되므로 채널 길이가 짧아지는 것을 억제하므로 단채널효과를 방지할 수 있다.The second impurity region 69 is formed by ion implanting N-type impurities, such as phosphorus (P) or arsenic (As), at low concentration into the semiconductor substrate 51. The second impurity region 69 is used as the source and drain regions of the transistor in the cell region C2 and overlaps with the first impurity region 67 in the peripheral circuit region P2 to form the LDD region of the driving transistor. Is used. In addition, the second impurity region 69 is suppressed from overlapping with the gate 58 by the mask layer 63. Since the second impurity region 69 is formed after the first impurity region 67 is formed and overlaps with the gate 58 by the mask layer 63, the channel length is reduced. The short channel effect can be prevented.
도 2d를 참조하면, 마스크층(63)을 RIE 등의 방법으로 반도체기판(51)이 노출되도록 에치백하여 제 2 측벽(71)을 형성한다. 상술한 구조의 전 표면에 제 2 캡층(61) 및 제 2 측벽(71)과 식각선택비가 다른 절연물질, 즉, 산화실리콘 또는 질화실리콘을 CVD 방법으로 증착하여 제 1 층간절연층(73)을 형성한다. 그리고, 셀영역(C2) 내의 제 1 층간절연층(73)을 포토리쏘그래피 방법으로 패터닝하여 제 2 불순물영역(69)을 노출시키는 제 1 접촉홀(75)을 형성한다. 상기에서 제 1 접촉홀(75)은 셀영역(C2) 내의 제 2 불순물영역(69) 중 인접하는 트랜지스터들이 공유하지 않는 영역을 노출시킨다. 이 때, 제 1 층간절연층(73)이 제 2 캡층(61) 및 제 2 측벽(71)과 식각선택비가 서로 다르므로 제 1 접촉홀(75)은 자기 정렬되게 형성된다.Referring to FIG. 2D, the mask layer 63 is etched back to expose the semiconductor substrate 51 by RIE or the like to form the second sidewall 71. The first interlayer insulating layer 73 is formed by depositing an insulating material having a different etching selectivity from the second cap layer 61 and the second sidewall 71, that is, silicon oxide or silicon nitride, by the CVD method on the entire surface of the above-described structure. Form. The first interlayer insulating layer 73 in the cell region C2 is patterned by a photolithography method to form a first contact hole 75 exposing the second impurity region 69. In this case, the first contact hole 75 exposes an area of the second impurity region 69 in the cell region C2 that is not shared by adjacent transistors. In this case, since the etch selectivity of the first interlayer insulating layer 73 and the second cap layer 61 and the second sidewall 71 are different from each other, the first contact hole 75 is formed to be self-aligned.
도 2e를 참조하면, 제 1 접촉홀(75) 내에 제 2 불순물영역(69)과 접촉되어 전기적으로 연결되는 플러그(77)를 형성한다. 상기에서 플러그(77)는 제 1 층간절연층(73) 상에 제 1 접촉홀(75)을 채우도록 금속 등의 도전성 물질을 증착한 후 제 1 층간절연층(73)이 노출되고 제 1 접촉홀(75) 내부에만 잔류되게 에치백하므로써 형성된다. 플러그(77)는 이후에 형성될 캐패시터의 스토리지전극을 셀영역(C2) 내의 제 2 불순물영역(69)과 전기적으로 연결시킨다.Referring to FIG. 2E, a plug 77 is formed in the first contact hole 75 to be in contact with the second impurity region 69 to be electrically connected to the second impurity region 69. In the plug 77, a conductive material such as metal is deposited on the first interlayer insulating layer 73 to fill the first contact hole 75, and then the first interlayer insulating layer 73 is exposed and the first contact is made. It is formed by etching back so as to remain only inside the hole 75. The plug 77 electrically connects the storage electrode of the capacitor to be formed later with the second impurity region 69 in the cell region C2.
제 1 층간절연층(73) 상에 플러그(77)를 덮는 제 2 층간절연층(79)을 형성한다. 상기에서 제 2 층간절연층(79)도 제 2 캡층(61) 및 제 2 측벽(71)과 식각선택비가 다른 산화실리콘 또는 질화실리콘을 CVD 방법으로 증착하므로써 형성된다.A second interlayer insulating layer 79 covering the plug 77 is formed on the first interlayer insulating layer 73. The second interlayer insulating layer 79 is also formed by depositing silicon oxide or silicon nitride having a different etching selectivity from the second cap layer 61 and the second sidewall 71 by the CVD method.
셀영역(C2) 내의 제 2 불순물영역(69) 중 플러그(77)와 접촉되지 않는 인접하는 트랜지스터들이 공유하는 영역을 노출시키는 제 2 접촉홀(81)과 주변회로영역(P2) 내의 소정 게이트(58)을 노출시키는 제 3 접촉홀(83)을 도포리쏘그래피 방법으로 형성한다. 상기에서 제 2 접촉홀(81)은 제 3 접촉홀(83) 보다 깊이가 깊은 데, 제 2 캡층(61)과 제 2 측벽(71)이 제 1 층간절연층(73) 및 캡층(59)과 식각선택비가 다르므로 제 3 접촉홀(83)의 형성이 완료된 후에도 셀영역(C2)의 반도체기판(51)이 노출되도록 과도식각하므로써 제 2 접촉홀(81)을 형성한다.The second contact hole 81 exposing a region shared by adjacent transistors which are not in contact with the plug 77 among the second impurity regions 69 in the cell region C2 and a predetermined gate in the peripheral circuit region P2 ( A third contact hole 83 exposing 58 is formed by an applied lithography method. The second contact hole 81 is deeper than the third contact hole 83, and the second cap layer 61 and the second sidewall 71 are formed of the first interlayer insulating layer 73 and the cap layer 59. Since the etching selectivity is different from that of the second contact hole 81, the second contact hole 81 is formed by overetching the semiconductor substrate 51 in the cell region C2 even after the third contact hole 83 is formed.
도 2f를 참조하면, 제 2 층간절연층(79) 상에 셀영역(C2)에서 제 2 접촉홀(81)을 통해 제 1 불순물영역(69)과 접촉되며, 주변회로영역(P2)에서 제 3 접촉홀(83)을 통해 게이트(58)와 접촉되어 전기적으로 연결되는 비트라인(85)(87)을 형성한다.Referring to FIG. 2F, the first impurity region 69 is contacted on the second interlayer insulating layer 79 through the second contact hole 81 in the cell region C2, and is formed in the peripheral circuit region P2. The bit lines 85 and 87 are formed to be in contact with the gate 58 through the three contact holes 83.
따라서, 본 발명은 저농도의 제 2 불순물영역을 고농도의 제 1 불순물영역을 형성한 후에 형성하므로 저농도의 제 2 불순물영역의 확산이 억제되어 단채널효과를 방지할 수 있으며, 또한, 셀영역 및 주변회로영역의 비트라인을 형성하기 위한 제 2 및 제 3 접촉창을 동시에 형성하므로 공정이 단순해지는 잇점이 있다.Therefore, the present invention forms the second impurity region of low concentration after forming the first impurity region of high concentration, so that diffusion of the second impurity region of low concentration can be suppressed and the short channel effect can be prevented. The process is simplified because the second and third contact windows for forming the bit line of the circuit area are simultaneously formed.
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