KR20000019563A - Method for fabricating heterojunction bipolar transistor - Google Patents

Abstract

PURPOSE: A method for fabricating a heterojunction bipolar transistor is provided to improve a speed characteristic of the transistor by reducing a base resistance. CONSTITUTION: A heterojunction bipolar transistor epi structure is formed on a substrate(1) up to an external base(2) layer. A dielectric layer is on an epi wafer, a base is etched by using the dielectric layer as a mask. The external base(2) is etched by using the dielectric layer(7) as a mask. An emitter portion of the heterojunction bipolar transistor is grown by use of a selective-area regrowth. After removing the dielectric layer used as the mask, a new dielectric layer is deposited on an entire surface of the epi wafer, and is reactive ion-etched. A semiconductor layer is removed via a selective etching. A base electrode(12) is deposited on the resultant structure, and an emitter(8) and a base electrode(12) are formed by a self aligned structure with the dielectric layer(11) sandwiched therebetween. An emitter, a base and a collector are formed according to a well-known manner.

Description

Manufacturing method of heterojunction dipole transistor

The present invention relates to a method for manufacturing a heterojunction bipolar transistor (HBT) having a selective recrystallized grown emitter structure. More particularly, the base structure of a heterojunction dipole transistor, which is a compound semiconductor ultra-fast device, can be obtained from an external base and an internal base. It is to improve the speed characteristics of heterojunction dipole transistors by reducing the base resistance by applying selective-area regrowth technology, which is a kind of semiconductor epitaxial growth technology, to the emitter structure.

In general, heterojunction dipole devices are manufactured using compound semiconductors such as gallium arsenide (GaAs) or indium phosphorus (InP) systems. The heterojunction dipole device manufactured as described above is a kind of ultra-high speed electronic device operating in the microwave or millimeter wave frequency band of tens or hundreds of GHz, and is an integrated circuit for processing high-speed optical information communication and microwaves in the tens or GHz band. It is widely applied in the manufacture of MMIC for wireless communication using millimeter wave, and the optical information communication and wireless communication integrated circuit technology using heterojunction dipole elements is the core technology for the development of next generation high speed information communication system technology. It is applied.

The structure of a conventional heterojunction dipole device is shown in FIG. 4, and in order to improve the maximum oscillation frequency (Maximum Oscillation Frequencyifmax), which is the most important speed characteristic of such a heterojunction dipole device, the base resistance should be reduced.

As shown in FIG. 2, the base resistance includes a sum of a contact resistance component generated when the base electrode contacts the base compound semiconductor layer and the spreading resistance component of the external base compound semiconductor layer itself. have. In the structure of the heterojunction dipole device using the prior art, the following limitations exist in reducing the base resistance value.

That is, in the heterojunction dipole device using the prior art, the base impurity concentration must be high to reduce the base resistance value, but when the base impurity concentration is increased, the life time of the electron in the base is shortened, so that the current gain of the transistor is reduced. Will decrease. Another method is to increase the thickness of the base, which also increases the base transit time of the electrons, which reduces the current gain of the transistor, resulting in a decrease in the maximum operating frequency. do.

An object of the present invention is to reduce the base resistance and to simultaneously reduce the base contact and spreading resistance components without reducing the current gain of the heterojunction dipole element in improving the speed characteristic (maximum operating frequency) of the heterojunction dipole element. It is done.

The present invention for achieving the above object is to divide the base structure of the heterojunction dipole device into an inner base and an outer base to optimize the impurity concentration and thickness of each of them.

In other words, by using the selective recrystallization growth technology, the impurity concentration and thickness of the internal base for determining the current gain of the heterojunction dipole device can be optimized to optimize the current gain of the device and the base passage time of the electron, The base contact resistance and the spreading resistance value to be configured are to reduce the resistance value by increasing the impurity concentration and thickness of the external base.

As described above, the present invention has no influence on the current gain of the heterojunction dipole device due to the wide thickness of the external base and the high impurity concentration. Therefore, the maximum operating frequency of the heterojunction dipole device is reduced by reducing the base resistance without changing the current gain. It will be improved.

1 is a cross-sectional view of a heterojunction dipole transistor structure completed by the present invention.

2 is an enlarged view of a part of FIG. 1;

(A) to (i) of Figure 3 is a heterojunction dipole according to a preferred embodiment of the present invention

Manufacturing Process Diagram of Transistor

4 is a cross-sectional view of a conventional heterojunction dipole transistor structure.

<Description of Symbols for Major Parts of Drawings>

1 substrate 2 outer base 3 inner base

4: etching stop layer 5: sub collector 6: collector

7,11: dielectric layer 8: emitter 9: emitter cap

10 compound semiconductor layer 12 base electrode

The present invention will be described in the order of steps as an example through FIGS. 3A to 3I.

Description of the terms used in the following description is as follows.

(1) Base contact resistance: Resistance component formed when the base electrode metal is in contact with the base semiconductor

(2) Base spreading resistance: resistance component of the base semiconductor layer itself

(3) Outer base: base layer doped with ultra high concentration of impurities to form very small base contact resistance

(4) Internal base: Base area that determines the current gain of the heterojunction dipole transistor and the base pass time of the electrons (similar to the base of a conventional high speed heterojunction dipole transistor)

(5) Emitter cap and sub-collector: semiconductor layers doped with high-concentration impurities to form ohmic electrodes on the emitter and collector, respectively.

(6) Etch stop layer: A semiconductor layer that allows the external base reaction to be etched using a selective etching process (the solution or medium for etching the outer base does not etch the stop layer).

(7) Anisotropic Etching: Etching method with different etching speed depending on direction (eg RIE, CAIBE, ION Milling, etc.)

[Step 1]

As shown in FIG. 3A, the substrate 1 is grown up to the outer base 2 layer of the heterojunction dipole transistor epitaxial structure.

The impurity concentration and thickness of the inner base 3 in the first step may be the same as the conventional base structure, and the etch stop layer 4 is not etched in the solution for etching the outer base 2. Material is used, and its thickness is so thin that it does not prevent the flow of current by the tunneling effect. In addition, the outer base 2 is an ultrahigh concentration semiconductor layer (P> 1 × 10 ²⁰ / cm 3) having a thickness of about several hundred A. 5 is a sub collector and 6 is a collector.

Second Process

As shown in (b) of FIG. 3, a dielectric layer is deposited on the epi wafer on the entire surface, an emitter pattern is formed using a photomask, and the dielectric layer is etched to form a dielectric layer 7 of the type shown in the figure.

[Third process]

As shown in Fig. 3C, the outer base 2 is etched using the dielectric layer 7 in the second step as a mask.

At this time, the etching method used is an selective etching method which only etches the outer base 2 and does not etch the etch stop layer 4. In this case, the use of the etch stop layer 4 and the selective etching method enables precise control of the base thickness of the heterojunction dipole transistor, thereby increasing the yield by uniformizing the electrical characteristics of the transistor.

[4th process]

The epi-wafer having undergone the third process is put back into the crystal growth system to grow the emitter portion of the heterojunction dipole transistor using a selective recrystallization method.

In the above, a chemical beam epitaxy (CBE) or a MOCVD system (Metalorganic Chemical Vapor Deposition System) is mainly used for selective recrystallization, and crystal growth is performed in the dielectric layer 7 at an appropriate growth temperature (mainly high temperature). Instead, crystal growth occurs only on semiconductors without dielectrics.

As shown in (d) of FIG. 3, three compound semiconductor layers are grown by selective recrystallization, and the roles of the two layers are as follows.

That is, reference numeral 8 shown in FIG. 3D is an emitter layer of the heterojunction dipole transistor, and a material having a larger energy band cap than the base is used. Reference numeral 9 uses a material having a small energy band cap of ultra high impurity concentration to reduce contact resistance when forming a metal electrode on the emitter as an emitter cap layer. Reference numeral 10 denotes a compound semiconductor layer grown for the purpose of fabricating a self-aligning base electrode as shown in FIG. 3 (f) (g) as a compound semiconductor layer which can be selectively etched with the emitter cap layer 9.

[5th process]

As in the fourth process, after the selective recrystallization growth, the dielectric layer 7 used as the mask is removed, and a new dielectric layer 11 is deposited on the front surface of the epi wafer, and then an anisotropic etching process is performed as shown in FIG. ; Reactive Ion Etching).

[Sixth Step]

When the anisotropic etching process is performed as in the fifth process, the dielectric deposited on the plane is etched away, but only the dielectric deposited on the side remains, and the compound semiconductor layer 10 is selectively etched as shown in FIG. Remove

[7th process]

The base electrode 12 is deposited on the structure obtained in the sixth step, so that the emitter 8 and the base electrode 12 are self-aligned with the dielectric layer 11 interposed therebetween as shown in FIG. To form a structure.

[Step 8]

After the seventh process, as shown in (h) and (i) of FIG. 3, the metal electrodes of the emitter, the base, and the collector are formed as in the conventional heterojunction dipole transistor fabrication process.

As mentioned above, the whole cross-sectional structure of this invention obtained by the 1st process-the 8th process is shown as FIG.

The present invention divides the base structure into an outer base layer, an etch stop layer, and an inner base layer so that the current gain of the heterojunction dipole transistor and the base pass rate of the electron are optimized by the thickness of the inner base and the impurity concentration. By individually optimizing by the concentration and thickness of the base layer, it is possible to greatly improve the speed characteristics, that is, the maximum operating frequency of the heterojunction dipole transistor, and the etch stop layer is caused by the change of the thickness of the internal base that can be generated during the etching process. It has the effect of increasing the yield of the device by preventing the nonuniformity of the device characteristics.

Claims (5)

The first step of growing a heterojunction dipole transistor epitaxial structure on a substrate (1) up to an outer base (2) layer, depositing a dielectric layer (7) on an epi wafer, and forming an emitter pattern using a photomask, The second step of etching (7), the third step of etching the external base 2 using the dielectric layer 7 in the second step as a mask, and the epi wafer which has undergone the third step are used for the crystal growth system. A fourth step of growing the emitter portion of the heterojunction dipole transistor by using a selective recrystallization method, and removing the dielectric layer 7 used as a mask after selective recrystallization growth and depositing a new dielectric layer 11 on the front surface of the epi wafer. And a fifth process for performing anisotropic etching after removal, a sixth process for removing the compound semiconductor layer 10 through selective etching, and a structure obtained in the sixth process. A seventh step of depositing the e-electrode 12 and forming the self-aligned structure with the emitter 8 and the base electrode 12 interposed therebetween with the dielectric layer 11 interposed therebetween, and the first to seventh steps. And a method of manufacturing a heterojunction dipole transistor, comprising the eighth step of forming a metal electrode of an emitter, a base, and a collector, respectively, according to a known method. 2. The base of claim 1, wherein the base of the heterojunction dipole transistor is divided into an outer base (2) layer and an inner base (3) layer, and the outer base (2) layer is etched using the etch stop layer (4). (3) A method of manufacturing a heterojunction dipole transistor, wherein the emitter 8 is grown by selective recrystallization. 2. The outer base 2 is designed to reduce the base resistance by doping ultra high concentration impurities, and the inner base 3 is an impurity capable of optimizing the current gain of the heterojunction dipole transistor and the base passage time of the electron. A method of manufacturing a heterojunction dipole transistor, characterized by maintaining concentration and thickness. 2. The heterojunction dipole according to claim 1, wherein an etch stop layer, which is a compound semiconductor layer 10 having different physical properties from the outer base 2, is inserted to selectively etch only the outer base 2 using a selective etching method. A method of manufacturing a heterojunction dipole transistor, characterized in that the base thickness of the transistor is made uniform. The self-aligned base electrode is formed by growing a compound semiconductor layer (10) capable of selective etching on the emitter (8) and the emitter cap (6) layer upon selective recrystallization of the emitter structure. A method of manufacturing a heterojunction dipole transistor, characterized by enabling this.