KR20000018734A - Method for forming a high density plasma insulator of semiconductor devices - Google Patents

Method for forming a high density plasma insulator of semiconductor devices Download PDF

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Publication number
KR20000018734A
KR20000018734A KR1019980036479A KR19980036479A KR20000018734A KR 20000018734 A KR20000018734 A KR 20000018734A KR 1019980036479 A KR1019980036479 A KR 1019980036479A KR 19980036479 A KR19980036479 A KR 19980036479A KR 20000018734 A KR20000018734 A KR 20000018734A
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South Korea
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high density
density plasma
forming
insulating film
film
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KR1019980036479A
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Korean (ko)
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전영수
노태효
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윤종용
삼성전자 주식회사
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Publication of KR20000018734A publication Critical patent/KR20000018734A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76819—Smoothing of the dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76826—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by contacting the layer with gases, liquids or plasmas

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE: A high density plasma insulating layer formation method is provided to prevent a detaching at interface between the high density plasma insulator and an oxide layer. CONSTITUTION: A method comprises the steps of forming a lower film(13) having a contact hole on a semiconductor substrate(11); forming a high density plasma insulator(15) to fill in the contact hole using a plasma apparatus; and removing a polymer(7) generated at interface of the high density plasma insulator(15) by etch-back in the same plasma apparatus by in-situ. The etch-back is performed by using an argon gas.

Description

반도체 소자의 고밀도 플라즈마 절연막 형성방법High Density Plasma Insulator Formation Method of Semiconductor Device

본 발명은 반도체 소자의 제조방법에 관한 것으로, 특히 고밀도 플라즈마 절연막의 형성방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming a high density plasma insulating film.

반도체 소자의 제조 기술이 점차 고집적화되고 반도체 소자가 빠른 속도9speed)가 요구됨에 따라서 반도체 소자는 종래의 단일 금속층 구조 또는 이중 금속층 구조에서 다층 금속층 구조로 바뀌고 있다. 이러한 다층 금속층 구조에서는 층간 절연막을 화학기상증착법(chemical vapor deposition)을 이용하여 형성하고 있다.As the manufacturing technology of semiconductor devices is increasingly integrated and the semiconductor devices are required to have a high speed (9 speed), semiconductor devices are changing from a conventional single metal layer structure or a double metal layer structure to a multilayer metal layer structure. In such a multilayer metal layer structure, an interlayer insulating film is formed by chemical vapor deposition.

상기 화학기상증착법은 막질의 증착 속도를 빠르게 조절할 수 있고, 막질의 조성 조절이 용이하다는 장점이 있지만, 화학기상증착법에 의하여 형성한 막질이 강도면에서는 다소 취약하여 금속층 위에 사용할 때 하부 금속층의 조건 및 레이아웃 등에 의하여 취약한 지점에 균열(crack)이 발생하는 경우가 있다. 상기 균열은 금속층과 화학기상증착법에 의하여 형성한 막질의 열팽창 계수가 달라 발생한다.The chemical vapor deposition method has an advantage that the deposition rate of the film can be quickly controlled and the composition of the film can be easily controlled. However, the film quality formed by the chemical vapor deposition method is somewhat weak in terms of strength, so that the conditions of the lower metal layer and A crack may occur at a weak point due to the layout or the like. The cracks are caused by different coefficients of thermal expansion of the film formed by the metal layer and chemical vapor deposition.

이에 따라서, 상기 균열를 방지하고 금속층 사이의 공간(space)을 잘 메울수(filling) 있는 방법으로써 고밀도 플라즈마(high density plasma) 설비를 이용하여 막질을 형성하는 고밀도 플라즈마 공정이다.Accordingly, it is a high density plasma process that forms a film using a high density plasma facility as a method of preventing the crack and filling the space between the metal layers.

그러나, 상기 고밀도 플라즈마 공정을 사용함에 있어서 여러 가지 불량이 발생되는데, 그 중 하나가 도 1에 도시한 바와 같이 하지막(3), 예컨대 금속층이 형성된 반도체 기판(1) 상에 고밀도 플라즈마 절연막(5)을 형성하면 그 표면(계면)의 골진 부위에 폴리머(7)가 잔존하는 것이다. 이렇게 되면, 후속의 화학기상증착법에 의한 산화막(9) 증착후 평탄화를 위하여 수행하는 화학기계적연마(chemical mechanical polishing) 공정 및 습식 화학용액에 의한 세정시 화학용액의 침투 및 상기 화학기계적연마시의 물리적인 충격에 의하여 고밀도 플라즈마 절연막(5)과 화학기상증착법에 의한 산화막(9)의 계면 박리 현상이 발생되는 문제점이 있다.However, various defects occur in using the high-density plasma process. One of them is a high-density plasma insulating film 5 on the semiconductor substrate 1 on which the underlayer 3, for example, a metal layer is formed, as shown in FIG. ), The polymer 7 remains in the corrugated portion of the surface (interface). In this case, the chemical mechanical polishing process performed for the planarization after deposition of the oxide film 9 by the subsequent chemical vapor deposition method and the penetration of the chemical solution during the cleaning by the wet chemical solution and the physical mechanical polishing process Due to the phosphorous impact, there is a problem in that an interfacial peeling phenomenon occurs between the high density plasma insulating film 5 and the oxide film 9 by chemical vapor deposition.

따라서, 본 발명이 이루고자 하는 기술적 과제는 상기 폴리머를 제거할 수 있는 반도체 소자의 고밀도 플라즈마 절연막 형성방법을 제공하는 데 있다.Accordingly, an object of the present invention is to provide a method for forming a high density plasma insulating film of a semiconductor device capable of removing the polymer.

도 1은 종래기술에 의한 반도체 소자의 고밀도 플라즈마 절연막 형성방법을 설명하기 위하여 도시한 단면도이다.1 is a cross-sectional view illustrating a method for forming a high density plasma insulating film of a semiconductor device according to the prior art.

도 2는 본 발명에 의한 반도체 소자의 고밀도 플라즈마 절연막 형성방법을 설명하기 위하여 도시한 단면도이다.2 is a cross-sectional view for explaining a method for forming a high density plasma insulating film of a semiconductor device according to the present invention.

상기 기술적 과제를 달성하기 위하여, 본 발명은 반도체 기판 상에 콘택홀을 갖는 하지막을 형성하는 단계와, 상기 하지막이 형성된 반도체 기판의 전면에 상기 콘택홀을 매립하도록 고밀도 플라즈마 설비에 의하여 고밀도 플라즈마 절연막을 형성하는 단계와, 상기 고밀도 플라즈마 절연막 형성시 고밀도 플라즈마 절연막의 계면에 발생하는 폴리머를 상기 고밀도 플라즈마 설비에서 에치백하여 제거하는 단계를 포함하여 이루어지는 것을 특징으로 하는 반도체 소자의 고밀도 플라즈마 절연막 형성방법을 제공한다.In order to achieve the above technical problem, the present invention provides a method of forming a base film having a contact hole on a semiconductor substrate, and forming a high density plasma insulating film by a high density plasma apparatus to fill the contact hole in the entire surface of the semiconductor substrate on which the base film is formed. And forming and removing the polymer generated at the interface of the high density plasma insulating film by forming the high density plasma insulating film in the high density plasma facility. do.

상기 고밀도 플라즈마 절연막은 고밀도 플라즈마 산화막이며, 상기 에치백은 아르곤 가스를 이용하여 수행한다.The high density plasma insulating film is a high density plasma oxide film, and the etch back is performed using argon gas.

이하, 첨부 도면을 참조하여 본 발명의 실시예를 상세히 설명한다.Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 2는 본 발명에 의한 반도체 소자의 고밀도 플라즈마 절연막 형성방법을 설명하기 위하여 도시한 단면도이다.2 is a cross-sectional view for explaining a method for forming a high density plasma insulating film of a semiconductor device according to the present invention.

구체적으로, 반도체 기판(11) 상에 콘택홀을 갖는 하지막(13)을 형성한다. 상기 반도체 기판(11)은 실리콘 기판을 이용하여, 상기 하지막(13)은 다층의 금속층 구조에서 하나의 금속층일 수 있다.Specifically, an underlayer 13 having a contact hole is formed on the semiconductor substrate 11. The semiconductor substrate 11 may be a silicon substrate, and the base layer 13 may be one metal layer in a multilayer metal layer structure.

다음에, 상기 하지막(13)이 형성된 반도체 기판의 전면에 상기 콘택홀을 매립하도록 고밀도 플라즈마 설비에 의하여 고밀도 플라즈마 절연막(15)을 형성한다. 본 실시예에서, 상기 고밀도 플라즈마 절연막(15)은 사일렌(SiH4) 및 산소를 이용하여 형성되는 고밀도 플라즈마 산화막이다.Next, a high density plasma insulating film 15 is formed by a high density plasma facility so as to fill the contact hole in the entire surface of the semiconductor substrate on which the base film 13 is formed. In the present exemplary embodiment, the high density plasma insulating film 15 is a high density plasma oxide film formed by using xylene (SiH 4 ) and oxygen.

여기서, 상기 고밀도 플라즈마 설비를 이용한 고밀도 플라즈마 절연막 형성 방법을 자세하 설명한다. 상기 고밀도 플라즈마 설비는 증착과 아르곤을 이용한 에치백을 동시에 실시할 수 있는 설비이다. 그런데, 본 실시예에 의한 고밀도 플라즈마 산화막(15) 형성시 사일렌과 산소로 증착하면서 아르곤에 의한 에치백을 실시하는 가운데 상기 고밀도 플라즈막 산화막(15) 내에 다량의 아르곤 입자가 존재하며 증착 종료시 스퍼터링된 아르곤에 의하여 에치된 산화물 입자와 아르곤이 하부 패턴의 굴곡진 계면에 싸여 도 1에 도시한 바와 같이 고밀도 플라즈마 산화막의 계켠에 기공(porous) 상태의 폴리머(7)가 발생한다. 상기 폴리머(7)는 상술한 바와 같이 후속의 화학기계적연마시 연마 패드의 압력으로 인하여 폴리머가 박리되어 후속의 화학기상증착법에 의하여 형성한 산화막의 들뜸(lifting) 현상이 발생한다. 따라서, 반도체 소자를 제조하기 위하여는 이를 제거하는 것이 필요하다.Here, the high density plasma insulating film formation method using the said high density plasma installation is demonstrated in detail. The high density plasma facility is a facility capable of simultaneously performing deposition and etch back using argon. However, a large amount of argon particles are present in the high density plasma film oxide film 15 while sputtering at the end of the deposition while performing the etch back by argon while depositing with xylene and oxygen when forming the high density plasma oxide film 15 according to the present embodiment. Oxide particles etched by the argon and the argon are wrapped in the curved interface of the lower pattern, and as shown in FIG. As described above, the polymer 7 peels off the polymer due to the pressure of the polishing pad during subsequent chemical mechanical polishing, thereby causing a lifting phenomenon of the oxide film formed by the subsequent chemical vapor deposition. Therefore, in order to manufacture a semiconductor device it is necessary to remove it.

이를 해결하기 위하여, 상기 고밀도 플라즈마 절연막(15) 형성시 고밀도 플라즈마 절연막의 계면에 발생하는 폴리머(도 1의 7)를 상기 고밀도 플라즈마 설비에서 에치백(etch-back)하여 제거한다. 즉, 고밀도 플라즈마 절연막(15) 형성한 후 사일렌 및 산소를 고밀도 플라즈마 설비의 챔버에 유입시키지 않고 추가로 아르곤에 바이어스를 걸어 에치백하는 것이다. 다시 말하면, 사일렌 및 산소를 챔버에 유입시키지 않아 증착은 더 이상 일어나지 않은 상태에서 아르곤 바이어스를 일정 시간, 예컨대 수십초간 계속 걸어 반도체 기판(11)의 전면에 일정 시간 동안 아르곤에 의한 에치백(etch back)을 실시하는 것이다. 이렇게 되면, 상기 고밀도 플라즈마 절연막(15) 계면에 존재하는 폴리머(도 1의 7)가 제거된다.In order to solve this problem, the polymer (7 in FIG. 1) generated at the interface of the high density plasma insulating film 15 is formed by etching back to the high density plasma facility. That is, after forming the high density plasma insulating film 15, it does not inject xylene and oxygen into the chamber of a high density plasma installation, but further biases argon and etches back. In other words, the argon bias is continuously applied for a predetermined time, for example, several tens of seconds while the silicide and oxygen are not introduced into the chamber and the deposition is no longer occurring. back). In this case, the polymer (7 of FIG. 1) which exists in the interface of the said high density plasma insulating film 15 is removed.

다음에, 상기 폴리머(도 1의 7)가 제거된 반도체 기판(11)의 전면에 화학기장증착법에 의한 산화막(19)을 증착한 후, 화학기계적연막 및 습식 세정하여 평탄화함으로써 반도체 소자의 다층 금속층 구조를 완성한다.Next, after depositing the oxide film 19 by chemical vapor deposition on the entire surface of the semiconductor substrate 11 from which the polymer (7 in FIG. 1) has been removed, the multilayer metal layer of the semiconductor device by planarizing by chemical mechanical vapor deposition and wet cleaning. Complete the structure.

이상, 실시예를 통하여 본 발명을 구체적으로 설명하였지만, 본 발명은 이에 한정되는 것이 아니고, 본 발명의 기술적 사상 내에서 당 분야에서 통상의 지식으로 그 변형이나 개량이 가능하다.As mentioned above, although this invention was demonstrated concretely through the Example, this invention is not limited to this, A deformation | transformation and improvement are possible with the conventional knowledge in the art within the technical idea of this invention.

이상의 본 발명의 고밀도 플라즈마 절연막 형성방법에 의하여 폴리머가 제거되면 다음과 같은 효과가 있다.When the polymer is removed by the high density plasma insulating film forming method of the present invention as described above has the following effects.

첫째로, 후속의 화학기상증착법에 의한 산화막과 고밀도 플라즈마 절연막 간의 계면 접촉을 향상시켜 고밀도 플라즈마 절연막에서의 필요한 강도와 분리(isolation) 효과를 얻을 수 있다. 둘째로, 후속의 화학기계적연마시 기공상태의 계면에 화학기계적연마용 화학용액의 침투 및 물리적인 충격에 의하여 발생하는 계면 박리현상을 없앨 수 있다. 셋째로, 후속의 화학기계적연마후 세정 공정시 기공상태의 계면에 습식 식각 용액 침투에 의한 계면 박리 현상을 막을 수 있다.First, the interface contact between the oxide film and the high density plasma insulating film by the subsequent chemical vapor deposition method can be improved to obtain the necessary strength and isolation effect in the high density plasma insulating film. Secondly, it is possible to eliminate the interfacial peeling phenomenon caused by the penetration of the chemical mechanical polishing chemical solution and the physical impact at the pore interface during the subsequent chemical mechanical polishing. Third, in the subsequent cleaning process after chemical mechanical polishing, it is possible to prevent the interface peeling phenomenon caused by the penetration of the wet etching solution into the pore interface.

Claims (3)

반도체 기판 상에 콘택홀을 갖는 하지막을 형성하는 단계;Forming a base film having a contact hole on the semiconductor substrate; 상기 하지막이 형성된 반도체 기판의 전면에 상기 콘택홀을 매립하도록 고밀도 플라즈마 설비에 의하여 고밀도 플라즈마 절연막을 형성하는 단계; 및Forming a high density plasma insulating film by a high density plasma facility so as to fill the contact hole on the entire surface of the semiconductor substrate on which the base film is formed; And 상기 고밀도 플라즈마 절연막 형성시 고밀도 플라즈마 절연막의 계면에 발생하는 폴리머를 상기 고밀도 플라즈마 설비에서 에치백하여 제거하는 단계를 포함하여 이루어지는 것을 특징으로 하는 반도체 소자의 고밀도 플라즈마 절연막 형성방법.And etching back and removing the polymer generated at the interface of the high density plasma insulating film in the high density plasma facility during the formation of the high density plasma insulating film. 제1항에 있어서, 상기 고밀도 플라즈마 절연막은 고밀도 플라즈마 산화막인 것을 특징으로 하는 반도체 소자의 고밀도 플라즈마 절연막 형성방법.The method for forming a high density plasma insulating film of a semiconductor device according to claim 1, wherein the high density plasma insulating film is a high density plasma oxide film. 제1항에 있어서, 상기 에치백은 아르곤 가스를 이용하여 수행하는 것을 특징으로 하는 반도체 소자의 고밀도 플라즈마 절연막 형성방법.The method of claim 1, wherein the etch back is performed using argon gas.
KR1019980036479A 1998-09-04 1998-09-04 Method for forming a high density plasma insulator of semiconductor devices KR20000018734A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10040528B2 (en) 2013-02-08 2018-08-07 Samsung Heavy Ind. Co., Ltd. Propulsion device for ship

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10040528B2 (en) 2013-02-08 2018-08-07 Samsung Heavy Ind. Co., Ltd. Propulsion device for ship

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