KR20000016942A - Method for rorming a gate contact directly over the channel region of a mos transistor - Google Patents

Abstract

PURPOSE: A method for depositing directly a gate contact in a channel domain of a MOS transistor is provided to protect a gate and a spacer from an etching procedure by using an etching stationary layer. CONSTITUTION: The method for depositing directly a gate contact in a channel domain of a MOS transistor comprises the steps of: depositing an etching stationary layer(330) having a surface on a MOS transistor(310); depositing a dielectric substance(332) having a surface on the etching stationary layer(330); depositing a mask(334) on the dielectric substance(332); patterning the mask(334) on the surface of the dielectric substance(332) to limit a first contact portion on the etching stationary layer(330) and a second contact portion on a gate surface of a channel domain(320); etching an unmasked portion of the dielectric substance(332) until the dielectric substance(332) is removed from the first contact portion of the surface of the etching stationary layer(330); and etching the first contact portion of the etching stationary layer(330) to limit a contact aperture portion until the etching stationary layer(330) is removed from the second contact portion of the gate surface.

Description

METHOD FOR RORMING A GATE CONTACT DIRECTLY OVER THE CHANNEL REGION OF A MOS TRANSISTOR}

Technical field

The present invention relates to a method of forming a transistor contact, and more particularly to a method of directly forming a gate contact on a channel region of a MOS transistor.

Description of the related technology

Integrated circuits are formed from MOS transistors and other devices that are electrically connected to each other to implement the desired functionality of the circuit. Structurally, the MOS transistors are typically formed on the surface of the semiconductor substrate and are separated from each other by the field oxide region.

On the other hand, an electrical passage connecting the MOS transistor and another device to each other is formed on a layer of dielectric material formed on the transistor. The electrical connection between the MOS transistor and the upper electrical passage is made by a vertical section of conductive material, again known as a contact.

1A shows a top view illustrating a conventional MOS contact structure 100. FIG. 1B shows a cross sectional view taken along line 1B-1B of FIG. 1A, while FIG. 1C shows a cross sectional view taken along line 1C-1C of FIG. 1A.

As shown in FIGS. 1A-1C, the structure 100 is formed on the surface of the substrate 112 to surround and separate the MOS transistor 110 formed on the surface of the semiconductor substrate 112 and the transistor 110. The formed field oxide region FOX.

The MOS transistor 110 further includes a source region 114 formed in the substrate 112, a drain region 116 formed in the substrate 112, and a channel region 120 defined between the source and drain regions 114 and 116. .

In addition, the transistor 110 also includes a gate oxide layer 122 formed on the channel region 120, and a gate 124 formed on the gate oxide layer 122 and a portion of the field oxide region FOX. do. Moreover, oxide spacer 126 is formed adjacent to sidewalls of gate oxide layer 122 and gate 124.

As also shown in FIGS. 1A-1C, structure 100 is a dielectric material layer 128 formed on MOS transistor 110, a source region 130 formed in dielectric layer 128 in contact with source region 114. ), A drain region 132 formed in dielectric layer 128 to contact drain region 116, and a dielectric layer 128 formed in contact with gate 124 on a portion of the field oxide region FOX. It further includes a gate contact 134.

The structure 100 additionally includes a series of metal-1 interconnects 142, 144, 146 connected to the contacts 130, 132, 134, respectively. Contacts 130 and 132 on dielectric layer 128;

Metal-1 interconnects 142, 144, and 146, each extending away from 134, form an electrical passage that allows MOS transistors and other devices in the circuit to be connected to each other.

One problem with structure 100 is that the field oxide region (FOX) must consume more silicon area than necessary for isolation to accommodate the size of gate contact 134. This in turn makes it difficult to increase the density of the circuit without increasing the overall area of the circuit.

One solution to this problem is to simply form a gate contact on the channel region. However, this solution is difficult to implement due to process problems occurring in the manufacture of the contacts.

Conventionally, contacts are made by first forming a dielectric layer and planarizing it. Next, the dielectric layer is etched to form contact openings.

In practice, however, the etchant that was used to etch the dielectric layer was poorly selected for polysilicon, which is typically used to form the gate. As a result, most of the gate is usually removed during the etching step, thereby destroying or substantially changing the characteristics of the MOS transistors. Moreover, plasma etchers that emit high energy particles often damaged underlying gate oxide layers.

Although more recent etching devices have greatly eliminated these problems, the trend towards continued miniaturization of integrated circuits has created new problems for placing gate contacts on channels. According to a design rule of 0.5 microns or less, the width W of the gate 124 (see FIG. 1A) is always smaller than the contact size. Thus, when a gate contact is connected to the gate 124 on the channel region 120, the gate contact is always formed on a particular portion of the oxide spacer 126 that is always surrounded.

In addition, due to process variations, the depth of dielectric layer 128 is not uniform on the gates of all MOS transistors in the circuit. Moreover, to ensure that good contacts are made, all of the dielectric layer 128 must be removed from the contact sites on the surface of the gate 124.

Thus, some over etching is required to remove all of the dielectric layer 128 from the contact sites on the surface of the gate 128 and to accommodate the different thicknesses of the dielectric layer 128. However, such over etching often causes an excessive amount of oxide spacer 126 to be removed, which in turn results in an electrical short to the substrate.

2 shows a cross-sectional view of an SEM photograph illustrating over etching on MOS contact structure 200. Figure 2 is the same as Figure 1B, and therefore the same reference numerals are used to refer to the structures common to all of the structures.

As shown in FIG. 2, the main difference between structure 200 and structure 100 is that in structure 200, gate contacts 210 are formed on gate 124 on channel region 120. However, due to over etching, a portion of the gate contact 210 also extends down the side of the gate 124 to the substrate 112, thereby electrically shorting the gate 124 to the substrate 112.

Thus, in view of the above, there is a need for a process for forming a gate contact on a channel region without etching away and removing an excessive amount of sidewall spacers.

It is an object of the present invention to provide a method of forming a gate contact on a channel region by using an etch stop layer to protect the gate and adjacent oxide spacers from the etching step of forming contact openings.

1A is a plan view illustrating a conventional MOS contact structure 100.

1B is a cross-sectional view taken along line 1B-1B in FIG. 1A.

1C is a cross-sectional view taken along line 1C-1C in FIG. 1A.

FIG. 2 is a cross-sectional view of a SEM photograph illustrating over etching on MOS contact structure 200. FIG.

3A-3D are cross-sectional views illustrating a process of forming a transistor according to the present invention.

Conventionally, it is difficult to form gate contacts on the channel region of a MOS transistor because the etching step of forming contact openings in the poly-metal-1 layer of dielectric material also consumes an excessive amount of oxide spacers formed adjacent to the gate. .

The present invention provides a method of forming the gate contact on the channel region by using an etch stop layer to protect the gate and adjacent oxide spacers from the etching step of forming contact openings.

According to the present invention, the method begins with the step of conventionally forming a spaced source and drain region formed in a semiconductor material, and a channel region formed in the semiconductor material between the source and drain regions.

In addition, the MOS transistor also has a gate oxide layer formed on the channel region, and a gate formed on the gate oxide layer. Moreover, the transistor also has a spacer formed to be adjacent to the gate oxide layer and sidewalls of the gate.

After forming the MOS transistor in a conventional manner, the method continues with forming an etch stop material layer on the MOS transistor. Next, a dielectric material layer is formed on the etch stop layer.

After the dielectric layer is formed, a mask is formed on the dielectric material layer. The mask is then patterned to define an unmasked site on the surface of the dielectric material. The unmasked portion again defines a first contact portion on the surface of the etch stop layer and a second contact portion on the surface of the gate on the channel region.

Next, the unmasked portion of the dielectric material layer is etched until the dielectric material layer is removed from the first contact portion on the surface of the etch stop layer. Next, the first contact portion of the etch stop layer is etched until the etch stop layer is removed from the second contact portion on the surface of the gate to define a contact opening.

The features and advantages of the present invention will be better understood with reference to the accompanying drawings and the following detailed description showing exemplary embodiments in which the principles of the present invention are used.

Example

3A-3D show cross-sectional views illustrating a process of forming a transistor junction in accordance with the present invention. As will be described in more detail below, the present invention allows a gate contact to be formed on the channel region of a MOS transistor. This is accomplished by using an etch stop layer to protect the gate and adjacent oxide spacers from the etching step of forming contact openings in the poly-metall layer of dielectric material.

As shown in Figure 3A, the process of the present invention conventionally forms a field oxide region (FOX) in a semiconductor material 312, such as a substrate or well, and then conventionally forms a MOS transistor in the material 312. From the step of forming.

As also shown in FIG. 3A, the MOS transistor 310 includes spaced source and drain regions 314 and 316 formed in the material 312 so as to be adjacent to a portion of the field oxide region FOX, respectively. Channel region 320 defined within the material between regions 314 and 316. The source and drain regions 314 and 316 again include an implant region and an upper metal silicide layer 318. (The source and drain regions 314 and 316 may alternatively be formed without the upper metal silicide layer 318.) .

In addition, transistor 310 also includes a gate oxide layer 322 formed on channel region 320, and a gate 324 formed on gate oxide layer 322. Gate 324 again includes a polysilicon (poly) layer and an upper metal silicide layer 318. (Gate 324 may alternatively be formed without an upper metal silicide layer 318.) Furthermore, oxide spacer 326 is formed adjacent to sidewalls of gate oxide layer 322 and gate 324.

After forming the MOS transistor 310 in a conventional manner, an etch stop material layer 330 of approximately 300-700 microns thick is deposited on the MOS transistor 310 and the field oxide region FOX. Once the etch stop layer 330 is formed, a dielectric material layer 332 of approximately 10,000 microns thick is formed on the etch stop layer 330. Once formed, dielectric layer 332 is planarized using flow / reflow, etch back, chemical-mechanical polishing (CMP) or other similar technique.

Next, a mask 334 is formed and patterned on the dielectric layer 332 to define a plurality of unmasked portions on the surface of the dielectric layer 332. The unmasked portion again defines a plurality of first contact portions on the surface of the etch stop layer 330, defines a second contact portion on the surface of the source region 314, and drain region 316. Define a second contact portion on the surface and define a second contact portion on the surface of the gate 324. Other areas that can be contacted include local interconnect portions of semiconductor material, and other areas.

Next, as shown in FIG. 3B, the unmasked portion of the dielectric material layer 332 is completely removed from the first contact portion on the surface of the etch stop layer 330. Until etched.

After etching the dielectric layer 332, the etch stop layer 330 has a second contact portion on the surface of the source region 314, a second contact portion on the surface of the drain region 316. It is etched until it is completely removed from the contact site and the second contact site on the surface of the gate 324. As shown in FIG. 3B, two etching steps produce a plurality of contact openings 336. In addition, conventional techniques are used to form the shape of the contact openings 336 having anisotropic lower sections and isotropic upper sections.

Next, as shown in FIG. 3C, a metal layer 340 is deposited to fill the contact openings 336 on the dielectric layer 332 and the second contact portion. As shown in FIG. 3D, once metal layer 340 is deposited, metal layer 340 is etched back to form source contact 342, drain contact 344, and gate contact 346. do. After this, the process returns to the conventional stage.

For the material, the dielectric layer 332 may be any material that meets the known requirements of the poly-metall dielectric layer, such as doped or undoped silicon dioxide, or doped or undoped tetraethyl orthosilicate ( TEOS).

Etch stop layer 330 may be implemented with any material that strongly inhibits etching when dielectric layer 332 is etched. As shown in FIG. 3B, dielectric layer 332 is significantly deeper for source region 314 than for gate 324. As a result, the etch stop layer 330 on the gate 324 should be able to withstand significant over etching when contact openings are also formed in the source region.

For example, if the dielectric layer 332 is implemented with a doped silicon dioxide layer, the etch stop layer 330 may have silicon oxynitride etch rate of silicon dioxide when silicon dioxide is applied to known etching techniques. It can be implemented with silicon oxynitride (SiON) because it has a slower etching rate.

In addition to the above, the etch stop layer 330 is also easy while the surrounding structures, such as dielectric layers, oxide spacers, poly gates, and metal silicided gates, sources, and drains, are etched at much slower etch rates. It can also be implemented with a material that is etched. Silicon oxynitride, for example, also meets the requirements of such an etch stop layer.

Thus, according to the present invention, a method of forming a contact point structure having a gate contact formed on a channel region has been described so far. This method allows the field oxide regions to be made smaller, which in turn increases the density of the circuit.

It should be understood that various modifications to the embodiments of the invention described herein may be used to practice the invention. Accordingly, the appended claims define the scope of the invention and methods and structures belonging to the claims and their equivalents are intended to be included in the invention.

Accordingly, the present invention provides a method of forming a gate contact on a channel region using an etch stop layer to protect the gate and adjacent oxide spacers from the etching step of forming contact openings, thereby etching an excessive amount of sidewall spacers. The gate contact can be formed on the channel region without removing it.

Claims (5)

A method of forming a contact structure on a MOS transistor formed in a semiconductor material, the MOS transistor comprising: Spaced sources and drains formed in the semiconductor material; A channel region defined within the semiconductor material between the source and drain regions; A gate oxide layer formed on said channel region and having sidewalls; A gate formed on the gate oxide layer and having a surface and sidewalls; And A spacer formed adjacent to the gate oxide layer and sidewalls of the gate In the method of having, Forming a etch stop material layer having a surface on the MOS transistor; Forming a surface-bearing dielectric material layer on the etch stop layer; Forming a mask on the dielectric material layer; On the surface of the dielectric material to define an unmasked portion that defines a first contact portion on the surface of the etch stop layer and a second contact portion on the surface of the gate on the channel region. Patterning the mask; Etching the unmasked portion of the dielectric material layer until the dielectric material layer is removed from the first contact portion on the surface of the etch stop layer; And Etching the first contact portion of the etch stop layer until the etch stop material layer is removed from a second contact portion on the surface of the gate to define a contact opening. How to include. The method of claim 1 wherein the gate comprises polysilicon and an upper conductive material layer. 2. The method of claim 1, further comprising forming a conductive material layer on the dielectric material layer to fill the contact openings. A method of forming a contact structure on a MOS transistor formed in a semiconductor material, the MOS transistor comprising: A spaced source and drain formed in the semiconductor material and having a surface; A channel region defined within the semiconductor material between the source and drain regions; A gate oxide layer formed on said channel region and having sidewalls; A gate formed on the gate oxide layer and having a surface and sidewalls; And A spacer formed adjacent to the gate oxide layer and sidewalls of the gate In the method of having, Forming a etch stop material layer having a surface on the MOS transistor; Forming a surface-bearing dielectric material layer on the etch stop layer; Forming a mask on the dielectric material layer; Define a plurality of first contact sites on the surface of the dielectric material, a plurality of first contact sites on the surface of the etch stop layer, define gate contact sites on the surface of the gate on the channel region, and source contact sites on the surface of the source. Patterning the mask to define and define a plurality of unmasked portions defining a drain contact portion on a surface of the drain; Etching the unmasked portion of the dielectric material layer until the dielectric material layer is removed from the first contact portion on the surface of the etch stop layer; And The etch stop material layer is removed from the gate contact portion on the surface of the gate to define a gate contact opening, removed from the source contact portion on the surface of the source to define a source contact opening, and the drain to define a drain contact opening. Etching the first contact portion of the etch stop layer until removed from the drain contact portion on the surface of the film How to include. In a MOS contact structure formed in a semiconductor material, Spaced sources and drains formed in the semiconductor material; A channel region defined within the semiconductor material between the source and drain regions; A gate oxide layer formed on said channel region and having sidewalls; A gate formed on the gate oxide layer and having a surface and sidewalls; And A spacer formed adjacent to the gate oxide layer and sidewalls of the gate A MOS transistor having; An etch stop material layer having a gate opening on the MOS transistor, the gate opening exposing a portion of a surface of the gate formed on the channel region; A dielectric material layer exposing a portion of the surface of the gate on and in and on the etch stop layer; And A gate contact formed in the gate opening of the etch stop and dielectric material layer adjacent to a portion of the surface of the gate MOS contact structure comprising a.