KR20000015594A - Marking method for fabricating semiconductor package - Google Patents

Marking method for fabricating semiconductor package Download PDF

Info

Publication number
KR20000015594A
KR20000015594A KR1019980035620A KR19980035620A KR20000015594A KR 20000015594 A KR20000015594 A KR 20000015594A KR 1019980035620 A KR1019980035620 A KR 1019980035620A KR 19980035620 A KR19980035620 A KR 19980035620A KR 20000015594 A KR20000015594 A KR 20000015594A
Authority
KR
South Korea
Prior art keywords
semiconductor package
wafer
semiconductor
marking
circuit
Prior art date
Application number
KR1019980035620A
Other languages
Korean (ko)
Other versions
KR100370844B1 (en
Inventor
윤주훈
강대병
박인배
Original Assignee
김규현
아남반도체 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김규현, 아남반도체 주식회사 filed Critical 김규현
Priority to KR10-1998-0035620A priority Critical patent/KR100370844B1/en
Priority to JP11200832A priority patent/JP3055104B2/en
Priority to US09/385,694 priority patent/US6589801B1/en
Publication of KR20000015594A publication Critical patent/KR20000015594A/en
Application granted granted Critical
Publication of KR100370844B1 publication Critical patent/KR100370844B1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)

Abstract

PURPOSE: A marking method for fabricating semiconductor package is provide to reduce the number of manufacturing process and enhance productivity. CONSTITUTION: The marking method for fabricating semiconductor package comprises: a step presenting a wafer; a step presenting a circuit tape; a step bonding said wafer and circuit tape; a wire bonding step connecting said wafer and circuit tape by a wire; an encapsulation step coating said wire bonding portion with sealing material and curing it; a solder ball bumping step bumping a solder ball; a step cutting plural semiconductor chips along a street line on said wafer to form a semiconductor package having the same size as that of the chip; and a step picking up said cut semiconductor package, dividing good package and rework package through inspection, marking said packages with rotation state by 180 degree, and separating the good and rework packages.

Description

반도체 패키지 제조를 위한 마킹방법Marking method for semiconductor package manufacturing

본 발명은 반도체 패키지 제조를 위한 마킹방법에 관한 것으로, 더욱 상세하게는 반도체 패키지의 뒷면에 마킹하는 공정을 픽엔플레이스(Pick & Place) 공정에서 함께 하도록 함으로써, 제조공정을 단축시켜 생산성을 향상시키도록 된 반도체 패키지 제조를 위한 마킹방법에 관한 것이다.The present invention relates to a marking method for manufacturing a semiconductor package, and more particularly to the process of marking on the back of the semiconductor package in the Pick & Place (Pick & Place) process, to shorten the manufacturing process to improve productivity The present invention relates to a marking method for manufacturing a semiconductor package.

일반적으로 전자 제품, 통신 기기, 컴퓨터 등 반도체 패키지가 실장되는 전자 제품들이 소형화되어 가고 있는 추세에 따라 반도체 패키지의 크기를 기능의 저하없이 소형화시키고, 고다핀을 구현하면서 경박단소화 하고자 하는 새로운 형태의 반도체 패키지(예를 들면, 반도체칩의 크기와 동일한 크기로 형성되는 칩 사이즈 패키지)가 개발되어 있다.In general, as electronic products, such as electronic products, communication devices, and computers, are being miniaturized, new types of semiconductor packages are being miniaturized without degrading their function and miniaturization while minimizing high size. A semiconductor package (for example, a chip size package formed to be the same size as that of a semiconductor chip) has been developed.

이러한 반도체 패키지는, 다수의 반도체칩이 형성되어 있는 웨이퍼상에 회로패턴이 형성되어 있는 써킷테이프를 접착시킨 채, 웨이퍼상에서 와이어본딩, 인캡슐레이션 및 솔더볼 범핑을 마친 후, 마지막 단계에서 상기한 웨이퍼를 각각의 반도체칩으로 절단하여 독립된 반도체 패키지를 완성하는 방법에 의해 제조되는 것이 일반적이다.Such a semiconductor package is a wafer as described above in the last step after wire bonding, encapsulation and solder ball bumping are completed on a wafer while a circuit tape having a circuit pattern formed thereon is bonded on a wafer on which a plurality of semiconductor chips are formed. Is manufactured by a method of cutting an individual semiconductor chip into a separate semiconductor package.

이와 같이 웨이퍼상에서 각각의 반도체칩으로 절단되어 제조된 반도체 패키지는 픽엔플레이스 장비를 이용하여 트레이에 안착시키고, 이 트레이를 이송시키면서 후 공정인 마킹공정 등을 수행한다.As described above, a semiconductor package manufactured by cutting each semiconductor chip on a wafer is placed on a tray using a pick-and-place equipment, and then the marking process is performed while transferring the tray.

따라서, 종래에는 반도체 패키지의 뒷면에 마킹을 하기 위해서는 픽엔플레이스 장비를 이용하여 반도체 패키지를 트레이에 안착시키고, 이와 같이 트레이에 안착된 상태에서 상기한 트레이를 별도의 마킹장비에서 이송시키면서 반도체 패키지의 뒷면에 마킹을 하였다.Therefore, conventionally, in order to mark the back of the semiconductor package, the semiconductor package is seated on a tray using a pick-and-place equipment, and the tray is transported from a separate marking device while the tray is seated on the tray. Marked on.

그러나, 이러한 방법의 마킹은 별도의 마킹장비가 필요함은 물론, 반도체 패키지를 트레이에 안착시키기 위한 픽엔플레이스 장비도 필요하다. 즉, 픽엔플레이스장비와 마킹장비가 각각 필요하게 된다.However, the marking of this method requires a separate marking equipment, as well as pick-and-place equipment for seating the semiconductor package on the tray. That is, pick and place equipment and marking equipment are required.

또한, 상기한 마킹장비에서 반도체 패키지가 안착된 트레이를 이송시키면서 마킹할 때에는 상기한 반도체 패키지를 정위치에 고정시키기 위한 장치들이 필요함으로써, 기계장치의 구성이 복잡하고, 이러한 마킹장비를 이용한 마킹은 픽엔플레이스 공정과 마킹공정이 구분지어서 행해짐으로써, 공정수가 추가되는 등의 문제점도 있다.In addition, when marking while transporting the tray on which the semiconductor package is seated in the marking equipment is required for the device for fixing the semiconductor package in place, the configuration of the mechanical device is complicated, marking using this marking equipment Since the pick-and-place process and the marking process are performed separately, there is a problem that the number of steps is added.

본 발명의 목적은 이와 같은 문제점을 해소하기 위하여 발명된 것으로서, 반도체 패키지의 뒷면에 마킹하는 공정을 픽엔플레이스 공정시에 하도록 함으로써, 제조공정을 단축시켜 생산성을 향상시키도록 된 반도체 패키지 제조를 위한 마킹방법을 제공함에 있다.An object of the present invention has been invented to solve such a problem, by marking the back side of the semiconductor package during the pick-and-place process, marking for manufacturing a semiconductor package to shorten the manufacturing process to improve productivity In providing a method.

도 1은 반도체 패키지의 제조공정을 나타낸 블럭도1 is a block diagram showing a manufacturing process of a semiconductor package

이하, 본 발명을 첨부된 도면을 참조하여 상세히 설명하면 다음과 같다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

본 발명에 따른 반도체 패키지의 제조공정은, 도 1에 도시된 바와 같이 전자회로가 집적되어 있는 다수의 반도체칩이 형성된 웨이퍼를 제공하는 단계와, 상기한 웨이퍼에 형성된 다수의 반도체칩에 대응하는 회로가 형성되어 있는 써킷테이프(Circuit Tape)를 제공하는 단계와, 상기한 웨이퍼와 상기한 써킷테이프를 접착시키는 단계와, 상기한 웨이퍼상에 형성된 반도체칩의 신호를 상기한 써킷테이프의 회로에 전달할 수 있도록 와이어로 연결하는 와이어본딩단계와, 상기한 와이어본딩단계에서 와이어로 본딩된 부분을 보호하도록 봉지재로 덮어씌우고, 이 봉지재를 경화시키는 인캡슐레이션단계와, 상기한 써킷테이프의 회로에 전달된 신호를 외부로 전달하도록 솔더볼을 범핑하는 솔더볼범핑단계와, 상기한 웨이퍼상의 스트리트 라인(Street Line)을 따라 다수의 반도체칩을 절단하는 절단단계를 거쳐 반도체칩의 크기와 동일한 크기의 반도체 패키지를 완성한다.The manufacturing process of the semiconductor package according to the present invention comprises the steps of providing a wafer having a plurality of semiconductor chips in which the electronic circuit is integrated, as shown in Figure 1, a circuit corresponding to the plurality of semiconductor chips formed on the wafer Providing a circuit tape on which the wafer is formed, adhering the wafer and the circuit tape to each other, and transmitting a signal of a semiconductor chip formed on the wafer to the circuit of the circuit tape. A wire bonding step of connecting the wire so that the wire bonding step is covered with an encapsulant to protect the wire-bonded portion in the wire bonding step, the encapsulation step of curing the encapsulant, and the circuit of the circuit tape. A solder ball bumping step of bumping the solder ball to transmit the signal to the outside, and following the above-described street line on the wafer After the cutting step of cutting a plurality of the semiconductor chip to complete the semiconductor package of the same size as the size of the semiconductor chip.

상기와 같은 제조공정을 거쳐 완성된 반도체 패키지의 뒷면에 마킹을 하기 위한 본 발명의 제1 실시예는, 웨이퍼상에서 절단된 반도체 패키지를 픽업한 후, 인스펙션(Inspection)하여 양호한 반도체 패키지와 리워크(Rework ; 반도체 패키지의 제조공정을 다시 실시하여야 될 반도체 패키지)가 필요한 반도체 패키지를 구분하고, 상기 양호한 반도체 패키지와 리워크가 필요한 반도체 패키지를 180°회전시킨 상태에서 마킹을 실시하며, 마킹이 완료된 양호한 반도체 패키지와 리워크가 필요한 반도체 패키지는 서로 다른 트레이에 각각 구분지어서 안착시키는 단계에 의해 픽엔플레이스 및 마킹이 완료된다.According to a first embodiment of the present invention for marking a back surface of a semiconductor package completed through the manufacturing process as described above, the semiconductor package cut on the wafer is picked up, inspected, and inspected to obtain a good semiconductor package and rework ( Rework (semiconductor package to be re-manufactured) is divided into semiconductor packages, and marking is performed in a state where the good semiconductor package and the semiconductor package requiring rework are rotated by 180 ° and marking is completed. The semiconductor package and the semiconductor package requiring the rework are picked and marked by the step of placing the semiconductor packages separately placed in different trays.

이때, 상기한 웨이퍼상에서 절단된 반도체 패키지를 픽업하기 위한 데이타는 웨이퍼 맵 파일(Wafer Map File ; 웨이퍼상에 반도체칩이 양호한 반도체칩과 불량인 반도체칩으로 구별시키는 정보가 데이타로 저장되어 있는 파일)에 의해 불량으로 판정된 반도체칩이 패키지화 된 자재는 픽업하지 않고, 양호한 반도체칩이 패키지화 된 자재 만을 픽업하여 마킹한다.At this time, the data for picking up the semiconductor package cut on the wafer is a wafer map file; Does not pick up the material in which the semiconductor chip has been determined to be packaged, but picks up and marks only the material in which the good semiconductor chip is packaged.

본 발명의 제1 실시예에 의한 반도체 패키지의 마킹방법은, 반도체 패키지의 뒷면에 마킹하는 공정을 웨이퍼 맵 파일을 이용하여 양호한 반도체칩이 패키지화 된 자재만을 픽엔플레이스 공정시에 함께 마킹함으로써, 제조공정을 단축시킬 수 있는 장점이 있다.In the method of marking a semiconductor package according to the first embodiment of the present invention, a process of marking a back surface of a semiconductor package is performed by using only a wafer map file to mark only materials in which a good semiconductor chip is packaged together during a pick-and-place process. There is an advantage that can shorten.

또한, 반도체 패키지의 뒷면에 마킹을 하기 위한 본 발명의 제2 실시예는, 웨이퍼상에서 절단된 반도체 패키지를 픽업한 후, 인스펙션(Inspection)하여 양호한 반도체 패키지와 리워크(Rework ; 반도체 패키지의 제조공정을 다시 실시하여야 될 반도체 패키지)가 필요한 반도체 패키지를 구분하고, 상기 양호한 반도체 패키지와 리워크가 필요한 반도체 패키지를 180°회전시켜 서로 다른 트레이에 각각 구분지어서 안착시킨 후, 마킹을 실시하는 단계에 의해 픽엔플레이스 및 마킹이 완료된다.In addition, according to a second embodiment of the present invention for marking the back surface of a semiconductor package, a semiconductor package cut on a wafer is picked up and inspected to inspect a good semiconductor package and a rework. The semiconductor package to be re-executed) is separated, and the good semiconductor package and the semiconductor package requiring the rework are rotated by 180 ° to be seated separately in different trays, and then marked. Pick and place and marking are complete.

이때, 상기한 웨이퍼상에서 절단된 반도체 패키지를 픽업하기 위한 데이타는 웨이퍼 맵 파일(Wafer Map File ; 웨이퍼상에 반도체칩이 양호한 반도체칩과 불량인 반도체칩으로 구별시키는 정보가 데이타로 저장되어 있는 파일)을 이용하여 불량으로 판정된 반도체칩이 패키지화 된 자재는 픽업하지 않고, 양호한 반도체칩이 패키지화 된 자재 만을 픽업한다.At this time, the data for picking up the semiconductor package cut on the wafer is a wafer map file; The pick-up of the material in which the semiconductor chip packaged as defective is not carried out is carried out, and only the material in which the good semiconductor chip is packaged is picked up.

본 발명의 제2 실시예에 의한 반도체 패키지의 마킹방법은, 반도체 패키지의 뒷면에 마킹하는 공정을 웨이퍼 맵 파일을 이용하여 양호한 반도체칩이 패키지화 된 자재만을 선택적으로 픽업하여 트레이에 안착시킨 상태로 마킹함으로써, 불량의 반도체칩이 패키지화 된 자재를 마킹하지 않아 불량률을 줄이고, 작업 효율을 높일 수 있는 이점이 있다.In the method of marking a semiconductor package according to the second embodiment of the present invention, a process of marking the back surface of a semiconductor package is performed by using a wafer map file, selectively picking only materials in which a good semiconductor chip is packaged, and marking the sheet on a tray. By doing so, there is an advantage in that the defective semiconductor chip does not mark the packaged material, thereby reducing the defective rate and increasing the work efficiency.

상기와 같은 방법에 의한 마킹을 실시하기 위한 장비의 일 예는, 웨이퍼상에서 절단된 반도체 패키지를 픽업하는 픽업부와, 상기한 픽업부에서 픽업된 반도체 패키지를 180°회전시켜 그 뒷면이 상부로 향하도록 하는 회전부와, 상기한 회전부에서 뒷면이 상부로 향하도록 180°회전된 반도체 패키지의 뒷면에 마킹을 하는 마킹부와, 상기한 마킹부에서 마킹이 완료된 반도체 패키지를 트레이에 안착시키도록 상기한 트레이가 위치하는 트레이안착부로 구성할 수 있다. 즉, 픽엔플레이스 장비에 마킹부를 형성함으로써, 장비의 구성을 간단히 할 수 있다.An example of the equipment for marking by the above method is a pickup for picking up the semiconductor package cut on the wafer, and the semiconductor package picked up by the pick-up is rotated by 180 ° so that the back side thereof faces upward. The tray to mark the back of the semiconductor package rotated 180 ° so that the back side is turned upward from the rotor, and the tray to seat the semiconductor package marked by the marking on the tray. It can be configured as a tray mounting portion is located. That is, by forming the marking portion in the pick-and-place equipment, the configuration of the equipment can be simplified.

상기에 있어서, 트레이안착부는 양호한 반도체패키지가 안착되는 트레이와, 리워크가 필요한 반도체 패키지가 안착되는 트레이로 각각 구분된다.In the above, the tray mounting portion is divided into a tray on which a good semiconductor package is seated and a tray on which a semiconductor package requiring rework is seated.

이상의 설명에서 알 수 있듯이 본 발명의 반도체 패키지 제조를 위한 마킹방법에 의하면, 픽엔플레이스 장비에 마킹부를 형성함으로써, 반도체 패키지의 뒷면에 마킹하는 공정을 픽엔플레이스 공정에서 할 수 있음으로써, 제조공정을 단축시키고, 생산성을 향상시킬 수 있는 효과가 있다.As can be seen from the above description, according to the marking method for manufacturing a semiconductor package of the present invention, by forming a marking portion in the pick-and-place equipment, the marking process on the back side of the semiconductor package can be performed in the pick-and-place process, thereby shortening the manufacturing process. And the productivity can be improved.

Claims (4)

전자회로가 집적되어 있는 다수의 반도체칩이 형성된 웨이퍼를 제공하는 단계와,Providing a wafer having a plurality of semiconductor chips in which electronic circuits are integrated; 상기한 웨이퍼에 형성된 다수의 반도체칩에 대응하는 회로가 형성되어 있는 써킷테이프를 제공하는 단계와,Providing a circuit tape on which circuits corresponding to a plurality of semiconductor chips formed on the wafer are formed; 상기한 웨이퍼와 상기한 써킷테이프를 접착시키는 단계와,Adhering the wafer and the circuit tape to each other; 상기한 웨이퍼상에 형성된 반도체칩의 신호를 상기한 써킷테이프의 회로에 전달할 수 있도록 와이어로 연결하는 와이어본딩단계와,A wire bonding step of connecting the signal of the semiconductor chip formed on the wafer to the circuit so as to transfer the signal of the circuit tape; 상기한 와이어본딩단계에서 와이어로 본딩된 부분을 보호하도록 봉지재로 덮어씌우고, 이 봉지재를 경화시키는 인캡슐레이션단계와,An encapsulation step of covering the encapsulant to protect the portion bonded with the wire in the wire bonding step, and curing the encapsulant; 상기한 써킷테이프의 회로에 전달된 신호를 외부로 전달하도록 솔더볼을 범핑하는 솔더볼범핑단계와,Solder ball bumping step of bumping the solder ball to transfer the signal transmitted to the circuit of the circuit tape to the outside, 상기한 웨이퍼상의 스트리트 라인(Street Line)을 따라 다수의 반도체칩을 절단하여 반도체칩의 크기와 동일한 크기의 반도체 패키지를 형성하는 단계와,Cutting a plurality of semiconductor chips along the street line on the wafer to form a semiconductor package having the same size as that of the semiconductor chip; 상기한 웨이퍼상에서 절단된 반도체 패키지를 픽업한 후, 인스펙션(Inspection)하여 양호한 반도체 패키지와 리워크(Rework)가 필요한 반도체 패키지를 구분하고, 상기 양호한 반도체 패키지와 리워크가 필요한 반도체 패키지를 180°회전시킨 상태에서 마킹을 실시하며, 마킹이 완료된 양호한 반도체 패키지와 리워크가 필요한 반도체 패키지는 서로 다른 트레이에 각각 구분지어서 안착시키는 단계를After picking up the semiconductor package cut on the wafer, inspection is performed to distinguish between a good semiconductor package and a semiconductor package requiring rework, and rotate the good semiconductor package and the semiconductor package requiring rework by 180 °. Marking is carried out in a state in which the marking is completed, and the semiconductor package requiring rework and the semiconductor package requiring rework are separately placed in different trays and seated. 포함하여 이루어지는 것을 특징으로 하는 반도체 패키지 제조를 위한 마킹방법.Marking method for manufacturing a semiconductor package comprising a. 제 1 항에 있어서,The method of claim 1, 상기한 웨이퍼상에서 절단된 반도체 패키지를 픽업할 때에는 웨이퍼 맵 파일(Wafer Map File)에 의해 불량으로 판정된 반도체칩이 패키지화 된 반도체 패키지는 픽업하지 않고, 양호한 반도체칩이 패키지화 된 반도체 패키지 만을 선택하여 픽업하는 것을 특징으로 하는 반도체 패키지 제조를 위한 마킹방법.When picking up the semiconductor package cut out on the wafer, the semiconductor package in which the semiconductor chip is determined as defective by the wafer map file is not picked up, but only the semiconductor package in which the good semiconductor chip is packaged is selected. Marking method for manufacturing a semiconductor package, characterized in that. 전자회로가 집적되어 있는 다수의 반도체칩이 형성된 웨이퍼를 제공하는 단계와,Providing a wafer having a plurality of semiconductor chips in which electronic circuits are integrated; 상기한 웨이퍼에 형성된 다수의 반도체칩에 대응하는 회로가 형성되어 있는 써킷테이프를 제공하는 단계와,Providing a circuit tape on which circuits corresponding to a plurality of semiconductor chips formed on the wafer are formed; 상기한 웨이퍼와 상기한 써킷테이프를 접착시키는 단계와,Adhering the wafer and the circuit tape to each other; 상기한 웨이퍼상에 형성된 반도체칩의 신호를 상기한 써킷테이프의 회로에 전달할 수 있도록 와이어로 연결하는 와이어본딩단계와,A wire bonding step of connecting the signal of the semiconductor chip formed on the wafer to the circuit so as to transfer the signal of the circuit tape; 상기한 와이어본딩단계에서 와이어로 본딩된 부분을 보호하도록 봉지재로 덮어씌우고, 이 봉지재를 경화시키는 인캡슐레이션단계와,An encapsulation step of covering the encapsulant to protect the portion bonded with the wire in the wire bonding step, and curing the encapsulant; 상기한 써킷테이프의 회로에 전달된 신호를 외부로 전달하도록 솔더볼을 범핑하는 솔더볼범핑단계와,Solder ball bumping step of bumping the solder ball to transfer the signal transmitted to the circuit of the circuit tape to the outside, 상기한 웨이퍼상의 스트리트 라인(Street Line)을 따라 다수의 반도체칩을 절단하여 반도체칩의 크기와 동일한 크기의 반도체 패키지를 형성하는 단계와,Cutting a plurality of semiconductor chips along the street line on the wafer to form a semiconductor package having the same size as that of the semiconductor chip; 상기한 웨이퍼상에서 절단된 반도체 패키지를 픽업한 후, 인스펙션(Inspection)하여 양호한 반도체 패키지와 리워크(Rework)가 필요한 반도체 패키지를 구분하고, 상기 양호한 반도체 패키지와 리워크가 필요한 반도체 패키지를 180°회전시켜 서로 다른 트레이에 각각 구분지어서 안착시킨 후, 마킹을 실시하는 단계를After picking up the semiconductor package cut on the wafer, inspection is performed to distinguish between a good semiconductor package and a semiconductor package requiring rework, and rotate the good semiconductor package and the semiconductor package requiring rework by 180 °. After placing them separately in different trays, the marking is carried out. 포함하여 이루어지는 것을 특징으로 하는 반도체 패키지 제조를 위한 마킹방법.Marking method for manufacturing a semiconductor package comprising a. 제 3 항에 있어서,The method of claim 3, wherein 상기한 웨이퍼상에서 절단된 반도체 패키지를 픽업할 때에는 웨이퍼 맵 파일(Wafer Map File)에 의해 불량으로 판정된 반도체칩이 패키지화 된 반도체 패키지는 픽업하지 않고, 양호한 반도체칩이 패키지화 된 반도체 패키지 만을 선택하여 픽업하는 것을 특징으로 하는 반도체 패키지 제조를 위한 마킹방법.When picking up the semiconductor package cut out on the wafer, the semiconductor package in which the semiconductor chip is determined as defective by the wafer map file is not picked up, but only the semiconductor package in which the good semiconductor chip is packaged is selected. Marking method for manufacturing a semiconductor package, characterized in that.
KR10-1998-0035620A 1998-08-31 1998-08-31 Marking method for manufacturing semiconductor package KR100370844B1 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
KR10-1998-0035620A KR100370844B1 (en) 1998-08-31 1998-08-31 Marking method for manufacturing semiconductor package
JP11200832A JP3055104B2 (en) 1998-08-31 1999-07-14 Manufacturing method of semiconductor package
US09/385,694 US6589801B1 (en) 1998-08-31 1999-08-30 Wafer-scale production of chip-scale semiconductor packages using wafer mapping techniques

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR10-1998-0035620A KR100370844B1 (en) 1998-08-31 1998-08-31 Marking method for manufacturing semiconductor package

Publications (2)

Publication Number Publication Date
KR20000015594A true KR20000015594A (en) 2000-03-15
KR100370844B1 KR100370844B1 (en) 2003-07-07

Family

ID=19548971

Family Applications (1)

Application Number Title Priority Date Filing Date
KR10-1998-0035620A KR100370844B1 (en) 1998-08-31 1998-08-31 Marking method for manufacturing semiconductor package

Country Status (1)

Country Link
KR (1) KR100370844B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20150111222A (en) * 2014-03-25 2015-10-05 앰코 테크놀로지 코리아 주식회사 Manufacturing method of semiconductor device and semiconductor device thereof

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5713749A (en) * 1980-06-30 1982-01-23 Toshiba Corp Marking machine
JPS60193344A (en) * 1984-03-15 1985-10-01 Mitsubishi Electric Corp Removing device of foreign matter in package for semiconductor device
JP2725701B2 (en) * 1988-08-22 1998-03-11 松下電器産業株式会社 Electronic component mounting equipment
KR970004831B1 (en) * 1993-07-26 1997-04-04 아남산업 주식회사 Feeding of components in integrated circuit package
KR0115254Y1 (en) * 1994-07-28 1998-04-16 김주용 Marking device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20150111222A (en) * 2014-03-25 2015-10-05 앰코 테크놀로지 코리아 주식회사 Manufacturing method of semiconductor device and semiconductor device thereof

Also Published As

Publication number Publication date
KR100370844B1 (en) 2003-07-07

Similar Documents

Publication Publication Date Title
US6845554B2 (en) Method for connection of circuit units
US6737300B2 (en) Chip scale package and manufacturing method
US6537848B2 (en) Super thin/super thermal ball grid array package
US20010015009A1 (en) Method of fabricating semiconductor package
US6291270B1 (en) Revealing localized cutting line patterns in a semiconductor device
JP2005032910A (en) Method for manufacturing semiconductor device and semiconductor manufacturing device used therefor
US7087459B2 (en) Method for packaging a multi-chip module of a semiconductor device
US20090146299A1 (en) Semiconductor package and method thereof
CN107895703A (en) Multipurpose nonlinear semiconductor packaging body assembly line
US8445906B2 (en) Method for sorting and acquiring semiconductor element, method for producing semiconductor device, and semiconductor device
KR100370844B1 (en) Marking method for manufacturing semiconductor package
JP2002134651A (en) Baseless semiconductor device and its manufacturing method
US6772510B1 (en) Mapable tape apply for LOC and BOC packages
JPH11111650A (en) Manufacture of semiconductor device, and jig used thereof and semiconductor device
JP2001250834A (en) Method of manufacturing semiconductor device
KR100370840B1 (en) Adhesive method of wafer and circuit tape for manufacturing semiconductor package
US7015065B2 (en) Manufacturing method of ball grid array package
KR100379084B1 (en) Semiconductor Package Manufacturing Method
JPH10303151A (en) Manufacture of electronic parts
KR100379093B1 (en) Marking method of semiconductor package
KR100379087B1 (en) Semiconductor Package Manufacturing Method
US20230361045A1 (en) Semiconductor package and methods of manufacturing
US20230395443A1 (en) Semiconductor package and methods of manufacturing
KR100411812B1 (en) Manufacturing method of semiconductor package
KR100694425B1 (en) manufacturing method of semiconductor package

Legal Events

Date Code Title Description
A201 Request for examination
N231 Notification of change of applicant
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20130116

Year of fee payment: 11

FPAY Annual fee payment

Payment date: 20140121

Year of fee payment: 12

FPAY Annual fee payment

Payment date: 20150119

Year of fee payment: 13

FPAY Annual fee payment

Payment date: 20160120

Year of fee payment: 14

FPAY Annual fee payment

Payment date: 20170112

Year of fee payment: 15

FPAY Annual fee payment

Payment date: 20180108

Year of fee payment: 16

EXPY Expiration of term