KR20000013292A - Semiconductor memory device and method for fabricating thereof - Google Patents

Semiconductor memory device and method for fabricating thereof Download PDF

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Publication number
KR20000013292A
KR20000013292A KR1019980032058A KR19980032058A KR20000013292A KR 20000013292 A KR20000013292 A KR 20000013292A KR 1019980032058 A KR1019980032058 A KR 1019980032058A KR 19980032058 A KR19980032058 A KR 19980032058A KR 20000013292 A KR20000013292 A KR 20000013292A
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South Korea
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conductive plug
polysilicon pattern
etching
contact
forming
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KR1019980032058A
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Korean (ko)
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김용식
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윤종용
삼성전자 주식회사
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Priority to KR1019980032058A priority Critical patent/KR20000013292A/en
Publication of KR20000013292A publication Critical patent/KR20000013292A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration

Abstract

PURPOSE: A semiconductor memory device and method for fabricating thereof are provided to reduce chip area by connecting a gate electrode and an active region. CONSTITUTION: The method comprises the steps of: a polysilicon pattern is formed. An interlayer insulating layer is formed the whole surface of the polysilicon pattern. A contact is formed by etching the interlayer insulating layer until a part region of a semiconductor substrate contiguous to the polysilicon pattern is exposed using a photo and etching method. A conductive plug is formed by charging the contact with a predetermined conductive material. And a metal line layer is formed using the contact.

Description

반도체 메모리장치 및 그의 제조방법Semiconductor memory device and manufacturing method thereof

본 발명은 반도체 메모리장치에 관한 것으로서, 특히 소자의 미세화에 용이한 반도체 메모리장치 및 그의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device and a method of manufacturing the same, which are easy to miniaturize devices.

일반적으로 반도체 소자는, 설계특성상 트랜지스터의 게이트 전극과 반도체 기판의 활성영역을 연결하는 것이 많이 존재하게 되는데, 예를들어 씨모스 에스램(CMOS SRAM)의 경우 인버터 게이트의 출력단이 다음단의 입력 게이트로 설계되며, 이를 연결하기 위해 종래에는 활성영역과 게이트 전극 위에 따로 따로 접촉부(contact)을 형성하고 금속배선층과 연결하였다.In general, a semiconductor device has a lot of connections between a gate electrode of a transistor and an active region of a semiconductor substrate due to design characteristics. For example, in the case of CMOS SRAM, an output terminal of an inverter gate is an input gate of a next stage. In order to connect the same, conventionally, a contact is formed separately on the active region and the gate electrode and connected to the metallization layer.

그러나 상기와 같이 활성영역과 게이트 전극과의 연결을 위해 두 개의 접촉부를 형성하게 되면 칩면적을 감소시키기 어려운 문제점이 있다.However, when the two contact portions are formed to connect the active region and the gate electrode as described above, it is difficult to reduce the chip area.

따라서 본 발명의 목적은 상기와 같은 종래 기술의 문제점을 해결하기 위하여 한 개의 접촉부를 이용하여 인접한 게이트 전극과 활성영역을 연결함으로써 칩면적의 감소가 용이한 반도체 메모리장치를 제공하는 것이다.Accordingly, an object of the present invention is to provide a semiconductor memory device in which the chip area can be easily reduced by connecting an adjacent gate electrode and an active region by using one contact to solve the problems of the prior art.

본 발명의 다른 목적은 상기 반도체 메모리장치를 효율적으로 제조할 수 있는 제조방법을 제공하는 것이다.Another object of the present invention is to provide a manufacturing method capable of efficiently manufacturing the semiconductor memory device.

상기 목적을 달성하기 위한 본 발명의 반도체 메모리장치는, 다결정실리콘 패턴과, 상기 다결정실리콘 패턴 및 다결정실리콘 패턴에 인접한 반도체 기판의 일부영역과 동시에 접하도록 형성된 도전성 플러그와, 상기 도전성 플러그와 접하도록 형성된 금속배선층을 포함하여 구성된 것을 특징으로 한다.A semiconductor memory device of the present invention for achieving the above object is a polysilicon pattern, a conductive plug formed to be in contact with the polycrystalline silicon pattern and a partial region of the semiconductor substrate adjacent to the polycrystalline silicon pattern and formed to be in contact with the conductive plug Characterized in that it comprises a metal wiring layer.

상기 다른 목적을 달성하기 위한 본 발명의 반도체 메모리장치의 제조방법은, 반도체 기판상에 다결정실리콘 패턴을 형성하는 단계와, 상기 다결정실리콘 패턴이 형성되어 있는 결과물의 전면에 층간절연막을 형성하는 단계와, 상기 다결정실리콘 패턴 및 다결정실리콘 패턴에 인접한 반도체 기판의 일부영역이 동시에 노출되도록 사진 및 식각방법으로 상기 층간절연막을 식각하여 접촉부를 형성하는 단계와, 임의의 도전물질로 상기 접촉부를 충전시켜 도전성 플러그를 형성하는 단계, 및 상기 도전성 플러그와 접하는 금속배선층을 형성하는 단계를 포함하여 이루어지는 것을 특징으로 한다.According to another aspect of the present invention, there is provided a method of fabricating a semiconductor memory device, the method including: forming a polysilicon pattern on a semiconductor substrate, and forming an interlayer insulating film on the entire surface of the resultant product on which the polysilicon pattern is formed; Etching the interlayer insulating layer by a photo and etching method so as to simultaneously expose the polysilicon pattern and a partial region of the semiconductor substrate adjacent to the polysilicon pattern, and forming a contact portion, and filling the contact portion with an arbitrary conductive material to form a conductive plug And forming a metal wiring layer in contact with the conductive plug.

도 1 은 본 발명에 의한 반도체 메모리장치의 평면 구조를 도시한 것이고,1 illustrates a planar structure of a semiconductor memory device according to the present invention,

도 2a 내지 도 2d 는 본 발명에 의한 반도체 메모리장치의 제조방법에 따른 수직 단면 구조를 도시한 것들이다.2A to 2D illustrate vertical cross-sectional structures in accordance with a method of manufacturing a semiconductor memory device according to the present invention.

*도면의 주요 부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *

21 : 반도체 기판 22 : 필드산화막21 semiconductor substrate 22 field oxide film

23 : 게이트 전극 24 : 층간절연막23 gate electrode 24 interlayer insulating film

25 : 도전성 플러그 26 : 금속배선층25 conductive plug 26 metal wiring layer

이하, 첨부한 도면을 참조하여 본 발명을 상세하게 설명하고자 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

본 발명의 반도체 메모리장치는, 도 1 에 도시한 바와 같이 게이트 전극(14) 및 이 게이트 전극과 인접한 활성영역(13)의 일부영역을 한 개의 접촉부(15)로 동시에 열리게 한 것이다.(도면우측)In the semiconductor memory device of the present invention, as shown in Fig. 1, the gate electrode 14 and a partial region of the active region 13 adjacent to the gate electrode are simultaneously opened by one contact portion 15. (Fig. Right side) )

도 2a 내지 도 2d를 참조하여 제조방법을 설명하면, 먼저 도 2a 에서는 반도체 기판(21)을 국부적으로 열산화시켜 활성영역과 비활성영역을 정의하기 위한 필드산화막(23)을 형성하고, 다결정실리콘을 침적한 후 패터닝하여 게이트 전극(23)을 형성한다.Referring to FIGS. 2A to 2D, first, in FIG. 2A, the semiconductor substrate 21 is locally thermally oxidized to form a field oxide layer 23 for defining an active region and an inactive region, and polysilicon is formed. After deposition, the gate electrode 23 is formed by patterning.

이어서 도 2b 에서는, 상기 게이트 전극(23)이 형성되어 있는 구조물의 전면에 절연물질을 소정의 두께로 증착시켜 층간절연막(24)을 형성한 후 평탄화시키고, 계속하여 상기 게이트 전극(23)의 일부영역과 게이트 전극(23)에 인접한 반도체 기판(21)의 일부영역이 동시에 노출되도록 상기 층간절연막(24)을 식각하여 접촉부를 형성한다. 이때 상기 층간절연막(24)을 식각하기 위해서는 사진 및 식각방법을 이용한다.Subsequently, in FIG. 2B, an insulating material is deposited on the entire surface of the structure on which the gate electrode 23 is formed to form an interlayer insulating film 24, and then planarized, and then a part of the gate electrode 23 is continued. The interlayer insulating layer 24 is etched to form a contact portion so that a region and a partial region of the semiconductor substrate 21 adjacent to the gate electrode 23 are simultaneously exposed. In this case, a photo and an etching method are used to etch the interlayer insulating layer 24.

이어서 도 2c 에서는, 상기 층간절연막(24) 형성 후 그 결과물의 전면에 Al, Cu,W와 같은 금속물질로 상기 접촉부가 충전되도록 상기 금속물질 중 어느 하나를 CVD(chemical vapor deposition) 또는 PVD(plasma vapor deposition) 방법으로 침적하고, 계속하여 상기 침적된 금속물질을 전면식각하여 도전성 플러그(25)를 형성한다. 이때 상기 침적된 도전물질의 전면식각방법으로는 건식식각이나 CMP (chemical mechanical polishing)을 이용한다.Subsequently, in FIG. 2C, any one of the metal materials is CVD (chemical vapor deposition) or PVD (plasma) so that the contact portion is filled with a metal material such as Al, Cu, and W on the front surface of the resultant after the interlayer insulating film 24 is formed. The deposition is carried out by a vapor deposition method, and then the deposited metal material is completely etched to form the conductive plug 25. In this case, dry etching or chemical mechanical polishing (CMP) may be used as a front etching method of the deposited conductive material.

이어서 도 2d 에서는, 상기 도전성 플러그(25) 형성 후 그 결과물의 전면에 다시 금속물질을 침적한 후 사진 및 식각방법을 이용하여 상기 침적된 금속물질을 선택적으로 식각함으로써 금속배선층(26)을 형성한다.Subsequently, in FIG. 2D, after the conductive plug 25 is formed, the metal material is deposited on the entire surface of the resultant material, and then the metal material layer 26 is formed by selectively etching the deposited metal material using a photograph and an etching method. .

이상에서와 같이 본 발명에 의하면, 한 개의 접촉부를 이용하여 인접한 게이트 전극과 활성영역을 연결함으로써 칩면적을 효율적으로 감소시킬 수 있는 효과가 있다.As described above, according to the present invention, there is an effect that the chip area can be efficiently reduced by connecting the adjacent gate electrode and the active region using one contact portion.

Claims (8)

다결정실리콘 패턴과, 상기 다결정실리콘 패턴 및 다결정실리콘 패턴에 인접한 반도체 기판의 일부영역과 동시에 접하도록 형성된 도전성 플러그와, 상기 도전성 플러그와 접하도록 형성된 금속배선층을 포함하여 구성된 것을 특징으로 하는 반도체 메모리장치.And a polysilicon pattern, a conductive plug formed in contact with the polysilicon pattern and a portion of the semiconductor substrate adjacent to the polycrystalline silicon pattern, and a metal wiring layer formed in contact with the conductive plug. 제 1 항에 있어서, 상기 도전성 플러그는 Al, Cu 및 W 중 어느 하나로 구성된 것임을 특징으로 하는 반도체 메모리장치.The semiconductor memory device of claim 1, wherein the conductive plug is made of one of Al, Cu, and W. 3. 반도체 기판상에 다결정실리콘 패턴을 형성하는 단계와, 상기 다결정실리콘 패턴이 형성되어 있는 결과물의 전면에 층간절연막을 형성하는 단계와, 상기 다결정실리콘 패턴 및 다결정실리콘 패턴에 인접한 반도체 기판의 일부영역이 동시에 노출되도록 사진 및 식각방법으로 상기 층간절연막을 식각하여 접촉부를 형성하는 단계와, 임의의 도전물질로 상기 접촉부를 충전시켜 도전성 플러그를 형성하는 단계, 및 상기 도전성 플러그와 접하는 금속배선층을 형성하는 단계를 포함하여 이루어지는 것을 특징으로 하는 반도체 메모리장치의 제조방법.Forming a polysilicon pattern on the semiconductor substrate, forming an interlayer insulating film on the entire surface of the product on which the polysilicon pattern is formed, and a portion of the semiconductor substrate adjacent to the polysilicon pattern and the polysilicon pattern at the same time Etching the interlayer insulating film by a photo and etching method so as to be exposed to form a contact portion, filling the contact portion with an arbitrary conductive material to form a conductive plug, and forming a metal wiring layer in contact with the conductive plug. A method of manufacturing a semiconductor memory device, comprising: 제 3 항에 있어서, 상기 도전성 플러그를 형성하는 단계는 상기 접촉부 형성 후 그 결과물의 전면에 도전물질을 소정의 두께로 증착시키는 단계와, 상기 증착된 도전물질을 전면식각하는 단계를 포함하여 이루어지는 것을 특징으로 하는 반도체 메모리장치의 제조방법.The method of claim 3, wherein the forming of the conductive plug comprises depositing a conductive material to a predetermined thickness on the entire surface of the resultant after forming the contact portion, and etching the entire surface of the deposited conductive material. A method of manufacturing a semiconductor memory device. 제 4 항에 있어서, 상기 도전성 플러그를 형성하기 위한 도전물질을 증착시키는 단계는 CVD에 의하여 이루어지는 것을 특징으로 하는 반도체 메모리장치의 제조방법.The method of claim 4, wherein the depositing a conductive material for forming the conductive plug is performed by CVD. 제 4 항에 있어서, 상기 도전성 플러그를 형성하기 위한 도전물질을 증착시키는 단계는 PVD에 의하여 이루어지는 것을 특징으로 하는 반도체 메모리장치의 제조방법.The method of claim 4, wherein the depositing a conductive material for forming the conductive plug is performed by PVD. 제 4 항에 있어서, 상기 도전성 플러그를 형성하기 위하여 증착된 도전물질을 전면식각하는 단계는 건식식각에 의하여 이루어지는 것을 특징으로 하는 반도체 메모리장치의 제조방법.The method of claim 4, wherein the etching of the entire surface of the conductive material deposited to form the conductive plug is performed by dry etching. 제 4 항에 있어서, 상기 도전성 플러그를 형성하기 위하여 증착된 도전물질을 전면식각하는 단계는 CMP에 의하여 이루어지는 것을 특징으로 하는 반도체 메모리장치의 제조방법.The method of claim 4, wherein the etching of the entire surface of the conductive material deposited to form the conductive plug is performed by CMP.
KR1019980032058A 1998-08-06 1998-08-06 Semiconductor memory device and method for fabricating thereof KR20000013292A (en)

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