KR20000009092A - Inter metal dielectric film of semiconductor device and its fabrication method - Google Patents
Inter metal dielectric film of semiconductor device and its fabrication method Download PDFInfo
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- KR20000009092A KR20000009092A KR1019980029283A KR19980029283A KR20000009092A KR 20000009092 A KR20000009092 A KR 20000009092A KR 1019980029283 A KR1019980029283 A KR 1019980029283A KR 19980029283 A KR19980029283 A KR 19980029283A KR 20000009092 A KR20000009092 A KR 20000009092A
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- 239000002184 metal Substances 0.000 title claims abstract description 53
- 238000000034 method Methods 0.000 title claims abstract description 29
- 239000004065 semiconductor Substances 0.000 title claims abstract description 22
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 11
- 238000005229 chemical vapour deposition Methods 0.000 claims abstract description 12
- 239000011800 void material Substances 0.000 claims abstract description 7
- 239000000758 substrate Substances 0.000 claims description 8
- 238000005498 polishing Methods 0.000 claims description 2
- 239000000126 substance Substances 0.000 claims description 2
- 239000012861 aquazol Substances 0.000 claims 3
- 229920006187 aquazol Polymers 0.000 claims 3
- BPQQTUXANYXVAA-UHFFFAOYSA-N Orthosilicate Chemical compound [O-][Si]([O-])([O-])[O-] BPQQTUXANYXVAA-UHFFFAOYSA-N 0.000 abstract description 5
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 abstract description 4
- 239000011248 coating agent Substances 0.000 abstract description 4
- 238000000576 coating method Methods 0.000 abstract description 4
- 239000011521 glass Substances 0.000 abstract description 4
- 238000010521 absorption reaction Methods 0.000 description 6
- 239000010410 layer Substances 0.000 description 4
- 230000001186 cumulative effect Effects 0.000 description 3
- 238000009413 insulation Methods 0.000 description 2
- 238000005336 cracking Methods 0.000 description 1
- 125000001495 ethyl group Chemical group [H]C([H])([H])C([H])([H])* 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76819—Smoothing of the dielectric
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02282—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
본 발명은 반도체 장치의 금속간 절연(Inter Metal Dielectric; IMD)막 및 그 제조 방법에 관한 것으로서, 특히 CVD(Chemical Vapour Deposition)법을 사용하여 형성된 반도체 장치의 금속 배선간 절연막 및 그 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an intermetal dielectric (IMD) film of a semiconductor device and a method of manufacturing the same. will be.
반도체 소자의 제조 기술이 점차 고 집적화되고 있으며, 또한 빠른 속도가 요구됨에 따라 금속 배선 구조에 있어서도 기존의 단일 금속 배선 구조에서 이중 금속 배선 구조 또는 다층 금속 배선 구조로 점점 그 사용 폭이 넓어지고 있다. 그리고 이와 같은 이중 금속 배선 구조 또는 다층 금속 배선 구조에서 금속 배선막 사이의 층간 절연막을 형성하는 방법으로서, 도포율이 빠르고 도포막의 특성 등의 조절이 용이한 CVD 방식을 주로 이용한다.As the manufacturing technology of semiconductor devices is becoming increasingly integrated and high speed is required, the use range of the metal wiring structure from the existing single metal wiring structure to the double metal wiring structure or the multilayer metal wiring structure is gradually increasing. As a method of forming an interlayer insulating film between metal wiring films in such a double metal wiring structure or a multi-layered metal wiring structure, a CVD method which has a high coating rate and easy adjustment of characteristics of the coating film is mainly used.
도 1은 종래의 반도체 장치, 예컨대 DRAM(Dynamic Random Access Memory)의 금속 배선간 절연막을 개략적으로 나타내 보인 단면도이다.1 is a cross-sectional view schematically showing an insulating film between metal interconnects of a conventional semiconductor device, for example, a DRAM (Dynamic Random Access Memory).
도 1을 참조하면, 반도체 기판(1) 상에 제1 금속막 패턴(2)이 형성되어 있다. 제1 금속막 패턴(2) 상에는 버퍼층으로서 PEOX(Plasma Enhanced OXide)막(3)이 소정 두께, 예컨대 1100Å의 두께로 형성되며, PEOX막(3) 상에는 O3-TEOS(O3-Tetra Ethyl Ortho Silicate)막(4)이 일정 두께, 예컨대 6300Å의 두께로 형성된다. 그리고, O3-TEOS막(4)의 상부 표면 부분에 형성된 보이드(void)에는 SOG(Silicate On Glass)막(5)으로 채워져 있으며, 에치백 또는 평탄화 공정이 수행된 O3-TEOS막(4) 및 SOG막(5)의 표면상에는 PEOX막(6)이 소정 두께, 예컨대 4000Å의 두께로 형성되어 있다. 제2 금속막 패턴(7)은 PEOX막(5) 및 O3-TEOS막(4) 사이의 컨택홀을 통하여 제1 금속막 패턴(2)과 컨택되어 있다.Referring to FIG. 1, a first metal film pattern 2 is formed on a semiconductor substrate 1. A PEOX (Plasma Enhanced OXide) film 3 is formed on the first metal film pattern 2 as a buffer layer at a predetermined thickness, for example, 1100 μs, and on the PEOX film 3, O 3 -TEOS (O 3 -Tetra Ethyl Ortho). Silicate film 4 is formed to a predetermined thickness, for example, 6300 mm 3. A void formed on the upper surface portion of the O 3 -TEOS film 4 is filled with a SOG (Silicate On Glass) film 5, and an O 3 -TEOS film 4 subjected to an etch back or planarization process 4. ) And the SOG film 5 are formed on the surface of the SOG film 5 with a predetermined thickness, for example, a thickness of 4000 kPa. The second metal film pattern 7 is in contact with the first metal film pattern 2 through a contact hole between the PEOX film 5 and the O 3 -TEOS film 4.
그런데, 이와 같은 구조의 금속 배선간 절연막은 다음과 같은 문제점이 있다.However, the inter-wire insulating film of such a structure has the following problems.
즉, 후속 공정인 열공정을 수행하는 도중에, 제1 금속막 패턴(2)과 O3-TEOS막(4)에서의 열팽창 계수의 차로 인하여 두 막 간에 스트레스의 불균형이 발생하고, 이로 인하여 O3-TEOS막(4)에 크랙(crack)이 발생한다. 따라서, 이를 방지하고 O3-TEOS막(4)의 하지막 의존도를 낮추기 위하여, 제1 금속막 패턴(2)과 O3-TEOS막(4) 사이에 PEOX막(3)을 형성한다. 그러나, PEOX막(3)은 스트레스의 흡수율이 낮은 특성을 갖고 있다. 이에 반하여, PEOX막(3) 상에 CVD법을 사용하여 형성된 O3-TEOS막(4)은 스트레스의 장력이 높은 특성을 갖고 있다. 따라서, 제1 금속막 패턴(2)과 O3-TEOSX막(4) 사이의 스트레스 불균형이 여전히 발생하고, 이로 인하여 O3-TEOS막(4)에는 크랙이 발생된다.In other words, during the subsequent step of performing a thermal process, the first metal layer pattern (2) and O 3 -TEOS film 4, the variation in the stress between the two films due to the thermal expansion coefficient of the drive occurs, and because of this in the O 3 A crack occurs in the TEOS film 4. Therefore, to prevent this and to form the O 3 -TEOS film 4, the first metal layer pattern (2) and O 3 -TEOS film 4 PEOX film 3 between not to reduce the dependency of the film. However, the PEOX film 3 has a characteristic of low stress absorption rate. In contrast, the O 3 -TEOS film 4 formed on the PEOX film 3 by the CVD method has a high stress tension. Therefore, the stress imbalance between the first metal film pattern 2 and the O 3 -TEOSX film 4 still occurs, which causes cracks in the O 3 -TEOS film 4.
본 발명의 목적은 CVD법을 사용하여 제1 금속막 패턴 상에 형성되는 O3-TEOS막에 크랙이 발생하지 않도록 하는 반도체 장치의 금속 배선간 절연막을 제공하는 것이다.SUMMARY OF THE INVENTION An object of the present invention is to provide an inter-wire insulating film of a semiconductor device in which cracks do not occur in the O 3 -TEOS film formed on the first metal film pattern by using the CVD method.
본 발명의 다른 목적은 상기 금속 배선간 절연막의 제조 방법을 제공하는 것이다.Another object of the present invention is to provide a method for producing the intermetallic insulating film.
도 1은 종래의 반도체 장치의 금속 배선간 절연막을 개략적으로 나타내 보인 단면도이다.1 is a cross-sectional view schematically showing an insulating film between metal wirings of a conventional semiconductor device.
도 2는 본 발명에 따른 반도체 장치의 금속 배선간 절연막을 개략적으로 나타내 보인 단면도이다.2 is a cross-sectional view schematically showing an insulating film between metal wirings of a semiconductor device according to the present invention.
도 3 내지 도 6은 본 발명에 따른 반도체 장치의 금속 배선간 절연막의 제조 방법을 설명하기 위한 단면도들이다.3 to 6 are cross-sectional views illustrating a method of manufacturing an inter-wire insulating film of a semiconductor device according to the present invention.
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>
100...반도체 기판 110...제1 금속막 패턴100 ... semiconductor substrate 110 ... first metal film pattern
120...PTEOS막 130...O3-TEOS막120 ... PTEOS film 130 ... O 3 -TEOS film
140...SOG막 150...PEOX막140 ... SOG film 150 ... PEOX film
160...제2 금속막 패턴160 ... second metal film pattern
상기 목적을 달성하기 위하여, 본 발명에 따른 반도체 장치의 금속 배선간 절연막은, 반도체 기판 상에 형성된 제1 금속막과 상기 제1 금속막과 컨택된 제2 금속막 사이에 CVD법을 사용하여 형성된 금속 배선간 절연막에 있어서, 상기 제1 금속막과 상기 제2 금속막 사이에 PTEOS막, O3-TEOS막 및 PEOX막이 순차적으로 형성된 것을 특징으로 한다.In order to achieve the above object, the inter-wire insulating film of the semiconductor device according to the present invention is formed using a CVD method between a first metal film formed on a semiconductor substrate and a second metal film contacted with the first metal film. The inter-wire insulating film, wherein the PTEOS film, the O 3 -TEOS film and the PEOX film are sequentially formed between the first metal film and the second metal film.
여기서, 상기 PTEOS막의 두께는 2500Å이고, 상기 O3-TEOS막의 두께는 5000Å이고, 그리고 상기 PEOX막의 두께는 4000Å인 것이 바람직하다. 그리고 상기 O3-TEOS막에 형성된 보이드에는 SOG막이 채워진다.The thickness of the PTEOS film is 2500 kPa, the thickness of the O 3 -TEOS film is 5000 kPa, and the thickness of the PEOX film is 4000 kPa. The SOG film is filled in the void formed in the O 3 -TEOS film.
상기 다른 목적을 달성하기 위하여, 본 발명에 따른 반도체 장치의 금속 배선간 절연막의 제조 방법은, 반도체 기판 상에 형성되는 제1 및 제2 금속막 패턴 사이의 금속 배선간 절연막의 제조 방법에 있어서, 상기 제1 금속막 패턴 상에 PTEOS막을 도포하는 단계; CVD법을 사용하여 상기 PTEOS막 상에 O3-TEOS막을 도포하는 단계; 상기 O3-TEOS막에 형성된 보이드에 SOG막을 형성하는 단계; 상기 O3-TEOS막 및 SOG막의 일정 표면이 노출되도록 에치백 공정을 수행하는 단계; 및 상기 O3-TEOS막 및 SOG막의 노출 표면상에 PEOX막을 형성하는 단계를 포함하는 것을 특징으로 한다.MEANS TO SOLVE THE PROBLEM In order to achieve the said another objective, the manufacturing method of the inter-wire insulation film of the semiconductor device which concerns on this invention is a manufacturing method of the inter-wire insulation film between the 1st and 2nd metal film pattern formed on a semiconductor substrate, Applying a PTEOS film on the first metal film pattern; Applying an O 3 -TEOS film on the PTEOS film using a CVD method; Forming an SOG film on the void formed on the O 3 -TEOS film; Performing an etch back process to expose a predetermined surface of the O 3 -TEOS film and the SOG film; And forming a PEOX film on the exposed surfaces of the O 3 -TEOS film and the SOG film.
이하, 첨부 도면을 참조하여 본 발명의 바람직한 실시예를 상세히 설명하기로 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 2는 본 발명에 따른 반도체 장치의 금속 배선간 절연막을 개략적으로 나타내 보인 단면도이다.2 is a cross-sectional view schematically showing an insulating film between metal wirings of a semiconductor device according to the present invention.
도 2를 참조하면, 본 발명에 따른 금속 배선간 절연막은, 반도체 기판(100) 상에 형성된 제1 금속막 패턴(110)과 비어 홀(via hole)을 통해 제1 금속막 패턴과 컨택되는 제2 금속막 패턴(160) 사이에 형성된다. 즉, 제1 및 제2 금속막 패턴(110)(160) 사이에 PTEOS막(120), O3-TEOS막(130) 및 PEOX막(140)이 순차적으로 형성된다.Referring to FIG. 2, the inter-wire insulating film according to the present invention may be formed by contacting the first metal film pattern through a via hole and a first metal film pattern 110 formed on the semiconductor substrate 100. It is formed between the two metal film patterns 160. That is, the PTEOS film 120, the O 3 -TEOS film 130, and the PEOX film 140 are sequentially formed between the first and second metal film patterns 110 and 160.
PTEOS막(120)은 상부막인 O3-TEOS막(130)의 하지막 의존성을 낮추므로 CVD법을 사용하여 형성되는 O3-TEOS막(130)의 보이드를 줄여준다. 그리고, PTEOS막(120)의 두께를 2500Å으로 종래의 1100Å에 비하여 약 두 배 이상 증가시킴으로써, 상부막인 O3-TEOS막(130)의 두께를 줄일 수 있고, 이로 인하여 전체 공정 시간을 단축시킬 수 있다. 즉, PTEOS막(120)의 두께를 증가시킴으로 인하여 늘어나는 시간보다 O3-TEOS막(130)의 두께를 감소시킴으로 인하여 단축되는 시간이 길기 때문에 전체 공정을 수행하는데 소요되는 시간은 짧아진다. 또한, PTEOS막(120)은 스트레스 흡수율이 높으므로 CVD 공정을 사용하여 형성되는 O3-TEOS막(130)에서의 크랙 발생이 억제된다.The PTEOS film 120 lowers the dependence of the underlying film of the O 3 -TEOS film 130 as the upper film, thereby reducing the void of the O 3 -TEOS film 130 formed by using the CVD method. In addition, by increasing the thickness of the PTEOS film 120 to about 2500 kW or more than the conventional 1100 kW, the thickness of the upper film O 3 -TEOS film 130 can be reduced, thereby reducing the overall process time. Can be. In other words, the time required to perform the entire process is shortened because the time shortened by reducing the thickness of the O 3 -TEOS film 130 is longer than the time due to increasing the thickness of the PTEOS film 120. In addition, since the PTEOS film 120 has a high stress absorption rate, crack generation in the O 3 -TEOS film 130 formed using the CVD process is suppressed.
O3-TEOS막(130)은 CVD법을 사용하여 형성되며, 두께는 5000Å로 앞서 설명한 바와 같이 종래의 6300Å에 비하여 현저하게 줄어들므로, 도포 시간이 단축된다. 그리고, 하지막인 PTEOS막(120)의 스트레스 흡수율이 높으므로 제1 금속막 패턴(110)과의 열팽창 계수의 차이에 의해 발생되는 스트레스 불균형의 영향을 덜 받고, 이에 따라 크랙이 거의 존재하지 않게 된다.The O 3 -TEOS film 130 is formed using the CVD method, and the thickness is 5000 mW, which is significantly reduced compared to the conventional 6300 mW as described above, so that the application time is shortened. In addition, since the stress absorption rate of the PTEOS film 120, which is the underlying film, is high, the stress imbalance caused by the difference in the thermal expansion coefficient with the first metal film pattern 110 is less affected by the stress imbalance. do.
한편, O3-TEOS막(130)에 형성된 보이드에는 SOG막(140)에 의해 채워지고, O3-TEOS막(130) 및 SOG막(140) 상에는 4000Å 두께의 PEOX막(150)이 형성된다.On the other hand, the void formed in the O 3 -TEOS film 130 is filled with the SOG film 140, and a 4000 OX thick PEOX film 150 is formed on the O 3 -TEOS film 130 and the SOG film 140. .
아래의 표 1은 종래의 금속 배선간 절연막과 본 발명에 따른 금속 배선간 절연막 사이의 생산성(%), 발생한 크랙수(개/chip), 누적 스트레스 및 O3-TEOS막의 습식 식각율(Å/분)을 비교하기 위한 표이다.Table 1 below shows the productivity (%), cracks (chips), cumulative stress, and wet etch rate of the O 3 -TEOS film between the conventional inter-wire insulating film and the inter-metal insulating film according to the present invention. Table) for comparison.
위 표 1에서, 종래 기술은 제1 절연막 패턴 상에 1100Å 두께의 PEOX막, 6300Å 두께의 O3-TEOS막 및 4000Å 두께의 PEOX막이 순차적으로 형성되어 이루어진 금속 배선간 절연막을 나타내고, 본 발명은 제1 절연막 패턴 상에 2500Å 두께의 PTEOS막, 5000Å 두께의 O3-TEOS막 및 4000Å 두께의 PEOX막이 순차적으로 형성되어 이루어진 금속 배선간 절연막을 나타낸다.In Table 1 above, the prior art shows a metal inter-wire insulating film formed by sequentially forming a PEOX film of 1100 Å thick, a O 3 -TEOS film of 6300 Å thick and a PEOX film of 4000 Å thick on the first insulating film pattern, the present invention An intermetallic insulating film formed by sequentially forming a 2500-kV PTEOS film, a 5000-kV O 3 -TEOS film, and a 4000-kW PEOX film on one insulating film pattern.
표 1에 나타낸 바와 같이, 본 발명에 따른 금속 배선간 절연막은 생산성이 1.6배 높아졌고, 크랙수 및 누적 스트레스가 현저하게 작아졌으며, 그리고 O3-TEOS막의 습식 식각율도 증가되었다.As shown in Table 1, the inter-wire insulating film according to the present invention had a 1.6 times higher productivity, a significantly smaller crack number and cumulative stress, and an increased wet etch rate of the O 3 -TEOS film.
도 3 내지 도 6은 본 발명에 따른 반도체 장치의 금속 배선간 절연막의 제조 방법을 설명하기 위한 단면도들이다.3 to 6 are cross-sectional views illustrating a method of manufacturing an inter-wire insulating film of a semiconductor device according to the present invention.
먼저, 도 3을 참조하면, 반도체 기판(100) 상에 형성된 제1 금속막 패턴(110)이 덮여지도록 소정 두께, 예컨대 2500Å의 두께를 갖는 PTEOS막(120)을 도포한다. PTEOS막(120)은 스트레스 흡수율이 높은 막으로서 버퍼층의 역할을 한다. 다음에, 도 4에 도시된 바와 같이, PTEOS막(120) 상에 O3-TEOS막(130)을 CVD법을 사용하여 도포한다. 이 때 O3-TEOS막(130)은 스트레스 흡수율이 높은 PTEOS막(120) 상에 형성되므로 제1 금속막 패턴(110) 사이의 스트레스 불균형이 완화되어 크랙의 발생이 억제되고, 보이드가 작게 형성된다.First, referring to FIG. 3, a PTEOS film 120 having a predetermined thickness, for example, a thickness of 2500 μs is coated to cover the first metal film pattern 110 formed on the semiconductor substrate 100. The PTEOS film 120 serves as a buffer layer as a film having a high stress absorption rate. Next, as shown in FIG. 4, the O 3 -TEOS film 130 is applied onto the PTEOS film 120 using the CVD method. At this time, since the O 3 -TEOS film 130 is formed on the PTEOS film 120 having a high stress absorption rate, the stress imbalance between the first metal film patterns 110 is alleviated, so that occurrence of cracks is suppressed and voids are formed small. do.
이와 같이, O3-TEOS막(130)을 형성한 후에는, 도 5에 도시된 바와 같이, 보이드 내에 SOG막(140)을 도포한다. 그리고, O3-TEOS막(130) 및 SOG막(140)의 일정 표면이 노출되도록 에치백 공정을 수행하여 O3-TEOS막(130)의 두께가 5000Å이 되도록 한다. 즉, 도 5의 점선으로 나타낸 부분까지 식각되도록 한다. 이 때, 에치백 공정 대신에 평탄화 공정을 수행할 수도 있으며, 평탄화 공정을 수행하는 경우에는 화학 기계적 폴리싱(Chemical Mechanical Polishing)법을 사용하는 것이 바람직하다.As described above, after the O 3 -TEOS film 130 is formed, the SOG film 140 is coated in the voids as shown in FIG. 5. Then, an etch back process is performed to expose a predetermined surface of the O 3 -TEOS film 130 and the SOG film 140 so that the thickness of the O 3 -TEOS film 130 is 5000 kPa. That is, the portion is etched to the portion indicated by the dotted line in FIG. 5. In this case, the planarization process may be performed instead of the etch back process, and in the case of performing the planarization process, it is preferable to use a chemical mechanical polishing method.
다음에는, 도 6에 도시된 바와 같이, O3-TEOS막(130) 및 SOG막(140)의 노출 표면상에 PEOX막(150)을 예컨대 4000Å의 두께로 형성한다. 그러면, 본 발명에 따른 금속 배선간 절연막이 완성된다.Next, as shown in FIG. 6, a PEOX film 150 is formed on the exposed surfaces of the O 3 -TEOS film 130 and the SOG film 140 to a thickness of, for example, 4000 kPa. Then, the inter-wire insulating film according to the present invention is completed.
한편, 제1 절연막 패턴(110) 상에 PTEOS막(120), O3-TEOS막(130) 및 PEOX막(150)을 포함하는 절연막을 형성한 후에는, 비어 홀을 형성한다. 그리고, 그 비어 홀을 통하여 제2 금속막 패턴(160)을 제1 금속막 패턴(110)과 컨택되도록 형성하면 도 2에 도시된 바와 같은 이중 금속 배선 구조가 완성된다.Meanwhile, after forming an insulating film including the PTEOS film 120, the O 3 -TEOS film 130, and the PEOX film 150 on the first insulating film pattern 110, a via hole is formed. When the second metal film pattern 160 is formed to contact the first metal film pattern 110 through the via hole, a double metal wiring structure as shown in FIG. 2 is completed.
이상, 본 발명을 바람직한 실시예를 들어 상세하게 설명하였으나, 본 발명은 상기 실시예에 한정되지 않으며, 본 발명의 기술적 사상의 범위 내에서 당 분야에서 통상의 지식을 가진 자에 의하여 여러 가지 변형이 가능하다.In the above, the present invention has been described in detail with reference to preferred embodiments, but the present invention is not limited to the above embodiments, and various modifications may be made by those skilled in the art within the scope of the technical idea of the present invention. It is possible.
이상의 설명에서와 같이, 본 발명에 따른 반도체 장치의 금속 배선간 절연막 및 그 제조 방법에 의하면, 제1 금속막 패턴과 O3-TEOS막 사이에 스트레스 흡수율이 높은 PTEOS막을 형성함으로써 제1 금속막 패턴과 O3-TEOS막 사이의 스트레스 불균형으로 인한 크랙 발생이 적어지며, 또한 PTEOS막의 두께를 증가시키고 O3-TEOS막의 두께를 감소시킴으로써 전체적인 공정 시간이 단축된다.As described above, according to the inter-wire insulating film of the semiconductor device and the manufacturing method thereof according to the present invention, the first metal film pattern by forming a PTEOS film with high stress absorption between the first metal film pattern and the O 3 -TEOS film Less cracking due to stress imbalance between the and O 3 -TEOS film, and also shorten the overall process time by increasing the thickness of the PTEOS film and reducing the thickness of the O 3 -TEOS film.
Claims (7)
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