KR20000009078A - Stopping layer etching method for fabricating semiconductor device - Google Patents
Stopping layer etching method for fabricating semiconductor device Download PDFInfo
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- KR20000009078A KR20000009078A KR1019980029261A KR19980029261A KR20000009078A KR 20000009078 A KR20000009078 A KR 20000009078A KR 1019980029261 A KR1019980029261 A KR 1019980029261A KR 19980029261 A KR19980029261 A KR 19980029261A KR 20000009078 A KR20000009078 A KR 20000009078A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31127—Etching organic layers
- H01L21/31133—Etching organic layers by chemical means
- H01L21/31138—Etching organic layers by chemical means by dry-etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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Abstract
Description
본 발명은 반도체 소자의 제조방법에 관한 것으로, 특히 반도체 소자의 제조를 위한 스탑핑 레이어 식각방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of etching a stopping layer for manufacturing a semiconductor device.
반도체 디바이스가 고집적화 고성능화 됨에 따라 새로운 형태의 칩이 개발 및 제조되고 있다. 예컨대 최근에 개발되고 있는 칩들중의 하나로서 디램(DRAM)과 로직(Logic)이 하나로 합쳐진 엠디엘(MDL:Merged DRAM Logic)디바이스가 그것이다. 그렇지만, 기존에 분리되어 인쇄회로기판에 각기 장착됨에 따라 발생되던 문제점을 해소하고 두 소자의 장점만을 한데 모은 상기 엠디엘 디바이스를 제조하는 제조공정은 더욱 복잡해지고 어려워지고 있는 실정이다. 그러한 엠디엘 디바이스 또는 통상의 반도체 메모리 디바이스내에 모오스 트랜지스터를 제조하는 경우에 일정한 목적을 위하여 고용융점 및 고내열성을 가지는 금속 예컨대, 티타늄, 코발트, 텡스텐 등의 금속이온을 실리콘이온과 결합시킨 금속 실리사이드 층을 도전층으로서 만들 수 있다. 상기 금속 실리사이드는 저저항 도전 물질로서 기능한다. 즉, 반도체 장치가 고집적화, 고성능화 및 저전압화됨에 따라, 미세 패턴 형성을 통한 트랜지스터 및 메모리 셀에서의 게이트 길이의 감소 및 소자 특성의 향상을 만족시키는 저저항 도전 물질이 필요한 것이다. 또한, 면 저항과 접촉 저항을 감소시킬 수 있는 물질로서 기능한다. 즉, 상기한 트랜지스터의 게이트 길이의 감소로 인한 쇼트-채널 효과(short channel effect)의 방지 및 펀치스루우(punchthrough)에 대한 마진 확보를 위하여, 소오스/드레인 영역의 접합 깊이(junction depth)를 얕게 형성하면서 동시에 소오스/드레인 영역의 기생 저항, 예컨대 면 저항(sheet resistance) 및 콘택 저항을 감소시키는 물질이 요구되는 것이다. 그러므로, 게이트 전극 및 소오스/드레인 영역의 표면에 실리사이드(silicide)층을 형성함으로써 게이트 전극의 비저항 및 소오스/드레인 영역의 면 저항과 접촉 저항을 감소시킬 수 있는 살리사이드 공정에 대한 연구가 활발히 진행되고 있다. 살리사이드 공정이란, 게이트 전극 및 소오스/드레인 영역에만 선택적으로 티타늄 실리사이드(TiSix) 등의 실리사이드층을 형성하는 방법이다.As semiconductor devices become highly integrated and high performance, new types of chips are being developed and manufactured. For example, one of the chips being developed recently is a merged DRAM logic (MDL) device in which a DRAM and a logic are combined into one. However, the manufacturing process of manufacturing the MD device, which solves the problems caused by the conventional separation and mounting on the printed circuit board, and combines only the advantages of the two devices, becomes more complicated and difficult. Metal silicide in which metal ions such as titanium, cobalt and tungsten are combined with silicon ions, such as titanium, cobalt, and tungsten, for the purpose of manufacturing a MOS transistor in such an MD device or a conventional semiconductor memory device. The layer can be made as a conductive layer. The metal silicide functions as a low resistance conductive material. In other words, as semiconductor devices become more integrated, higher in performance, and lower in voltage, a low resistance conductive material that satisfies the reduction of gate length and improvement of device characteristics in transistors and memory cells through fine pattern formation is required. It also functions as a material capable of reducing surface resistance and contact resistance. That is, the junction depth of the source / drain regions is shallow to prevent short channel effects due to the reduction of the gate length of the transistor and to secure a margin for punchthrough. What is needed is a material that forms while simultaneously reducing the parasitic resistance of the source / drain regions, such as sheet resistance and contact resistance. Therefore, studies on the salicide process that can reduce the specific resistance of the gate electrode and the surface resistance and contact resistance of the source / drain regions by forming a silicide layer on the surfaces of the gate electrode and the source / drain regions, have. The salicide process is a method of selectively forming a silicide layer such as titanium silicide (TiSix) only in the gate electrode and the source / drain regions.
스태틱 랜덤 억세스 메모리 (SRAM) 또는 비메모리인 알파-CHIP등과 같은 마이크로 프로세서의 메탈콘택 MC나 NC공정은 다음과 같은 이유로 스탑핑 레이어로서 SiON을 사용한다. 첫째는, 살리사이드가 형성된 액티브 영역과 콘택 오버랩 마진이 없어 미스 얼라인이 발생하면 기판 실리콘 쪽에 피팅이 발생하게 된다. 이러한 미스 얼라인을 개선하기 위하여 스탑핑 레이어를 사용하여 산화막질을 모두 에치하고 SiON위에 스탑핑시키면 미스 얼라인 마진이 확보된다. 둘째, 액티브와 게이트 단차가 3000Å차이가 있기 때문에 액티브 콘택을 비오픈이 없도록 오버 에칭하면 게이트 폴리위에 형성된 살리사이드 막질의 소모가 많아져 콘택저항이 나빠질 수 있다. 그러므로 스탑핑 레이어를 살리사이드 막위에 데포지션하여 살리사이드 막질에 대한 선택비를 높이면 충분히 오버 에치를 하여도 살리사이드 막질의 로스가 적고, 액티브 영역에 미스얼라인이 발생하여도 문제가 되지 않는다. 이러한 이유로 스탑핑레이어를 사용하는데 현재까지는 ICP설비에서 C2F6와 CH3F가스를 사용하여 SiON위에서 스탑핑 시키고 에싱/스트립을 하고 설비를 바꾸어 스탑핑 레이어를 제거하는 비교적 복잡한 공정을 사용해 왔다Metal contact MC or NC processes in microprocessors, such as static random access memory (SRAM) or non-memory alpha-CHIP, use SiON as a stopping layer for the following reasons: First, if there is no contact overlap margin with the active region where salicide is formed, a misalignment causes fitting to the substrate silicon side. In order to improve the misalignment, a misalignment margin is secured by etching all the oxides using a stopping layer and stopping over the SiON. Second, because the difference between the active and gate steps is 3000 Å, over-etching the active contact so that there is no opening can increase the consumption of the salicide film formed on the gate poly, resulting in poor contact resistance. Therefore, if the stopping layer is deposited on the salicide film to increase the selectivity to the salicide film quality, even if it is sufficiently overetched, the loss of the salicide film quality is low and there is no problem even if a misalignment occurs in the active region. For this reason, a stopping layer is used. Until now, ICP facilities have used a relatively complex process of using C2F6 and CH3F gas to stop on the SiON, ashing / striping and changing the equipment to remove the stopping layer.
따라서, 종래에는 스탑핑 레이어를 제거하는 공정들이 복잡하게 됨에 따라 반도체 소자의 제조특성이 저하되고 비용이 상승되는 문제점이 있었다.Therefore, conventionally, as the processes for removing the stopping layer become complicated, there is a problem in that manufacturing characteristics of the semiconductor device are lowered and the cost is increased.
따라서, 본 발명의 목적은 상기한 종래의 문제점을 해소할 수 있는 개선된 식각방법을 제공함에 있다.Accordingly, it is an object of the present invention to provide an improved etching method that can solve the above-mentioned problems.
본 발명의 다른 목적은 비교적 간단한 공정스텝으로 스탑핑 레이어를 제거하는 방법을 제공함에 있다.Another object of the present invention is to provide a method for removing a stopping layer in a relatively simple process step.
상기한 목적을 달성하기 위하여, 본 발명에서는 DRM설비에서 카아본 가스인 C4F8/CO와 Ar가스를 조합하여 SiON에 대한 선택비를 향상시켜서 SiON막질위에서 스탑핑시킨 후, 인시츄로 그 스탑핑된 SiON을 제거하는 것을 특징으로 한다.In order to achieve the above object, in the present invention, by combining C4F8 / CO, which is a carbon gas, and Ar gas in a DRM facility, the selectivity to SiON is improved to be stopped on the SiON film, and then stopped in situ. It is characterized by removing SiON.
본 발명의 타의 목적 및 이점은 첨부도면과 함께 설명되는 하기 설명에 의해 명확하게 나타날 것이다.Other objects and advantages of the invention will be apparent from the following description taken in conjunction with the accompanying drawings.
도 1 내지 도 5는 본 발명의 일실시예에 따른 스탑핑 레이어 식각의 제조수순을 보인 단면도들1 to 5 are cross-sectional views showing a manufacturing procedure of the stopping layer etching according to an embodiment of the present invention
이하에서, 스탑핑 레이어를 형성 및 제거하는 개선된 방법에 대한 본 발명의 바람직한 실시예가 상세히 설명된다.In the following, a preferred embodiment of the present invention for an improved method of forming and removing a stopping layer is described in detail.
먼저, 통상적인 콘택 에치시 살리사이드가 형성된 액티브 영역과 콘택 오버랩 마진이 없어 미스 얼라인이 발생하면 기판 실리콘 쪽에 피팅이 발생하게 된다. 이러한 미스 얼라인을 개선하고 오버에칭 마진을 확보하기 위하여 본 발명에서는 스탑핑 레이어인 SiON막질의 선택비를 높이는데 중요한 카아본 가스인 C4F8과 CO를 이용하여 고선택적으로 에칭을 한다.First, when there is no contact overlap margin with an active region in which a typical contact etch salicide is formed and a contact overlap margin occurs, fitting occurs on the substrate silicon side. In order to improve such misalignment and to secure an overetching margin, the present invention performs high selective etching using carbon4 gas, C4F8 and CO, which are important for increasing the selectivity of the SiON film quality as the stopping layer.
도 1과 같이 살리사이드 1가 형성된 액티브 영역과 게이트 폴리 11위에 스탑핑 레이어인 SiON막질 2을 500-1000Å의 두께로 데포하고 그 위에 산화막 3를 데포한다. 층간절연막으로서의 산화막 3이 데포된 결과물에 감광막 4을 사용하여 포토 패터닝을 도 2와 같이 수행한 뒤 메딜 플라즈마 덴시티 설비인 DRM설비에서 카아본을 많이 함유하고 있는 C4F8과 CO가스를 사용하여 상기 절연막 3을 고선택적으로 에칭을 한다. 여기서, CO가스를 너무 많이 사용하면 마이크로 로딩이 발생하기 때문에 아르곤 가스나 산소가스를 첨가하여 SiON막 2위에서 스탑핑 시키는데 그 결과가 도 3에 보여진다. 스탑핑된 SiON막 2에 대하여는 에싱/스트립을 하지 않고 CF4가스를 사용하여 인시츄 에칭하는 것이 바람직하다. 도 4에는 이 결과가 나타나 있다.As shown in FIG. 1, the SiON film 2, which is a stopping layer, is deposited on the active region where the salicide 1 is formed and the gate poly 11 to a thickness of 500-1000 kPa, and the oxide film 3 is deposited thereon. Photo patterning was carried out using the photoresist film 4 as a result of the deposition of the oxide film 3 as an interlayer insulating film as shown in FIG. 2, and then the insulating film was formed using C4F8 and CO gas containing a lot of carbon in the DRM facility, which is a medi plasma density facility. Etch 3 is highly selective. In this case, when too much CO gas is used, micro loading occurs, so that argon gas or oxygen gas is added to stop on the SiON film, and the result is shown in FIG. 3. The stopped SiON film 2 is preferably in-situ etched using CF4 gas without ashing / striping. This result is shown in FIG.
위와 같은 스킴으로 에치를 행하여 에싱/스트립을 하면 도 5와 같은 프로파일을 확보할 수 있다.Etching and stripping by the above scheme can ensure a profile as shown in FIG.
전술된 바와 같이 본 발명의 실시예는 도면을 참조하여 예를들어 설명되었지만, 사안이 허용하는 범위에서 다양한 변화와 변경이 가능함은 물론이다.As described above, the embodiment of the present invention has been described by way of example with reference to the drawings, but various changes and modifications can be made within the scope allowed by the matter.
상기한 본 발명에 따르면, 반도체 소자의 제조시에 간단한 공정스텝으로 스탑핑 레이어를 제거하는 효과가 있다.According to the present invention described above, there is an effect of removing the stopping layer in a simple process step in the manufacture of the semiconductor device.
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| Application Number | Priority Date | Filing Date | Title |
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| KR1019980029261A KR20000009078A (en) | 1998-07-21 | 1998-07-21 | Stopping layer etching method for fabricating semiconductor device |
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| KR1019980029261A KR20000009078A (en) | 1998-07-21 | 1998-07-21 | Stopping layer etching method for fabricating semiconductor device |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100907883B1 (en) * | 2002-12-30 | 2009-07-14 | 동부일렉트로닉스 주식회사 | Method of forming a contact of a semiconductor device |
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1998
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100907883B1 (en) * | 2002-12-30 | 2009-07-14 | 동부일렉트로닉스 주식회사 | Method of forming a contact of a semiconductor device |
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