KR20000008991A - Method for fabricating liquid crystal display - Google Patents
Method for fabricating liquid crystal display Download PDFInfo
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- KR20000008991A KR20000008991A KR1019980029127A KR19980029127A KR20000008991A KR 20000008991 A KR20000008991 A KR 20000008991A KR 1019980029127 A KR1019980029127 A KR 1019980029127A KR 19980029127 A KR19980029127 A KR 19980029127A KR 20000008991 A KR20000008991 A KR 20000008991A
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- film
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- 238000000034 method Methods 0.000 title claims abstract description 22
- 239000004973 liquid crystal related substance Substances 0.000 title description 6
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 48
- 238000005530 etching Methods 0.000 claims abstract description 4
- 239000002184 metal Substances 0.000 claims 1
- 239000011248 coating agent Substances 0.000 abstract 1
- 238000000576 coating method Methods 0.000 abstract 1
- 239000010408 film Substances 0.000 description 35
- 239000000758 substrate Substances 0.000 description 6
- 229910021417 amorphous silicon Inorganic materials 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 238000000206 photolithography Methods 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000012528 membrane Substances 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 1
- 239000011147 inorganic material Substances 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/13625—Patterning using multi-mask exposure
Abstract
Description
본 발명은 휴대형 정보통신기기, 게임기나 시뮬레이션기기 등에 이용되는 액정표시장치에 관련된 것으로써, 특히, 액정표시장치의 일방의 기판 위에 게이트버스라인, 데이터버스라인, 박막트랜지스터(Thin Film Transistor:TFT) 및 화소전극 등의 구조물 패턴을 형성하는 과정에 있어서, 그 패턴막에 단차가 형성되어 있을 때 단차부의 노광불균일을 해소하여 포토레지스트가 균일한 두께로 현상되도록 하는 방법에 관련된 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device used for a portable information communication device, a game machine, a simulation device, and the like, and in particular, a gate bus line, a data bus line, and a thin film transistor (TFT) on one substrate of the liquid crystal display device. And in the process of forming the structure pattern of the pixel electrode or the like, when the step is formed in the pattern film, the exposure unevenness of the step portion is eliminated so that the photoresist is developed to a uniform thickness.
상기 액정표시장치의 기판의 구조물에 있어서, 예컨데 도 1 및 도 2에서와 같이 화소전극(109a)은 인접하는 2개의 게이트버스라인(70)과 인접하는 2개의 데이터버스라인(60)이 교차하여 만드는 매트릭스 부분에 각각 배치되도록 형성된다.In the structure of the substrate of the liquid crystal display device, for example, as shown in FIGS. 1 and 2, the pixel electrode 109a crosses two adjacent gate bus lines 70 and two adjacent data bus lines 60. It is formed to be disposed on each of the matrix portion to be made.
상기 게이트버스라인(60)에서 분기하는 게이트전극(60a)과, 상기 데이터버스라인(70)에서 분기하는 소스전극(70a)은 a-Si층(80a) 및 n+이온이 도핑된 a-Si층(80b)로 이루어진 반도체층(80)을 개재하여 일부가 서로 중첩되고, 상기 소스전극(60a)과 같은 층에서 상기 소스전극과 일정한 간격을 두고 대향 배치됨과 아울러 상기 반도체층(80)을 개재하여 상기 게이트전극(70a)과 서로 일부가 중첩되는 드레인전극(60b)이 형성된다.The gate electrode 60a branching from the gate bus line 60 and the source electrode 70a branching from the data bus line 70 are a-Si layer 80a and a-Si doped with n + ions. A portion overlaps with each other through the semiconductor layer 80 formed of the layer 80b, and is disposed to face the source electrode at a predetermined distance from the same layer as the source electrode 60a and interpose the semiconductor layer 80 therebetween. As a result, a drain electrode 60b overlapping with the gate electrode 70a is formed.
상기와 같이 게이트전극(70a), 반도체층(80), 소스전극(60a) 및 드레인전극(60b)이 형성됨으로써, 상기 게이트버스라인(70)과 상기 데이터버스라인(60)의 전기적 신호에 의하여 구동되는 TFT가 형성되고, 그 TFT의 출력단자(드레인전극)는 화소전극(109a)과 접촉되도록 형성된다. 또, 화소전극의 용량을 보조하는 보조용량전극(35)이 절연막을 개재하여 게이트버스라인(70)의 일부와 중첩되도록 형성된다.As described above, the gate electrode 70a, the semiconductor layer 80, the source electrode 60a, and the drain electrode 60b are formed, and thus, by the electrical signals of the gate bus line 70 and the data bus line 60. A TFT to be driven is formed, and the output terminal (drain electrode) of the TFT is formed in contact with the pixel electrode 109a. In addition, the storage capacitor electrode 35 that assists the capacitance of the pixel electrode is formed to overlap with a portion of the gate bus line 70 through the insulating film.
한편, 게이트버스라인(70) 및 데이터버스라인(60)의 단부에는 구동드라이버(IC)의 단자와 접촉되는 게이트패드(170)와, 데이터패드(160)가 형성된다.Meanwhile, gate pads 170 and data pads 160 contacting terminals of the driving driver IC are formed at ends of the gate bus line 70 and the data bus line 60.
상기 TFT와 화소전극 등은 미세패턴으로 기판위에 구성되기 때문에 그 작업과정이 매우 복잡하고, 특히 각각의 패턴을 형성하는 과정에서 포토리소그래피 공정을 거치게 된다.Since the TFT and the pixel electrode are formed on the substrate in a fine pattern, the operation process is very complicated, and in particular, the photolithography process is performed in the process of forming each pattern.
상기 각각의 포토리소그래피 공정은 포토레지스트를 소망하는 패턴에 따라 경화시키기 위하여 반드시 마스크가 필요하고, 그 마스크를 이용하여 노광 한 후에는 경화되지 않은 포토레지스트 부분을 제거하기 위하여 현상하고, 현상된 패턴에 따라 하층에 형성된 막을 에칭하는 과정 등이 필요하다.Each photolithography process requires a mask to cure the photoresist in accordance with a desired pattern, and after exposure using the mask, it is developed to remove the uncured photoresist portion, and then to the developed pattern. Accordingly, a process of etching the film formed in the lower layer is required.
상기 포토리소그래피 공정을 본 발명에서는 마스크공정이라 약칭하는바, 특히 단차가 형성되어 있는 막 위에서 마스크공정을 진행하여 단차형성부에 포토레지스트가 남도록 현상하는 경우에 단차부의 노광불균일로 인하여 현상된 포토레지스트의 두께가 불균일하게 된다.The photolithography process is abbreviated as a mask process in the present invention. In particular, when the mask process is performed on a film on which a step is formed, the photoresist is developed due to uneven exposure of the stepped part. The thickness of becomes uneven.
상기 단차가 형성된 막 위에서 포토레지스트의 노광불균일이 일어나는 과정을 이하에 설명한다.A process in which exposure unevenness of the photoresist occurs on the film on which the step is formed will be described below.
도 3a와 같이 단차가 형성된 막(143)위에, 포토레지스트(600)를 도포하고, 마스크(500)를 위치 맞춤한 후 노광한다. 예컨데 포지형의 포토레지스트를 사용할 경우에는 UV광이 마스크의 글래스판(500b)를 통과하여 포토레지스트에 닿는 부분은 포토레지스트가 현상액에 녹도록 변화되고, UV광이 마스크의 라인엔드스패이스 Cr패턴(500a)에 의하여 차단되는 부분은 현상액에 불용성인 상태로 남아 있게 된다.The photoresist 600 is coated on the stepped film 143 as shown in FIG. 3A, the mask 500 is positioned, and then exposed. For example, in the case of using a positive photoresist, the portion where UV light passes through the glass plate 500b of the mask and touches the photoresist is changed so that the photoresist is melted in the developer, and the UV light is changed into the line end space Cr pattern of the mask. The part blocked by 500a) remains insoluble in the developer.
즉, 마스크(500)의 패턴에 따라 포토레지스트(600)가 현상액에 불용성인 부분은 (600b)이고, 포토레지스트가 현상액에 녹는 부분은 (600a)가 된다.That is, according to the pattern of the mask 500, the portion in which the photoresist 600 is insoluble in the developer is (600b), and the portion in which the photoresist is dissolved in the developer is (600a).
그런데, 도 3a의 구조에 있어서는 막의 단차부에 소정의 두께만큼 포토레지스트가 남도록 하기 위하여 UV광이 일부만 통과하는 라인엔드스패이스 패턴을 갖는 마스크를 이용하였기 때문에 그 라인엔드스패이스 패턴부에서는 포토레지스트의 일부만 현상액에 녹게 된다.However, in the structure of FIG. 3A, a mask having a line end space pattern through which only part of UV light passes is used to leave the photoresist at a predetermined thickness in the stepped portion of the film. Therefore, only a part of the photoresist is used in the line end space pattern portion. It is dissolved in the developer.
상기와 같은 노광과정을 거친후 현상액으로 포토레지스트(600)를 현상하면 도 3b와 같이 단차부에서 두께가 다른 포토레지스트의 패턴(600a)이 형성된다.When the photoresist 600 is developed with the developer after the exposure process as described above, a pattern 600a of photoresist having a different thickness is formed in the stepped portion as shown in FIG. 3B.
상기 포토레지스트 패턴(600b)의 두께 불균일 원인은 종래의 도 4의 평면 구조와 같이 라인엔드스패이스 패턴을 구성하였기 때문에 라인엔드스패이스 패턴의 전영역을 같은 해상도로 통과한 UV광이 막의 단차부의 거리 차이로 인하여 국부적으로 다른 강도로 회절하여 조사되기 때문이다. 상기 도 4에서 C1,C2의 실선은 막(143)의 단차위치를 나타낸다.The reason for the thickness non-uniformity of the photoresist pattern 600b is that the line end space pattern is configured as in the conventional planar structure of FIG. This is because it is irradiated by diffraction locally at different intensities. In FIG. 4, the solid lines C1 and C2 represent the stepped positions of the film 143.
상기 두께가 다른 포토레지스트의 패턴(600b)을 이용하여 단차진 막(143)을 드라이에칭 등의 방법으로 식각하면 도 3c와 같이 막(143)의 단차부 C1,C2부에서 막의 단선이 발생하거나 원하지 않는 모양으로 패턴이 형성되는 문제점이 발생한다.When the stepped film 143 is etched by dry etching using the pattern 600b of the photoresist having a different thickness, disconnection of the film may occur at the stepped portions C1 and C2 of the film 143 as shown in FIG. 3C. The problem arises that the pattern is formed in an undesirable shape.
본 발명은 단차가 형성된 막 위에서 단차부에 포토레지스트가 일정한 두께만큼 균일하게 남았도록 현상하여 원하는 패턴 모양으로 상기 막을 식각하기 위한 것으로써, 라인엔드스패이스 패턴을 노광기의 해상도보다 작은 해상도를 갖는 패턴으로 형성하고, 특히 단차부 C1,C2에 위치하는 라인엔드스패이스 패턴의 영역(제1영역)은 다른 라인엔드스패이스 패턴 영역(제2영역)에 비하여 해상도를 더 작게 한다.The present invention is to etch the film in a desired pattern shape by developing so that the photoresist remains uniformly by a predetermined thickness on the stepped film on the stepped film, and the line end space pattern is formed into a pattern having a resolution smaller than that of the exposure machine. In particular, the area (first area) of the line end space pattern located at the stepped portions C1 and C2 has a smaller resolution than the other line end space pattern area (second area).
즉, 단차부 C1,C2에 위치하는 라인엔드스패이스 패턴의 영역은 다른 라인엔드스패이스 패턴 영역에 비하여 UV광이 통과하는 량이 더 작도록 예컨데 도 5a 및 도 5b 구조의 라인엔드스패이스 패턴을 갖도록 한다.That is, the area of the line end space pattern located in the stepped portions C1 and C2 has a line end space pattern of FIGS. 5A and 5B so that the amount of UV light passes is smaller than that of other line end space pattern areas.
상기와 같이 라인엔드스패이스 패턴을 구성함으로써, 조사되는 UV광을 적절히 조절하여 단차부에 현상되는 포토레지스트의 패턴 두께를 조절하고, 단차부가 원하는 패턴모양으로 식각되도록 한다.By configuring the line end space pattern as described above, by adjusting the UV light to be irradiated appropriately to adjust the pattern thickness of the photoresist developed on the stepped portion, the stepped portion is etched to the desired pattern shape.
따라서, 본 발명의 목적은 개량된 라인엔드스패이스 패턴을 이용하여 포토레지스트의 패턴 두께를 임의로 조절함으로써, 막이 원하는 모양으로 식각되도록 하는 것에 있다.Accordingly, it is an object of the present invention to arbitrarily adjust the pattern thickness of a photoresist using an improved line end space pattern so that the film is etched into a desired shape.
본 발명의 또 다른 목적은 막의 단차특성을 개선하는 것에 있다.Another object of the present invention is to improve the step characteristic of the membrane.
도 1은 일반적인 액정표시장치의 기판의 평면도이고,1 is a plan view of a substrate of a general liquid crystal display device;
도 2는 도 1의 A-A´선을 따라 절단하여 나타내는 제조공정 단면도이고,FIG. 2 is a cross-sectional view of the manufacturing process taken along a line A-A ′ of FIG. 1;
도 3a∼도 3c는 종래의 라인엔드스패이스 패턴을 갖는 마스크를 이용하여 단차진 막을 패터닝하는 과정을 설명하기 위한 단면도이고,3A to 3C are cross-sectional views illustrating a process of patterning a stepped film using a mask having a conventional line end space pattern.
도 4는 종래의 라인엔드스패이스 패턴을 갖는 마스크의 평면도이고,4 is a plan view of a mask having a conventional line end space pattern,
도 5a,도 5b는 본 발명의 라인엔드스패이스 패턴을 갖는 마스크의 평면도이고,5A and 5B are plan views of a mask having a line end space pattern of the present invention,
도 6a∼도 6c는 본 발명의 라인엔드스패이스 패턴을 갖는 마스크를 이용하여 단차진 막을 패터닝하는 과정을 설명하기 위한 단면도이다.6A to 6C are cross-sectional views illustrating a process of patterning a stepped film using a mask having a line end space pattern of the present invention.
*도면의 주요 부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *
35 - 보조용량전극. 55 - 게이트절연막.35-auxiliary capacitance electrode. 55-gate insulating film.
60 - 데이터버스라인. 60a - 소스전극.60-data bus line. 60a-source electrode.
60b - 드레인전극. 70 - 게이트버스라인.60b-drain electrode. 70-Gate Bus Line.
70a - 게이트전극. 80 - 반도체층.70a-gate electrode. 80-semiconductor layer.
80a - a-Si층. 80b - n+이온이 도핑된 a-Si층.80a-a-Si layer. 80b-a-Si layer doped with n + ions.
100 - 투명기판. 143 - 단차가 형성된 막.100-transparent substrate. 143-membrane with stepped.
155 - 보호막. 160 - 데이터패드.155-Shield. 160-Data Pad.
170 - 게이트패드. 190a - 화소전극.170-gate pad. 190a-pixel electrode.
190b - 게이트패드의 보호ITO막.190b-ITO film on the gate pad.
500 - 마스크. 500a - 마스크의 라인엔드스패이스 Cr패턴.500-mask. 500a-Line End Space Cr pattern of the mask.
500b - 마스크의 글래스판.500b-the glass plate of the mask.
600 - 포토레지스트.600-photoresist.
본 발명은 상기 목적을 달성하기 위하여 단차(C1,C2)가 형성된 막 위에 포토레지스트(600)를 도포하고, 적어도 제1영역과 제2영역으로 구분하여 해상도의 차가 있는 라인엔드스패이스 패턴을 1개이상 구비한 마스크(500)를 이용하여 상기 막의 단차부(C1,C2)에 위치하는 포토레지스트의 패턴(600b) 두께가 대략 균일하게 현상되도록 하고, 상기 현상된 포토레지스트의 패턴 형상으로 상기 막을 식각한다.In order to achieve the above object, the present invention applies a photoresist 600 on a film on which the steps C1 and C2 are formed, and at least one line end space pattern having a difference in resolution by dividing it into at least a first region and a second region. The thickness of the pattern 600b of the photoresist positioned at the stepped portions C1 and C2 of the film is developed to be substantially uniform using the mask 500 provided above, and the film is etched in the pattern shape of the developed photoresist. do.
이하 본 발명의 액정표시장치의 기판의 제조과정에 대하여 첨부된 도면을 참고하여 상세히 설명한다.Hereinafter, a manufacturing process of the substrate of the liquid crystal display device of the present invention will be described in detail with reference to the accompanying drawings.
도 6a와 같이 단차가 형성된 적어도 1층 이상의 막(무기물 또는 유기물로 형성됨:143)위에, 포토레지스트(600)를 도포하고, 도 5a,도 5b와 같이 막의 단차부 C1,C2 부분은 다른 부분에 비하여 UV광이 적게 투과하도록 슬릿형 또는 모자이크상으로 라인엔드스패이스 패턴이 구비된 마스크(500)를 위치 맞춤한 후 노광한다. 예컨데 포지형의 포토레지스트를 사용하면 마스크(500)의 패턴에 따라 포토레지스트(600)가 현상액에 불용성인 부분은 (600a)가 되고, 포토레지스트가 현상액에 녹는 부분은 (600b)가 된다.A photoresist 600 is applied on at least one layer (at least one layer formed of inorganic or organic material) formed with a step as shown in FIG. 6A, and the stepped portions C1 and C2 of the film may be formed at different portions as shown in FIGS. 5A and 5B. In comparison, the mask 500 having the line-end space pattern is positioned and exposed in a slit or mosaic form so as to transmit less UV light. For example, when a positive photoresist is used, a portion of the photoresist 600 that is insoluble in the developer according to the pattern of the mask 500 becomes (600a), and a portion of the photoresist that melts in the developer becomes (600b).
상기 단차부(C1,C2)는 다른 부분보다 해상도가 작은 라인엔드스패이스 패턴부를 이용하여 노광하므로 단차부에서 UV광의 회절에 의한 노광불균일이 조정되고, 상기 노광불균일을 조정함으로써 막의 단차부에서 포토레지스트의 패턴(600b)은 대략 균일한 두께로 형성된다.Since the stepped portions C1 and C2 are exposed using a line end space pattern portion having a smaller resolution than other portions, the exposure unevenness due to diffraction of UV light is adjusted at the stepped portion, and the photoresist at the stepped portion of the film is adjusted by adjusting the exposure unevenness. The pattern 600b is formed to have a substantially uniform thickness.
상기와 같은 노광과정을 거친후 현상액으로 포토레지스트(600)를 현상하면 현상액에 녹는 (600a)부분은 제거되고 도 6b와 같이 단차부에서 두께가 같은 포토레지스트의 패턴(600b)이 형성된다.When the photoresist 600 is developed with the developer after the exposure process as described above, the portion 600a dissolved in the developer is removed, and a pattern 600b of photoresist having the same thickness is formed at the stepped portion as shown in FIG. 6B.
상기 포토레지스트의 패턴(600b)을 이용하여 단차진 막(143)을 드라이에칭 등의 방법으로 식각하면 도 6c와 같이 포토레지스트의 패턴(600b)과 같은 모양으로 막의 패턴이 형성된다.When the stepped film 143 is etched by dry etching using the pattern 600b of the photoresist, the pattern of the film is formed in the same shape as the pattern 600b of the photoresist as shown in FIG. 6C.
상기 단차가 형성된 막(143)과 포토레지스트의 패턴(600b)이 에칭선택비가 비슷할 경우에는 상기 포토레지스트의 패턴(600b) 표면과 노출된 막(143)의 표면이 동시에 식각되므로 에칭가스에 의하여 상기 포토레지스트의 패턴이 모두 제거된 후에도 상기 포토레지스트의 패턴 형상을 따라 상기 막이 식각되는 것은 자명하다.When the step etched film 143 and the pattern 600b of the photoresist have similar etching selectivity, the surface of the pattern 600b of the photoresist and the surface of the exposed film 143 are etched at the same time. It is apparent that the film is etched along the pattern shape of the photoresist even after all the patterns of the photoresist are removed.
따라서, 본 발명은 단차가 형성된 막의 C1,C2 부분에서 단선이 발생되지 않고, 기술자가 의도하는 패턴이 형성된다. 상기 단차부는 표현상 직각으로 표시하였지만, 라인엔드스패이스 패턴의 제1영역과 제2영의 경계부의 해상도가 순차변화하도록 패턴을 형성할 경우에는 단차부가 곡면형상으로 형성되어 막의 단차특성이 개선된다.Therefore, in the present invention, disconnection does not occur in the C1 and C2 portions of the film on which the step is formed, and a pattern intended by a technician is formed. Although the stepped portion is represented at right angles in the representation, when the pattern is formed such that the resolution of the boundary between the first region and the second zero of the line end space pattern is sequentially changed, the stepped portion is curved to improve the stepped characteristic of the film.
본 발명은 상기와 같이 막의 단차부에 포토레지스트의 패턴을 균일하게 형성함으로써, 막의 단차부의 단선을 방지하고, 기술자기 의도하는 막의 패턴모양을 형성할 수 있는 효과가 있다.The present invention has the effect of uniformly forming the pattern of the photoresist on the stepped portion of the film as described above, thereby preventing the disconnection of the stepped portion of the film and forming a pattern shape of a film intended by a technician.
또한, 마스크의 라인엔드스패이스 패턴을 복수개의 해상도를 갖는 영역으로 분할 함으로써 막의 단차특성을 개선하는 효과가 있다.In addition, by dividing the line end space pattern of the mask into a plurality of resolution areas, there is an effect of improving the step characteristic of the film.
Claims (5)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980029127A KR20000008991A (en) | 1998-07-20 | 1998-07-20 | Method for fabricating liquid crystal display |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980029127A KR20000008991A (en) | 1998-07-20 | 1998-07-20 | Method for fabricating liquid crystal display |
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| Publication Number | Publication Date |
|---|---|
| KR20000008991A true KR20000008991A (en) | 2000-02-15 |
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| KR1019980029127A KR20000008991A (en) | 1998-07-20 | 1998-07-20 | Method for fabricating liquid crystal display |
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| KR (1) | KR20000008991A (en) |
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1998
- 1998-07-20 KR KR1019980029127A patent/KR20000008991A/en not_active Application Discontinuation
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