CN117529158A - Display panel and manufacturing method thereof - Google Patents

Abstract

The embodiment of the application discloses a display panel and a manufacturing method thereof, wherein the display panel comprises the following components: a substrate; the active layer is arranged on the substrate and comprises a plurality of semiconductor parts and a plurality of cushion layer parts; a first insulating layer disposed on the plurality of pad portions; the first electrode layer is arranged on the first insulating layer, and comprises a plurality of first electrodes which are overlapped with the corresponding cushion layer parts in the thickness direction of the display panel. Compared with the prior art, the precision and the uniformity of the first electrode are improved.

Description

Display panel and manufacturing method thereof

Technical Field

The present disclosure relates to the field of display, and in particular, to a display panel and a method for manufacturing the same.

Background

Display panels have been widely used in people's lives, such as display screens of mobile phones, computers, and the like. With the rapid development of the display panel industry, people have put demands on the display panel in addition to the demands on the display panel such as high resolution, wide viewing angle, low power consumption, etc.

However, in the prior art, in the manufacturing process of the display panel, there is still a problem that the manufacturing accuracy and uniformity of the electrode such as the pixel electrode are poor due to the thicker photoresist layer.

Disclosure of Invention

The embodiment of the application provides a display panel, which can solve the problem that the manufacturing accuracy and uniformity of electrodes such as pixel electrodes are poor due to thicker photoresist layers in the manufacturing process of the display panel.

The embodiment of the application provides a display panel, which comprises:

a substrate;

an active layer disposed on the substrate, the active layer including a plurality of semiconductor portions and a plurality of pad portions;

a first insulating layer provided on the plurality of pad portions;

the first electrode layer is arranged on the first insulating layer, and comprises a plurality of first electrodes, and the first electrodes and the corresponding cushion layer parts are overlapped in the thickness direction of the display panel.

Optionally, in some embodiments of the present application, the display panel includes a plurality of sub-pixels, the pad layer portion is disposed corresponding to the sub-pixels, and the first electrode is a pixel electrode disposed corresponding to the sub-pixels.

Optionally, in some embodiments of the present application, the cushion portion includes a plurality of cushion subparts, and the first electrode includes a plurality of first sub-electrodes disposed in correspondence with the cushion subparts.

Optionally, in some embodiments of the present application, the cushion subpad is provided in a stripe configuration and the first microelectrode is provided in a corresponding stripe configuration with the cushion subpad.

Optionally, in some embodiments of the present application, the first insulating layer is further disposed in a first gap between the plurality of semiconductor portions and the plurality of pad portions, and in a second gap between adjacent pad sub-portions.

Optionally, in some embodiments of the present application, the display panel further includes:

the second insulating layer is arranged between the substrate and the first insulating layer, the second insulating layer is in contact with the first insulating layer at least at part of the first insulating layer, the second insulating layer comprises a first groove corresponding to the first gap and a second groove corresponding to the second gap, and the first insulating layer is further arranged in the first groove and the second groove.

Optionally, in some embodiments of the present application, the second insulating layer is a gate insulating layer.

Optionally, in some embodiments of the present application, further comprising:

the source-drain metal layer is arranged between the active layer and the first insulating layer, and comprises a source electrode and a drain electrode which are arranged at intervals and respectively connected with the semiconductor part.

Optionally, in some embodiments of the present application, the first insulating layer includes a first via, the first via is disposed corresponding to the drain, and the first electrode is electrically connected to the drain through the first via.

Correspondingly, the application also provides a manufacturing method of the display panel, which comprises the following steps:

providing a substrate;

forming an active layer on a substrate, patterning the active layer to form a plurality of semiconductor portions and a plurality of pad portions;

forming a first insulating layer on the active layer;

forming a first pattern photoresist layer on the pad layer portion, the first pattern photoresist layer covering first gaps between the plurality of semiconductor portions and the plurality of pad layer portions, the first pattern photoresist layer having a thickness of 0 on the plurality of pad layer portions;

flocking the first pattern photoresist layer;

forming a first electrode layer on the first pattern photoresist layer and the first insulating layer;

and removing the first pattern photoresist layer and the first electrode layer on the first pattern photoresist layer to form a plurality of first electrodes, wherein the first electrodes are overlapped with the corresponding cushion layer parts in the thickness direction of the display panel.

Optionally, in some embodiments of the present application, the display panel includes a plurality of sub-pixels;

after the cushion layer part is formed, the cushion layer part is arranged corresponding to the sub-pixels, and comprises a plurality of cushion layer sub-parts;

after forming a plurality of first electrodes, the first electrodes are pixel electrodes arranged corresponding to the sub-pixels, the first electrodes comprise a plurality of first sub-electrodes, and the first sub-electrodes are arranged corresponding to the cushion layer sub-portions.

Optionally, in some embodiments of the present application, the step of forming an active layer on a substrate, and patterning the active layer to form a plurality of semiconductor portions and a plurality of pad layer portions includes:

forming an active layer on the substrate;

forming a source drain metal layer on the active layer;

the source-drain metal layer and the active layer are patterned through the halftone light modulation cover, the source-drain metal layer comprises a source electrode and a drain electrode after being patterned, the active layer comprises a plurality of semiconductor parts and a plurality of cushion layer parts after being patterned, and the source electrode and the drain electrode are arranged on the semiconductor parts at intervals.

Optionally, in some embodiments of the present application, the step of forming the first patterned photoresist layer includes:

forming an initial photoresist layer on the first insulating layer, wherein the whole surface of the initial photoresist layer covers the first insulating layer;

the initial photoresist layer is processed through a half-tone photomask to form a second pattern photoresist layer, wherein the thickness of a preset part corresponding to the drain electrode in the second pattern photoresist layer is 0, and the thickness of the second pattern photoresist layer corresponding to a plurality of cushion layer parts is smaller than the thickness of the second pattern photoresist layer corresponding to the first gaps and a plurality of semiconductor parts;

and etching the second pattern photoresist layer and the first insulating layer at the preset part simultaneously to form a first via hole on the drain electrode, and removing the second pattern photoresist layer on the semiconductor parts and the cushion layer parts.

Optionally, in some embodiments of the present application, before the step of forming the active layer on the substrate, further includes: forming a gate electrode on the substrate, forming a gate insulating layer on the gate electrode, and forming an active layer on the gate insulating layer;

the step of patterning the active layer to form a plurality of semiconductor portions and a plurality of pad portions further includes: and over-etching the gate insulating layer to form a first groove corresponding to a first gap between a plurality of the semiconductor portions and a plurality of the pad layer portions and a second groove corresponding to a second gap between adjacent pad layer sub-portions, wherein the first insulating layer is further arranged in the first groove and the second groove.

In an embodiment of the present application, there is provided a display panel and a method for manufacturing the display panel, the display panel including: a substrate; the active layer is arranged on the substrate and comprises a plurality of semiconductor parts and a plurality of cushion layer parts; a first insulating layer disposed on the plurality of pad portions; the first electrode layer is arranged on the first insulating layer, and comprises a plurality of first electrodes which are overlapped with the corresponding cushion layer parts in the thickness direction of the display panel. The manufacturing method of the display panel comprises the following steps: providing a substrate; forming an active layer on a substrate, patterning the active layer to form a plurality of semiconductor portions and a plurality of pad portions; forming a first insulating layer on the active layer; forming a first pattern photoresist layer on the pad layer portion, the first pattern photoresist layer covering first gaps between the plurality of semiconductor portions and the plurality of pad layer portions, the first pattern photoresist layer having a thickness of 0 on the plurality of semiconductor portions and the plurality of pad layer portions; flocking the first pattern photoresist layer; forming a first electrode layer on the first patterned photoresist layer and the first insulating layer; the first pattern photoresist layer and the first electrode layer on the first pattern photoresist layer are removed to form a plurality of first electrodes, and the first electrodes and the corresponding cushion layer parts are overlapped in the thickness direction of the display panel. In the application, 1), the first electrode and the corresponding pad layer portion are overlapped, so that the precision and uniformity of the first electrode are mainly determined by the pad layer portion, when the pad layer portion is formed, a complete thin film transistor is not formed on the substrate, the flatness on the substrate is good, and the substrate can be covered flatly by the smaller photoresist layer thickness when the pad layer portion is formed, and therefore, the photoresist layer thickness is thinner, for example, the thickness of the photoresist layer is 0.5 micrometer, and the precision and uniformity of the pad layer portion formed by etching the thinner photoresist layer are good, so that the precision and uniformity of the first electrode are good; in the prior art, the precision and uniformity of forming the first electrode are determined by directly patterning the photoresist layer for forming the first electrode, at this time, a complete thin film transistor is formed on the substrate, the flatness on the substrate is poor, and the larger thickness of the photoresist layer can cover the substrate flatly when the first electrode is formed, so that the thickness of the photoresist layer is larger, for example, the thickness of the photoresist layer is larger than 1 micrometer, and the precision and uniformity of the first electrode formed by etching the thicker photoresist layer are poor; therefore, the precision and uniformity of the first electrode are improved compared with the prior art. 2) Forming a first electrode layer on the first patterned photoresist layer and the first insulating layer; the first pattern photoresist layer and the first electrode layer on the first pattern photoresist layer are removed to form a plurality of first electrodes, and the first electrodes and the corresponding cushion layer parts are overlapped in the thickness direction of the display panel. 3) Meanwhile, the first pattern photoresist layer covers the first gaps between the plurality of semiconductor parts and the plurality of cushion layers, the thickness of the first pattern photoresist layer on the plurality of semiconductor parts and the plurality of cushion layers is 0, and the first pattern photoresist layer is formed in the first gaps by utilizing a hot melt leveling process of photoresist materials, so that the thickness of the first pattern photoresist layer is smaller, and the organic solvent in the first pattern photoresist layer is smaller, and even if the organic solvent in the first pattern photoresist layer is not removed by a high-temperature curing thermal process, the problem that the organic solvent is precipitated to pollute vacuum equipment is avoided.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments will be briefly introduced below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a schematic partial top view of a first partial film layer of a display panel according to an embodiment of the disclosure;

FIG. 2 is a schematic top view of a portion of a second film layer of a display panel according to an embodiment of the disclosure;

fig. 3 is a schematic cross-sectional view of a portion of a film layer of a display panel according to an embodiment of the disclosure;

fig. 4 is a schematic diagram illustrating steps of a method for manufacturing a display panel according to a second embodiment of the present disclosure;

fig. 5 is a schematic diagram illustrating a first intermediate process of forming a pad layer portion in a method for manufacturing a display panel according to a second embodiment of the present disclosure;

fig. 6 is a schematic diagram illustrating a second intermediate process of forming a pad layer portion in a method for manufacturing a display panel according to a second embodiment of the present disclosure;

fig. 7 is a schematic diagram illustrating a third intermediate process of forming a pad layer portion in a method for manufacturing a display panel according to a second embodiment of the present disclosure;

fig. 8 is a schematic diagram illustrating a fourth intermediate process of forming a pad layer portion in a method for manufacturing a display panel according to a second embodiment of the present disclosure;

fig. 9 is a schematic diagram illustrating a fifth intermediate process of forming a pad layer portion in a method for manufacturing a display panel according to a second embodiment of the present disclosure;

fig. 10 is a schematic diagram illustrating a sixth intermediate process of forming a pad layer portion in a method for manufacturing a display panel according to a second embodiment of the present disclosure;

fig. 11 is a schematic diagram of a first intermediate process for forming a first electrode in a method for manufacturing a display panel according to a second embodiment of the present disclosure;

fig. 12 is a schematic diagram of a second intermediate process for forming a first electrode in a method for manufacturing a display panel according to a second embodiment of the present disclosure;

fig. 13 is a schematic diagram illustrating a third intermediate process for forming a first electrode in a method for manufacturing a display panel according to a second embodiment of the present disclosure;

fig. 14 is a schematic diagram illustrating a fourth intermediate process for forming a first electrode in a method for manufacturing a display panel according to a second embodiment of the present disclosure;

fig. 15 is a schematic diagram of a fifth intermediate process for forming a first electrode in a method for manufacturing a display panel according to a second embodiment of the present disclosure;

fig. 16 is a schematic diagram illustrating a sixth intermediate process for forming the first electrode in the method for manufacturing the display panel according to the second embodiment of the present application.

Fig. 17 is a schematic cross-sectional structure of another display panel according to an embodiment of the disclosure.

Detailed Description

The following description of the embodiments of the present application will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all, of the embodiments of the present application. All other embodiments, which can be made by those skilled in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application. Furthermore, it should be understood that the detailed description is presented herein for purposes of illustration and explanation only and is not intended to limit the present application. In this application, unless otherwise indicated, terms of orientation such as "upper" and "lower" are used to generally refer to the upper and lower positions of the device in actual use or operation, and specifically the orientation of the drawing figures; while "inner" and "outer" are for the outline of the device.

The application provides a display panel, including: a substrate; the active layer is arranged on the substrate and comprises a plurality of semiconductor parts and a plurality of cushion layer parts; a first insulating layer disposed on the plurality of pad portions; the first electrode layer is arranged on the first insulating layer, and comprises a plurality of first electrodes which are overlapped with the corresponding cushion layer parts in the thickness direction of the display panel.

The application also provides a manufacturing method of the display panel. The following will describe in detail. The following description of the embodiments is not intended to limit the preferred embodiments.

Example 1

Referring to fig. 1 to 3, fig. 1 is a schematic partial top view of a first partial film layer of a display panel according to an embodiment of the present disclosure; FIG. 2 is a schematic top view of a portion of a second film layer of a display panel according to an embodiment of the disclosure; fig. 3 is a schematic cross-sectional view of a portion of a film layer of a display panel according to an embodiment of the disclosure. The semiconductor portion and the pad layer portion are illustrated in fig. 1, the first electrode layer is illustrated in fig. 2, and fig. 3 is a schematic cross-sectional view of the portion indicated by the dotted line C-D in fig. 1.

The application provides a display panel 100, the display panel 100 includes a substrate 11, an active layer 14, a first insulating layer 16, a first electrode layer 17; the active layer 14 is disposed on the substrate 11, and the active layer 14 includes a plurality of semiconductor portions 141 and a plurality of pad portions 142; the first insulating layer 16 is disposed on the plurality of pad portions 142; the first electrode layer 17 is disposed on the first insulating layer 16, and the first electrode layer 17 includes a plurality of first electrodes 171, and the first electrodes 171 are disposed to overlap the corresponding pad portions 142 in the thickness direction of the display panel 100.

Specifically, the material of the active layer 14 may be amorphous silicon, polysilicon, or the like, which is not limited herein.

Specifically, the material of the first insulating layer 16 may be at least one of silicon nitride and silicon oxide, which is not limited herein.

Specifically, the material of the first electrode layer 17 may be Indium Tin Oxide (ITO), which is not limited herein.

Specifically, the display panel includes a plurality of thin film transistors and subpixels 101, and the active layer 14 includes a plurality of semiconductor portions 141 and a plurality of pad portions 142, and it is understood that the portions of the active layer 14 in the thin film transistors are the semiconductor portions 141, and the portions of the active layer 14 other than the thin film transistors are the pad portions 142.

Specifically, the pad portion 142 functions to form or support the first electrode layer 17 or the first electrode 171, which will be described in detail in the following embodiments.

Specifically, in the thickness direction of the display panel 100, the first electrode is disposed to overlap the corresponding pad layer portion 142, which may be understood that the front projection of the first electrode 171 on the substrate 11 overlaps the front projection of the corresponding pad layer portion 142 on the substrate 11, or the front projection of the first electrode 171 on the substrate 11 covers the front projection of the corresponding pad layer portion 142 on the substrate 11.

In some embodiments, the display panel includes a plurality of sub-pixels 101, the pad portion 142 is disposed corresponding to the sub-pixels 101, and the first electrode 171 is a pixel electrode disposed corresponding to the sub-pixels 101.

In some embodiments, cushion portion 142 includes a plurality of cushion sub-portions 1421 and first electrode 171 includes a plurality of first sub-electrodes 1711, first sub-electrodes 1711 being disposed corresponding to cushion sub-portions 1421.

In some embodiments, the cushion sub-portion 1421 is in a stripe configuration and the first sub-electrode 1711 is in a corresponding stripe configuration with the cushion sub-portion 1421.

In some embodiments, the first electrode 171 is a pixel electrode.

In some embodiments, pad portion 142 includes a plurality of pad sub-portions 1421 arranged in a stripe configuration, and first electrode 171 is in a corresponding stripe design to pad sub-portions 1421.

Specifically, the first electrode 171 is a pixel electrode, and the first electrode 171 may be a pixel electrode In an FFS (fringe field Switching technology) liquid crystal display panel or an IPS (In-Plane Switching technology) liquid crystal display panel, where the pixel electrode includes a plurality of pixel sub-electrodes 1721 and a gap 1722 between two adjacent pixel sub-electrodes 1721.

Specifically, the shape of the first electrode 171 or the pixel electrode is not limited herein, and for example, the first electrode 171 or the pixel electrode may be stripe-shaped, fishbone-shaped, m-shaped, or the like.

In some embodiments, the first insulating layer 16 is also disposed in a first gap 143 between the plurality of semiconductor portions 141 and the plurality of pad portions 142, and in a second gap 144 between adjacent pad sub-portions 1421.

In some embodiments, the display panel further includes a second insulating layer 41, the second insulating layer 41 is disposed between the substrate 11 and the first insulating layer 16, the second insulating layer 41 is disposed in contact with the first insulating layer 16 at least at a portion, the second insulating layer 41 includes a first groove 411 corresponding to the first gap 143, and a second groove 412 corresponding to the second gap 144, and the first insulating layer 16 is further disposed in the first groove 411 and the second groove 412.

Specifically, in order to ensure that the material removed in the first and second gaps 143 and 144 is free of residues (the active layer 14 is free of residues) during the formation of the first and second gaps 143 and 144, the second insulating layer 41 may be over-etched to form the first and second grooves 411 and 412, and the first insulating layer 16 is further disposed in the first and second grooves 411 and 412 when the first insulating layer 16 is formed.

In some embodiments, the second insulating layer 41 is the gate insulating layer 13.

In some embodiments, the display panel 100 further includes a source-drain metal layer 15, the source-drain metal layer 15 is disposed between the active layer 14 and the first insulating layer 16, the source-drain metal layer 15 includes a source electrode 151 and a drain electrode 152, and the source electrode 151 and the drain electrode 152 are spaced apart and connected to the semiconductor portion 141, respectively.

In some embodiments, the first insulating layer 16 includes a first via 161, the first via 161 is disposed corresponding to the drain electrode 152, and the first electrode 171 is electrically connected to the drain electrode 152 through the first via 161.

The following describes a method for manufacturing a display panel in detail, and the display panel in this embodiment has the same advantages as those of the method for manufacturing a display panel described below, and will not be described in detail herein.

Example two

Referring to fig. 4 to 16, fig. 4 is a schematic diagram illustrating steps of a method for manufacturing a display panel according to a second embodiment of the present disclosure; fig. 5 is a schematic diagram illustrating a first intermediate process of forming a pad layer portion in a method for manufacturing a display panel according to a second embodiment of the present disclosure; fig. 6 is a schematic diagram illustrating a second intermediate process of forming a pad layer portion in a method for manufacturing a display panel according to a second embodiment of the present disclosure; fig. 7 is a schematic diagram illustrating a third intermediate process of forming a pad layer portion in a method for manufacturing a display panel according to a second embodiment of the present disclosure; fig. 8 is a schematic diagram illustrating a fourth intermediate process of forming a pad layer portion in a method for manufacturing a display panel according to a second embodiment of the present disclosure; fig. 9 is a schematic diagram illustrating a fifth intermediate process of forming a pad layer portion in a method for manufacturing a display panel according to a second embodiment of the present disclosure; fig. 10 is a schematic diagram illustrating a sixth intermediate process of forming a pad layer portion in a method for manufacturing a display panel according to a second embodiment of the present disclosure.

Fig. 11 is a schematic diagram of a first intermediate process for forming a first electrode in a method for manufacturing a display panel according to a second embodiment of the present disclosure; fig. 12 is a schematic diagram of a second intermediate process for forming a first electrode in a method for manufacturing a display panel according to a second embodiment of the present disclosure; fig. 13 is a schematic diagram illustrating a third intermediate process for forming a first electrode in a method for manufacturing a display panel according to a second embodiment of the present disclosure; fig. 14 is a schematic diagram illustrating a fourth intermediate process for forming a first electrode in a method for manufacturing a display panel according to a second embodiment of the present disclosure; fig. 15 is a schematic diagram of a fifth intermediate process for forming a first electrode in a method for manufacturing a display panel according to a second embodiment of the present disclosure; fig. 16 is a schematic diagram illustrating a sixth intermediate process for forming the first electrode in the method for manufacturing the display panel according to the second embodiment of the present application.

The display panel 100 of any of the above embodiments may be manufactured by the manufacturing method of the display panel of the present embodiment.

The application provides a manufacturing method of a display panel, which comprises the following steps: s100, S200, S300, S400, S500, S600, S700.

S100, providing a substrate.

Specifically, as shown in fig. 11, a substrate 11 is provided.

And S200, forming an active layer on a substrate, and patterning the active layer to form a plurality of semiconductor parts and a plurality of cushion parts.

Specifically, as shown in fig. 11, an active layer 14 is formed on a substrate 11, and the active layer 14 is patterned to form a plurality of semiconductor portions 141 and a plurality of pad portions 142.

And S300, forming a first insulating layer on the active layer.

Specifically, as shown in fig. 11, a first insulating layer 16 is formed on the active layer 14.

S400, forming a first pattern photoresist layer on the pad layer portion, wherein the first pattern photoresist layer covers first gaps between the plurality of semiconductor portions and the plurality of pad layer portions, and the thickness of the first pattern photoresist layer on the plurality of pad layer portions is 0.

Specifically, as shown in fig. 13, the first pattern resist layer 31 is formed on the pad layer portion 142, the first pattern resist layer 31 covers the first gaps 143 between the plurality of semiconductor portions 141 and the plurality of pad layer portions 142, and the thickness of the first pattern resist layer 31 on the plurality of pad layer portions 142 is 0.

S500, flocking treatment is carried out on the first pattern photoresist layer.

Specifically, as shown in fig. 14, the first pattern photoresist layer 31 is subjected to a flocking process.

Specifically, as shown in fig. 14, after the flocking treatment is performed on the first pattern photoresist layer 31, the flock 311 is generated above the first pattern photoresist layer 31, and the flock 311 can be generated above the first pattern photoresist layer 31 by the high ashing treatment.

Specifically, the flocking process may be: and sputtering isolating layers of materials such as silicon nitride and the like onto the first pattern photoresist layer through inert gas to form a granular barrier layer in discrete distribution. The first pattern photoresist layer which is not blocked is ashed and etched through an ashing process to form a velvet 311.

And S600, forming a first electrode layer on the first pattern photoresist layer and the first insulating layer.

Specifically, as shown in fig. 15, the first electrode layer 17 is formed on the first pattern photoresist layer 31 and the first insulating layer 16.

Specifically, a first electrode layer 17 is deposited on the first patterned photoresist layer 31, and the first electrode layer 17 is broken by the velvet above the first patterned photoresist layer 31 because of the high and low fluctuation of the velvet structure generated above the first patterned photoresist layer 31, so that a broken pattern of the first electrode layer 17 is formed above the first patterned photoresist layer 31.

And S700, removing the first pattern photoresist layer and the first electrode layer on the first pattern photoresist layer to form a plurality of first electrodes, wherein the first electrodes are overlapped with the corresponding cushion layer parts in the thickness direction of the display panel.

Specifically, as shown in fig. 16, the first pattern photoresist layer 31 and the first electrode layer 17 on the first pattern photoresist layer 31 are removed to form a plurality of first electrodes 171, and the first electrodes 171 are disposed to overlap the corresponding pad layer portions 142 in the thickness direction of the display panel 100.

Specifically, since the first electrode layer 17 forms a fracture pattern of the first electrode layer 17 over the first pattern photoresist layer 31, the first pattern photoresist layer 31 and the first electrode layer 17 on the first pattern photoresist layer 31 can be removed by using the stripper contact.

Specifically, as shown in fig. 15 and 16, the first electrode layer 17 formed on the plurality of pad portions 142 may remain, thereby forming the first electrode 171.

In this embodiment, the beneficial effects include: 1) The first electrode 171 is overlapped with the corresponding pad layer portion 142, so that the accuracy and uniformity of the first electrode 171 are mainly determined by the pad layer portion 142, when the pad layer portion 142 is formed, a complete thin film transistor is not formed on the substrate, the flatness on the substrate is good, when the pad layer portion 142 is formed, the smaller photoresist layer thickness can cover the substrate flatly, and therefore, the photoresist layer thickness is thinner, for example, the thickness of the photoresist layer is 0.5 micrometer, and the accuracy and uniformity of the pad layer portion formed by etching the thinner photoresist layer are good, so that the accuracy and uniformity of the first electrode 171 are better; in the prior art, the precision and uniformity of forming the first electrode are determined by directly patterning the photoresist layer for forming the first electrode, at this time, a complete thin film transistor is formed on the substrate, the flatness on the substrate is poor, and the larger thickness of the photoresist layer can cover the substrate flatly when the first electrode is formed, so that the thickness of the photoresist layer is larger, for example, the thickness of the photoresist layer is larger than 1 micrometer, and the precision and uniformity of the first electrode formed by etching the thicker photoresist layer are poor; therefore, the present application improves the accuracy and uniformity of the first electrode compared to the prior art, and the inventors verified that the uniformity of the width of the first electrode 171 is improved from 45% to 15% of the prior art. 2) Forming a first electrode layer 17 on the first pattern photoresist layer 31 and the first insulating layer 16; the first pattern photoresist layer 31 and the first electrode layer 171 on the first pattern photoresist layer 31 are removed to form a plurality of first electrodes 171, and in the thickness direction of the display panel, the first electrodes 171 and the corresponding cushion layer portions 142 are overlapped, so that a photomask is not required to independently etch the first electrode layer 17, and the photomask and the process steps are saved. 3) At the same time, the first pattern photoresist layer 31 covers the first gaps 143 between the plurality of semiconductor portions 141 and the plurality of pad portions 142, the thickness of the first pattern photoresist layer 31 on the plurality of semiconductor portions 141 and the plurality of pad portions 142 is 0, and the first pattern photoresist layer 31 is formed in the first gaps 143 by using a thermal-melting leveling process of a photoresist material, so that the thickness of the first pattern photoresist layer 31 is small, and the organic solvent in the first pattern photoresist layer 31 is small, and there is no problem that the organic solvent is precipitated and contaminates the vacuum equipment even if the high-temperature curing thermal process is not performed to remove the organic solvent in the first pattern photoresist layer 31.

It should be noted that, the thickness of the first patterned photoresist layer 31 is smaller than or equal to the thickness of the pad layer 142, and thus, the thickness of the first patterned photoresist layer 31 is smaller, and the inventors have verified that the thickness of the first patterned photoresist layer 31 is greater than or equal to 0.3 μm and less than or equal to 0.5 μm, and thus, the amount of the organic solvent in the first patterned photoresist layer 31 is smaller, and the risk of contamination of the vacuum apparatus with the organic solvent is not generated during formation of the first electrode layer 17. In addition, the thickness of the first patterned photoresist layer 31 is smaller, and when the first patterned photoresist layer 31 and the first electrode layer 17 on the first patterned photoresist layer 31 are peeled off or removed, only a smaller amount of stripping liquid is needed, and the first patterned photoresist layer 31 and the first electrode layer 17 on the first patterned photoresist layer 31 can be peeled off or removed quickly, so that the usage amount of the stripping liquid can be reduced, the cost can be saved, the manufacturing time can be reduced, and the yield can be improved.

In the present embodiment, the first electrode layer 17 is formed on the first pattern photoresist layer 31 and the first insulating layer 16; the first pattern photoresist layer 31 and the first electrode layer 17 on the first pattern photoresist layer 31 are removed to form a plurality of first electrodes 171, and in the thickness direction of the display panel, the first electrodes 171 and the corresponding cushion layer portions 142 are overlapped, so that a photomask is not required to independently etch the first electrode layer 17, and the photomask and the process steps are saved. Meanwhile, the first pattern photoresist layer 31 covers the first gaps 143 between the plurality of semiconductor portions 141 and the plurality of pad portions 142, the thickness of the first pattern photoresist layer 31 on the plurality of semiconductor portions 141 and the plurality of pad portions 142 is 0, and the first pattern photoresist layer 31 is formed in the first gaps 143 by using a thermal-melting leveling process of a photoresist material, so that the thickness of the first pattern photoresist layer 31 is small, and an organic solvent in the first pattern photoresist layer 31 is small, and even if the organic solvent in the first pattern photoresist layer 31 is not removed by a high-temperature curing thermal process, there is no problem that the organic solvent is precipitated and contaminates a vacuum apparatus.

In some embodiments, the display panel includes a plurality of sub-pixels 101, and after forming the pad layer portion 142, the pad layer portion 142 is disposed corresponding to the sub-pixels 101, and the pad layer portion 142 includes a plurality of pad layer sub-portions 1421; after forming the plurality of first electrodes 171, the first electrodes 171 are pixel electrodes provided corresponding to the sub-pixels 101, and the first electrodes 17 include a plurality of first sub-electrodes 1711, and the first sub-electrodes 1711 are provided corresponding to the cushion sub-portions 1421.

Specifically, after forming cushion portion 142, cushion portion 142 includes a plurality of cushion sub-portions 1421 arranged in a stripe pattern; after forming the plurality of first electrodes 171, the first electrodes 171 and the pad layer sub-portions 1421 are in a corresponding stripe-like design.

In some embodiments, the first electrode 171 is a pixel electrode.

Further, in some embodiments, as shown in fig. 5-10, after forming the plurality of semiconductor portions 141 and the plurality of pad portions 142, before forming the first insulating layer 16 on the active layer 14, further includes: a source-drain metal layer 15 is formed on the semiconductor portion 141, and the source-drain metal layer 15 includes a source electrode 151 and a drain electrode 152 after patterning.

In some embodiments, as shown in fig. 5 to 10, "S200, the step of forming an active layer on a substrate, patterning the active layer to form a plurality of semiconductor portions and a plurality of pad portions" includes: s210, forming an active layer on a substrate; s220, forming a source drain metal layer on the active layer; s230, patterning the source-drain metal layer and the active layer through the halftone light modulation cover, wherein the source-drain metal layer comprises a source electrode and a drain electrode after being patterned, the active layer comprises a plurality of semiconductor parts and a plurality of cushion layer parts after being patterned, and the source electrode and the drain electrode are arranged on the semiconductor parts at intervals.

Specifically, as shown in fig. 5, S210, an active layer 14 is formed on a substrate 11; s220, the source-drain metal layer 15 is formed on the active layer 14.

Specifically, as shown in fig. 6 to 10, in S230, the source/drain metal layer 15 and the active layer 14 are patterned by the halftone mask, the source/drain metal layer 15 includes the source electrode 151 and the drain electrode 152 after being patterned, the active layer 14 includes the plurality of semiconductor portions 141 and the plurality of pad portions 142 after being patterned, and the source electrode 151 and the drain electrode 152 are disposed on the semiconductor portions 141 at intervals.

More specifically, the step of S230 includes: s231, as shown in FIG. 5 and FIG. 6, a preset photoresist layer 81 is formed through a halftone mask, the thickness of the part of the preset photoresist layer 81 corresponding to the first gap 143 is 0 (the thickness of the part of the preset photoresist layer 81 corresponding to the second gap 144 is also 0), and the thickness of the part of the preset photoresist layer 81 corresponding to the source 151 and the drain 152 is greater than the thickness of the part corresponding to the space between the source 151 and the drain 152; s232, as shown in fig. 7, forming a preset pad layer portion by wet etching the source drain metal layer 15 and dry etching the active layer 14; s233, as shown in FIG. 8, ashing the preset photoresist layer, wherein the thickness of the preset photoresist layer corresponding to the source electrode 151 and the drain electrode 152 is greater than 0, and the thickness of the preset photoresist layer at the other parts is 0; s234, as shown in fig. 9, the wet etching source/drain metal layer 15 forms the pad layer 142, the source 151, and the drain 152; s235, as shown in FIG. 10, removing or stripping the preset photoresist layer.

Note that the method of forming the pad portion 142, the semiconductor portion 141, the source electrode 151, and the drain electrode 152 is not limited to step S230 or S231 to S235, and the pad portion 142, the semiconductor portion 141, the source electrode 151, and the drain electrode 152 may be formed by a stepwise manufacturing method, for example, the active layer 14 is formed first, the pad portion 142 and the semiconductor portion 141 are formed by one mask, the source-drain metal layer 15 is formed, and the source electrode 151 and the drain electrode 152 are formed by one mask.

In some embodiments, the step of forming the first patterned photoresist layer 31 includes the steps of: s410, S420, S430.

S410, forming an initial photoresist layer on the first insulating layer, wherein the whole surface of the initial photoresist layer covers the first insulating layer.

Specifically, as shown in fig. 11, an initial photoresist layer 30 is formed on the first insulating layer 16, and the initial photoresist layer 30 entirely covers the first insulating layer 16.

S420, processing the initial photoresist layer through a half-tone photomask to form a second pattern photoresist layer, wherein the thickness of the preset part of the second pattern photoresist layer corresponding to the drain electrode is 0, and the thickness of the second pattern photoresist layer corresponding to the semiconductor parts and the cushion layer parts is smaller than the thickness of the second pattern photoresist layer corresponding to the first gap and the second gap.

Specifically, as shown in fig. 11 and 12, the initial photoresist layer 30 is processed by a half-tone mask (HTM) or a Gray Tone Mask (GTM) to form a second patterned photoresist layer 32, wherein the thickness of a predetermined portion of the second patterned photoresist layer 32 corresponding to the drain electrode 152 is 0, and the thickness of the second patterned photoresist layer 32 corresponding to the plurality of pad layers 142 is smaller than the thickness of the second patterned photoresist layer 32 corresponding to the first gap 143, the second gap 144 and the plurality of semiconductor portions 141.

S430, etching the second pattern photoresist layer 32 and the first insulating layer at the preset position simultaneously to form a first via hole on the drain electrode, and removing the second pattern photoresist layer 32 on the plurality of semiconductor parts and the plurality of cushion layer parts.

Specifically, as shown in fig. 12 and 13, the first insulating layer 16 is etched at a predetermined portion to form a first via 161 on the drain electrode 152, and the second patterned photoresist layer 32 on the pad layer portions 142 is ashed to be removed to form the first patterned photoresist layer 31.

In some embodiments, the step of forming the active layer 14 on the substrate 11 further includes, prior to: forming a gate electrode 12 on a substrate 11, forming a gate insulating layer 13 on the gate electrode 12, and forming an active layer 14 on the gate insulating layer 13; the step of patterning the active layer 14 to form the plurality of semiconductor portions 141 and the plurality of pad portions 142 further includes: the gate insulating layer 13 is over-etched to form a first groove 411 corresponding to the first gap 143 between the plurality of semiconductor portions 141 and the plurality of pad portions 142, and a second groove 412 corresponding to the second gap 144 between the adjacent pad sub-portions 1421, and the first insulating layer 16 is further disposed in the first groove 411 and the second groove 412.

Specifically, as shown in fig. 7, in order to ensure that the material removed in the first and second gaps 143 and 144 is free from residues (the active layer 14 is free from residues) during the formation of the first and second gaps 143 and 144, the second insulating layer 41 may be over-etched to form first and second grooves 411 and 412, and the first insulating layer 16 is further disposed in the first and second grooves 411 and 412 when the first insulating layer 16 is formed.

Specifically, the first groove 411 and the second groove 412 may be formed by dry etching.

It should be noted that, if the second insulating layer 41 is not over-etched, a display panel is formed as shown in fig. 17, fig. 17 is a schematic cross-sectional structure of another display panel according to the embodiment of the present application, and the difference between fig. 17 and fig. 3 is that: in fig. 17, the first groove 411 and the second groove 412 are not provided.

In some embodiments, after forming the plurality of first electrodes 171, the first electrodes 171 are connected to the corresponding drain electrodes 152 through the first vias 161.

The foregoing has described in detail a display panel and a method for manufacturing the display panel provided in the embodiments of the present application, and specific examples have been applied herein to illustrate the principles and embodiments of the present application, and the description of the foregoing examples is only for aiding in understanding the method and core concept of the present application; meanwhile, those skilled in the art will have variations in the specific embodiments and application scope in light of the ideas of the present application, and the present description should not be construed as limiting the present application in view of the above.

Claims (10)

1. A display panel, comprising:

a substrate;

an active layer disposed on the substrate, the active layer including a plurality of semiconductor portions and a plurality of pad portions;

a first insulating layer provided on the plurality of pad portions;

the first electrode layer is arranged on the first insulating layer, and comprises a plurality of first electrodes, and the first electrodes and the corresponding cushion layer parts are overlapped in the thickness direction of the display panel.

2. The display panel of claim 1, wherein the display panel includes a plurality of sub-pixels, the pad layer portion is disposed corresponding to the sub-pixels, and the first electrode is a pixel electrode disposed corresponding to the sub-pixels.

3. The display panel of claim 2, wherein the cushion portion comprises a plurality of cushion sub-portions, and the first electrode comprises a plurality of first sub-electrodes disposed in correspondence with the cushion sub-portions.

4. The display panel of claim 3, wherein the pad sub-portions are arranged in a stripe configuration and the first sub-electrodes are arranged in a corresponding stripe configuration with the pad sub-portions.

5. The display panel of claim 3, wherein the first insulating layer is further disposed in a first gap between the plurality of semiconductor portions and the plurality of spacer portions and in a second gap between adjacent ones of the spacer portions.

6. The display panel of claim 5, wherein the display panel further comprises:

the second insulating layer is arranged between the substrate and the first insulating layer, the second insulating layer is in contact with the first insulating layer at least at part of the first insulating layer, the second insulating layer comprises a first groove corresponding to the first gap and a second groove corresponding to the second gap, and the first insulating layer is further arranged in the first groove and the second groove.

7. A method of manufacturing a display panel, comprising:

providing a substrate;

forming an active layer on a substrate, patterning the active layer to form a plurality of semiconductor portions and a plurality of pad portions;

forming a first insulating layer on the active layer;

forming a first pattern photoresist layer on the pad layer portion, the first pattern photoresist layer covering first gaps between the plurality of semiconductor portions and the plurality of pad layer portions, the first pattern photoresist layer having a thickness of 0 on the plurality of pad layer portions;

flocking the first pattern photoresist layer;

forming a first electrode layer on the first pattern photoresist layer and the first insulating layer;

and removing the first pattern photoresist layer and the first electrode layer on the first pattern photoresist layer to form a plurality of first electrodes, wherein the first electrodes are overlapped with the corresponding cushion layer parts in the thickness direction of the display panel.

8. The method of manufacturing a display panel according to claim 7, wherein the display panel includes a plurality of sub-pixels;

after the cushion layer part is formed, the cushion layer part is arranged corresponding to the sub-pixels, and comprises a plurality of cushion layer sub-parts;

after forming a plurality of first electrodes, the first electrodes are pixel electrodes arranged corresponding to the sub-pixels, the first electrodes comprise a plurality of first sub-electrodes, and the first sub-electrodes are arranged corresponding to the cushion layer sub-portions.

9. The method of manufacturing a display panel according to claim 7, wherein the step of forming an active layer on a substrate and patterning the active layer to form a plurality of semiconductor portions and a plurality of pad portions comprises:

forming an active layer on the substrate;

forming a source drain metal layer on the active layer;

the source-drain metal layer and the active layer are patterned through the halftone light modulation cover, the source-drain metal layer comprises a source electrode and a drain electrode after being patterned, the active layer comprises a plurality of semiconductor parts and a plurality of cushion layer parts after being patterned, and the source electrode and the drain electrode are arranged on the semiconductor parts at intervals.

10. The method of manufacturing a display panel according to claim 9, wherein the step of forming the first patterned photoresist layer comprises:

forming an initial photoresist layer on the first insulating layer, wherein the whole surface of the initial photoresist layer covers the first insulating layer;

the initial photoresist layer is processed through a half-tone photomask to form a second pattern photoresist layer, wherein the thickness of a preset part corresponding to the drain electrode in the second pattern photoresist layer is 0, and the thickness of the second pattern photoresist layer corresponding to a plurality of cushion layer parts is smaller than the thickness of the second pattern photoresist layer corresponding to the first gaps and a plurality of semiconductor parts;

and etching the second pattern photoresist layer and the first insulating layer at the preset part simultaneously to form a first via hole on the drain electrode, and removing the second pattern photoresist layer on the semiconductor parts and the cushion layer parts.