KR20000008693A - Transistor and manufacturing method thereof - Google Patents

Abstract

PURPOSE: A transistor is provided to be suited for a high integrated circuit and improve the topography of the transistor. CONSTITUTION: The transistor comprises a rectangular gate(25) line made of a conducting material such as polycrystalline silicon doped with a dopant, and a first gate oxide film(23) and a second gate oxide film(27) enclosed a bottom and a surface of the gate line. A semiconductor area is provided on an outer portion of the first and second gate oxide films, in which the semiconductor area includes a p-typed semiconductor substrate(21) and an active layer(31) doped with a p-typed dopant. n-typed first to fourth dopant areas are formed on four corner of the gate to form four transistors, i.e., two transverse transistors and two vertical transistors, together with the gate line.

Description

Transistors and manufacturing methods thereof

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transistor of a semiconductor device and a method of manufacturing the same, and more particularly, to a transistor and a method of manufacturing the same, which are suitable for high integration by stacking transistors and can improve the topography of the transistor.

1A to 1B are cross-sectional process diagrams showing a method of manufacturing a transistor according to the prior art.

Conventionally, as shown in FIG. 1A, a gate oxide film 13 is formed on a conductive semiconductor substrate 11, for example, a p-type semiconductor substrate 11, and a chemical vapor deposition is formed on the gate oxide film 13. Chemical Vapor Deposition (hereinafter, referred to as CVD) is a method of depositing polysilicon doped with impurities to form a polysilicon layer. The polysilicon layer and the gate oxide film 13 are patterned to form a gate 15 in a predetermined portion of the semiconductor substrate 11.

Then, as shown in FIG. 1B, the gate 15 is used as a mask for the semiconductor substrate 11, and an asce (As) having a conductivity different from that of the p-type semiconductor substrate 11 or phosphorus ( N-type impurities such as P) are ion-implanted to form n-type impurity regions 17 used as source / drain regions in the semiconductor substrate 11 below the gate 15.

As described above, a gate having a gate oxide film interposed therebetween is formed in a predetermined portion on a first conductive semiconductor substrate, and a semiconductor substrate under the gate side is doped with a second conductive impurity to be used as a source / drain region. The transistor was formed by a method of forming an impurity region.

However, the transistor according to the conventional method described above has a limitation in integration, and there is a problem in that the topography of the transistor is lowered due to a gate formed in a predetermined portion on the semiconductor substrate.

Accordingly, an object of the present invention is to provide a transistor suitable for high integration and capable of improving topography and a method of manufacturing the same.

A transistor according to the present invention for achieving the above object is a rectangular gate line formed of a conductive material, the first and second gate insulating film surrounding the gate line, the element is formed outside the first and second gate insulating film The first to fourth impurity regions, the first to fourth impurity regions of the second conductivity type formed in the semiconductor region of the gate line corners, and a protective film covering the upper portion of the device. The impurity region forms two vertical transistors and two horizontal transistors together with the gate line.

A method of manufacturing a transistor according to the present invention for achieving the above object comprises the steps of forming a first insulating film on a first conductive semiconductor substrate and forming a gate in a predetermined portion on the first insulating film, and using the gate as a mask Forming first and second impurity regions of a second conductivity type in the semiconductor substrate below the gate side; forming a second insulating film to cover the gate on the first insulating film, and forming the first and second Patterning an insulating film to form first and second gate insulating films on a surface of the gate; forming a first conductive type active layer on the semiconductor substrate to cover the second gate insulating film; A mask layer is formed on a predetermined portion corresponding to the gate, and a second layer is formed on the active layer on the gate side by using the mask layer as a mask. The step of forming the impurity region of the second type, and comprises a step of forming a protective film to cover the active layer.

1A to 1B are process diagrams showing a method for manufacturing a transistor according to the prior art.

2 is a cross-sectional view illustrating a transistor according to an embodiment of the present invention.

3A to 3E are flowcharts illustrating a method of manufacturing a transistor according to an embodiment of the present invention.

<Brief description of symbols for the main parts of the drawings>

21 semiconductor substrate 23 first gate oxide film

25 gate 27 second gate oxide film

29, 30: first and second impurity regions 31: active layer

33, 34: third and fourth impurity regions 35: protective film

Hereinafter, with reference to the accompanying drawings will be described the present invention.

2 is a cross-sectional view illustrating a transistor according to an exemplary embodiment of the present invention.

As shown in FIG. 2, the transistor of the present invention has a quadrangular line of gate 25 made of a conductive material such as polycrystalline silicon doped with impurities, and first and second gates surrounding the bottom and the surface of the gate 25 line. There are oxide films 23 and 27. In addition, a p-type semiconductor substrate 21 on which semiconductor devices are formed and an active layer doped with p-type impurities on the semiconductor substrate 31 are formed outside the first and second gate oxide films 23 and 27. N-type first to fourth impurity regions 29, 30, 33, and 34 are formed at four corners of the gate 25 in the semiconductor region of the semiconductor region. Together with the line 25 it forms four transistors, two horizontal transistors and two vertical transistors. The first and second impurity regions 29 and 30 are formed in the p-type semiconductor substrate 21, and the third and fourth impurity regions 33 and 34 are formed in the active layer 31. In addition, the passivation layer 35 is formed of an insulating material on the active layer 31 to improve the topography of the transistor.

In other words, the transistor having the above-described structure is formed by stacking two vertical transistors and two horizontal transistors in an area where one transistor is formed, thereby driving four transistors simultaneously by applying a voltage to one gate, which is suitable for high integration. Done. In addition, by forming the protective layer on the active layer in which the gate is embedded and the device is formed, it is possible to improve the topography of the transistor caused by the conventional gate.

3A to 3E are flowcharts illustrating a method of manufacturing a transistor according to an embodiment of the present invention.

In this method, as shown in FIG. 3A, a first oxide film 22 is formed on a conductive semiconductor substrate 21, for example, a p-type semiconductor substrate 21 by thermal oxidation, and the first oxide film is formed. Polycrystalline silicon doped with impurities on 22 is deposited by a CVD method to form a polysilicon layer, and the polysilicon layer is patterned to form a gate 25 on a predetermined portion on the first oxide film 22.

As shown in FIG. 3B, the gate 25 is used as a mask for the semiconductor substrate 21, and an n type such as an asic (As) or phosphorus (P) having a different conductivity type from the semiconductor substrate 21. Impurities are implanted to form first and second impurity regions 29 and 30, which are n-type impurity doped regions, in the semiconductor substrate 21 below the gate 25. The exposed first oxide film 22 serves to prevent damage to the surface of the semiconductor substrate 21 during ion implantation to form the first and second impurity regions 29 and 30.

Thereafter, as shown in FIG. 3C, first and second gate oxide films 23 and 27 covering the surface of the gate 25 are formed. The first and second gate oxide films 23 and 27 form a second oxide film covering the gate 25 on the first oxide film 22 and selectively pattern the first and second oxide films. The semiconductor substrate 21 may be formed by covering the surface of the gate 25 and exposing the semiconductor substrate 21 where the gate 25 is not formed, or thermally oxidizing the gate 25 to form the second gate oxide layer 27. And the first oxide film 22 is selectively patterned to expose the semiconductor substrate 21 in a portion where the gate 25 is not formed. Then, the active layer 31 is formed on the semiconductor substrate 21 by CVD or epitaxial growth so as to cover the gate 25, and the active layer is doped in the same p-type as the semiconductor substrate 21. .

In the above, another method of forming the first and second gate oxide films 23 and 27 of FIG. 3C before forming the p-type active layer 31 is provided on a predetermined portion on the p-type semiconductor substrate 21. 1 form a gate 25 interposed between the gate oxide layer 23, and form an oxide layer on the semiconductor substrate 21 to cover the gate 25, and then a mask layer on the portion corresponding to the gate 25. And n-type impurities are implanted using the mask layer as a mask, and the n-type first and second impurity regions 29 are formed on the semiconductor substrate 21 under the gate 25. 30 is formed. The oxide layer is patterned using the mask layer as a mask to form a second gate oxide layer 27 on the surface of the gate 25 while exposing the semiconductor substrate 21 not in contact with the gate 25. There is also a method of removing the mask layer. In the above method, the oxide film portion removed by the patterning serves to prevent damage to the surface of the semiconductor substrate 21 during ion implantation for forming the first and second impurity regions 29 and 30. .

Subsequently, as shown in FIG. 3D, a mask layer 32 covering the portion corresponding to the gate 25 is formed on the active layer 31, and the active layer 31 is formed on the active layer using the mask layer 32 as a mask. N-type impurities having a different conductivity type from ion) are implanted to form n-type third and fourth impurity regions 33 and 34 in the active layer 31 on the side of the gate 25.

Thereafter, as shown in FIG. 3E, the protective layer is removed using an oxide film or a nitride film on the active layer 31 on which the mask layer 32 is removed and the third and fourth impurity regions 33 and 34 are formed. (35) is formed. When the device is annealed to activate the first and second impurity regions 29 and 33, four stacked transistors sharing the top, bottom, left, right source, and drain regions are formed. In this case, the passivation layer 35 prevents out-diffusion of impurities doped in the third and fourth impurity regions 33 and 34 during the annealing, and flattens the top of the completed transistor. It serves to improve the topography of the stacked transistors.

In the transistor formed as described above, the first and second impurity regions and the gate form a horizontal first transistor, and the second and third impurity regions and the gate become vertical second transistors, and the third and fourth impurities A region and a gate become a horizontal third transistor, and the fourth and first impurity regions and a gate become a vertical fourth transistor to drive the two horizontal transistors and the two vertical transistors simultaneously.

Accordingly, the present invention has a structure in which two vertical transistors and two horizontal transistors are stacked, which is suitable for high integration of semiconductor devices and has a gate-embedded structure to improve the topography of the transistor.

Claims (5)

A rectangular gate line formed of a conductive material, First and second gate insulating layers surrounding the gate lines; A semiconductor region of a first conductivity type in which elements are formed outside the first and second gate insulating films; First to fourth impurity regions of a second conductivity type formed in the semiconductor region of the gate line corners; And a passivation layer covering an upper portion of the device. The transistor of claim 1, wherein the gate line and the first to fourth impurity regions form two vertical transistors and two horizontal transistors. The transistor of claim 1, wherein the first conductive semiconductor region comprises a semiconductor substrate and an active layer. Forming a first insulating film on the first conductive semiconductor substrate and forming a gate in a predetermined portion on the first insulating film; Forming first and second impurity regions of a second conductivity type on the semiconductor substrate under the gate side using the gate as a mask; Forming a second insulating film so as to cover the gate on the first insulating film, and patterning the first and second insulating films to form first and second gate insulating films on the surface of the gate; Forming a first conductivity type active layer on the semiconductor substrate to cover the second gate insulating film; Forming a mask layer on a predetermined portion corresponding to the gate on the active layer and using the mask layer as a mask to form third and fourth impurity regions of a second conductivity type in the active layer above the gate side; And forming a protective film so as to cover the active layer. The method of claim 4, wherein the active layer is formed by a chemical vapor deposition method or an epitaxial growth method.