KR20000004978A - Semiconductor integrated circuit - Google Patents
Semiconductor integrated circuit Download PDFInfo
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- KR20000004978A KR20000004978A KR1019980707589A KR19980707589A KR20000004978A KR 20000004978 A KR20000004978 A KR 20000004978A KR 1019980707589 A KR1019980707589 A KR 1019980707589A KR 19980707589 A KR19980707589 A KR 19980707589A KR 20000004978 A KR20000004978 A KR 20000004978A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 117
- 239000000758 substrate Substances 0.000 claims abstract description 28
- 230000001681 protective effect Effects 0.000 claims abstract description 25
- 239000000463 material Substances 0.000 claims description 11
- 230000005693 optoelectronics Effects 0.000 claims description 7
- 229910052751 metal Inorganic materials 0.000 claims description 5
- 239000002184 metal Substances 0.000 claims description 5
- 238000000034 method Methods 0.000 claims description 4
- 229910052710 silicon Inorganic materials 0.000 claims description 4
- 239000010703 silicon Substances 0.000 claims description 4
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 claims description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 3
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 claims description 3
- 150000001875 compounds Chemical class 0.000 claims description 3
- 230000035945 sensitivity Effects 0.000 claims description 3
- 238000007599 discharging Methods 0.000 abstract 2
- 230000006378 damage Effects 0.000 description 6
- 230000005540 biological transmission Effects 0.000 description 5
- 230000017525 heat dissipation Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/64—Heat extraction or cooling elements
- H01L33/641—Heat extraction or cooling elements characterized by the materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
- H01L25/167—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits comprising optoelectronic devices, e.g. LED, photodiodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48464—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area also being a ball bond, i.e. ball-to-ball
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Semiconductor Integrated Circuits (AREA)
- Bipolar Integrated Circuits (AREA)
- Addition Polymer Or Copolymer, Post-Treatments, Or Chemical Modifications (AREA)
Abstract
Description
반도체 집적회로, 특히 반도체 레이저 회로나 적외선 발광 다이오드와 같은 고속 광전자 전송 소자들은 전송 소자의 pn 접합의 반대방향으로의 전압 스파이크나 정전기 전하(ESD)에 민감하며, 이는 소자에 손상을 입히거나 소자의 파괴를 초래하게 된다. ESD 손상을 피하기 위하여, 공지된 반도체 집적회로는 소자의 반도체 기판상에 형성되며 특히 소자의 액티브 pn 접합의 접속점과 접지 사이에 접속된 보호용 다이오드 형태로 과전압을 소산시키는 작용을 하는 보호 회로를 갖는다. 보호 회로는 소자와 동일한기판상에서 정확하게 과전압에 대해 보호되는 소자의 최근방에 배치된다. 동일한 기판상에 보호회로를 제조하는 것은 특히 갈륨 비화물, 인듐 인화물등과 같은 Ⅲ-Ⅴ족 화합물로 이루어진 반도체 기판을 갖는 광전자 전송 소자의 경우에 어려움을 초래할 수 있다. 한편, 반도체 기판상에 보호회로를 형성하는데 이용될 수 있는 공간은 구성배치 때문에 제한될 수 있다. 더욱이, 광전자 전송 소자는 특히 대체로 높은 전송 파워전송 때문에 소자의 동작 동안에 열의 양호한 소산을 보장하기 위한 측정을 필요로 한다. 적합하지 못한 방법에서, Ⅲ-Ⅴ 화합물로 이루어진 반도체 재료는 실리콘보다 더 나쁜 열 도전성을 가지며, 그 결과, 대부분의 이러한 전송소자에서는, 전송 소자 칩에 열적으로 결합되고 전송 소자의 칩 영역에 비해 더 큰 영역과 낮은 열 저항을 갖는 재료로 이루어진 마운트(mount)가 양호한 열 소산을 위하여 사용된다.Semiconductor integrated circuits, particularly high speed optoelectronic transfer devices such as semiconductor laser circuits or infrared light emitting diodes, are sensitive to voltage spikes or electrostatic charge (ESD) in the opposite direction of the pn junction of the transfer device, which can damage or destroy the device. Will result. In order to avoid ESD damage, known semiconductor integrated circuits are formed on the semiconductor substrate of the device and in particular have a protective circuit which acts to dissipate the overvoltage in the form of a protective diode connected between the connection point of the device's active pn junction and ground. The protection circuit is disposed on the same substrate as the device, closest to the device which is protected against overvoltage. Fabrication of the protective circuit on the same substrate can cause difficulties especially in the case of an optoelectronic transmission element having a semiconductor substrate made of group III-V compounds such as gallium arsenide, indium phosphide and the like. On the other hand, the space that can be used to form the protective circuit on the semiconductor substrate may be limited due to the configuration arrangement. Moreover, optoelectronic transfer devices require measurements to ensure good dissipation of heat during operation of the device, especially because of the generally high transfer power transfer. In an unsuitable method, semiconductor materials consisting of III-V compounds have worse thermal conductivity than silicon, and as a result, in most such transfer devices, they are thermally coupled to the transfer device chip and are more than the chip area of the transfer device. Mounts made of materials with large areas and low thermal resistance are used for good heat dissipation.
발명의 요약Summary of the Invention
본 발명은 액티브 소자와 액티브 소자에 할당되며 과전압을 소산시키는 작용을 하는 보호회로를 갖는 반도체 집적회로를 제공하는 것을 목적으로 하며, 반도체 집적회로에서 보호 회로는 이러한 구조로 이루어지고 소자의 동작동안에 생성된 열의 최대 가능한 소산의 요건들을 동시에 응하는 것이 가능한 방법으로 액티브 소자에 집적될 수 있다.It is an object of the present invention to provide a semiconductor integrated circuit having an active element and a protection circuit assigned to the active element and having a function of dissipating overvoltage, in which the protection circuit is made of such a structure and generated during operation of the element. It can be integrated in the active element in such a way that it is possible to meet the requirements of the maximum possible dissipation of the generated heat simultaneously.
상기 목적은 청구범위 1항에 따른 반도체 집적회로에 의해 달성된다.This object is achieved by a semiconductor integrated circuit according to claim 1.
본 발명에 따르면, 소자에 할당되고 과전압 및/또는 정전기 전하를 소산시키는 작용을 하는 보호회로는 반도체 마운트 상에 형성되며 반도체 마운트에 배치된 제 1 도전형의 제 1 반도체 마운트 영역 및 제 2 도전형의 제 2 반도체 마운트 영역을 가진다. 제 2 도전형의 제 2 반도체 영역은 반도체 기판에 형성된 제 1 도전형의 제 1 반도체 영역에 전기적으로 결합된다.According to the present invention, a protective circuit assigned to the element and acting to dissipate overvoltage and / or electrostatic charges is formed on the semiconductor mount and the first and second conductivity type semiconductor mount regions of the first conductivity type disposed on the semiconductor mount. Has a second semiconductor mount region. The second semiconductor region of the second conductivity type is electrically coupled to the first semiconductor region of the first conductivity type formed in the semiconductor substrate.
본 발명은 별도의 반도체 마운트상에 전기적으로 차단성이지만 높은 열 도전성의 pn 접합의 형태로 액티브 소자에 할당된 보호회로를 형성하는 관점을 기초로한다. 실리콘을 갖는 반도체 재료로 이루어진 반도체 마운트를 사용함으로써, 아주 간단한 방법으로 보호회로를 제조하고 그것을 반도체 마운트에 집적시킬 수 있으며, 그러므로 소자의 동작동안에 생성된 파워 때문에 열의 양호한 소산을 위해 동시에 제공될 수 있다. 보호회로의 pn 접합이 소자의 동작동안에 전기적으로 차단되기 때문에, 액티브 소자에 대한 전기적 절연을 위해 높은 열 저항을 갖는 산화 또는 질화 절연물이 전혀 필요없다.The present invention is based on the point of forming a protective circuit assigned to the active element in the form of an electrically shielded but highly thermally conductive pn junction on a separate semiconductor mount. By using a semiconductor mount made of a semiconductor material with silicon, it is possible to fabricate a protective circuit in a very simple way and to integrate it into a semiconductor mount, and therefore to provide simultaneously for good dissipation of heat due to the power generated during operation of the device. . Since the pn junction of the protection circuit is electrically interrupted during operation of the device, there is no need for oxidized or nitride insulators with high thermal resistance for electrical isolation of the active device.
본 발명의 원리에 따르면, 이 경우 반도체 기판에 형성된 소자의 pn 접합과 반도체 마운트 상에 형성된 보호회로의 보호용 pn 접합은 서로 평행하게 역방향 접속된다.According to the principle of the present invention, in this case, the pn junction of the element formed on the semiconductor substrate and the protective pn junction of the protection circuit formed on the semiconductor mount are connected in reverse in parallel with each other.
반도체 기판상에 형성된 소자는 독립적이고 별도로 제조되고 반도체 마운트상에 장착되어 그것에 의해 지지되는 반도체 칩을 구성하는 것이 이롭게 제공된다. 더욱이 반도체 마운트의 재료는 높은 열 도전성을 가지며 액티브 pn 접합을 가지는 소자의 반도체 기판은 반도체 마운트에 열적으로 결합되는 것이 이롭게 제공된다. 비교적 작은 영역의 소자에 대해서도, 반도체 마운트에 양호한 열적 결합에 의해 소자의 동작동안에 생성된 열의 유리한 소산을 보장할 수 있으며, 반도체 마운트는 열 소산의 목적을 위해 소자에 비해 상당히 큰 유효영역을 갖는다.The elements formed on the semiconductor substrate are advantageously provided to constitute a semiconductor chip which is manufactured independently and separately mounted and supported by the semiconductor mount. Furthermore, it is advantageously provided that the material of the semiconductor mount has high thermal conductivity and that the semiconductor substrate of the device with the active pn junction is thermally coupled to the semiconductor mount. Even for devices of relatively small areas, good thermal bonding to the semiconductor mount can ensure favorable dissipation of the heat generated during operation of the device, and the semiconductor mount has a significantly larger effective area than the device for the purpose of heat dissipation.
본 발명의 바람직한 구성에 있어서, 전기적으로 그리고 열적으로 도전성의 얇은 금속층은 액티브 pn 접합을 가지는 소자의 반도체 기판과 반도체 마운트 사이에 제공될 수 있다. 소자의 반도체 기판은 이롭게는 반도체 마운트의 얇은 금속층위에 전기적으로 도전성의 접착제에 의해 고착될 수 있다.In a preferred configuration of the present invention, an electrically and thermally conductive thin metal layer can be provided between the semiconductor substrate of the device having the active pn junction and the semiconductor mount. The semiconductor substrate of the device can advantageously be secured by an electrically conductive adhesive on the thin metal layer of the semiconductor mount.
본 발명의 바람직한 적용에 있어서, 반도체 기판상에 형성되며 액티브 pn 접합을 가지는 소자는 광전자 전송 소자를 이루며, 전송 소자의 동작동안, 액티브 pn 접합은 순방향 바이어스되고 반도체 마운트상에 형성된 보호용 pn 접합은 역방향 바이어스된다. 반도체 마운트상에 형성된 보호회로의 보호용 pn 접합은 둘다 p형 영역일 때 액티브 전송 소자에 걸리는 높은 역방향 전압을 방지하며, 반도체 마운트 상에 형성된 보호 다이오드의 n형 영역은 반도체 소자의 액티브 pn 접합의 p형 및 n형 영역과 평행하게 전기적으로 역방향 접속된다.In a preferred application of the invention, an element formed on a semiconductor substrate and having an active pn junction constitutes an optoelectronic transfer element, wherein during operation of the transfer element the active pn junction is forward biased and the protective pn junction formed on the semiconductor mount is reversed. Biased. The protective pn junction of the protection circuit formed on the semiconductor mount prevents the high reverse voltage applied to the active transfer element when both are p-type regions, and the n-type region of the protection diode formed on the semiconductor mount is p of the active pn junction of the semiconductor element. Electrically connected in parallel with the type and n-type regions.
제조하는데 특히 간단한 본 발명의 구성에 있어서, 제 1 도전형의 제 1 반도체 영역은 전기도전성 소자 콘택형성층(contact-making layer)이 제공되고, 이 콘택형성층은 제 2 도전형의 제 2 반도체 마운트 영역의 표면상에 배치되는 콘택 영역에 본딩 와이어를 통해 접속된다.In a configuration of the invention that is particularly simple to manufacture, the first semiconductor region of the first conductivity type is provided with an electroconductive element contact-making layer, which is a second semiconductor mount region of the second conductivity type. It is connected via a bonding wire to a contact region disposed on the surface of the.
본 발명에 따른 장치는 과전압 및/또는 정전기 척에 대한 보호회로의 민감성이 보호회로의 캐패시턴스를 형성하는 제 1 및 제 2 반도체 마운트의 적당한 도핑에 의해 세팅될 수 있다. 반도체 마운트에 대한 기판 재료의 적당한 선택에 있어서, 보호 다이오드의 캐피시턴스가 넓은 범위안에서 적정하게 세팅되도록 할 수 있다. 이 경우, 캐패시턴스는 특히 액티브 소자의 주파수 응답의 손상이 전혀 없고 동시에 과전압 및/또는 정전기 전하에 대한 민감성이 충분히 높게 되도록 선택된다.The device according to the invention can be set by the appropriate doping of the first and second semiconductor mounts in which the sensitivity of the protection circuit to overvoltage and / or electrostatic chuck forms the capacitance of the protection circuit. In the proper choice of substrate material for the semiconductor mount, it is possible to ensure that the capacitance of the protection diode is set appropriately within a wide range. In this case, the capacitance is chosen in particular so that there is no damage to the frequency response of the active element and at the same time the sensitivity to overvoltage and / or electrostatic charge is sufficiently high.
본 발명의 다른 특징, 이점 및 방법들은 도면을 참조로 실시예의 설명으로부터 명백할 것이다.Other features, advantages and methods of the present invention will be apparent from the description of the embodiments with reference to the drawings.
본 발명은 반도체 기판상에 형성되고 제 1 도전형의 제 1 반도체 영역과 제 2 도전형의 제 2 반도체 영역 사이에 형성된 액티브 pn 접합을 갖는 소자, 및 상기 소자에 할당되며 과전압 및/또는 정전기 전하를 소산시키는 작용을 하는 보호회로를 갖는 반도체 집적회로에 관한 것이다.The present invention provides a device having an active pn junction formed on a semiconductor substrate and formed between a first semiconductor region of a first conductivity type and a second semiconductor region of a second conductivity type, and assigned to the device and overvoltage and / or electrostatic charges. The present invention relates to a semiconductor integrated circuit having a protection circuit for dissipating.
도 1은 본 발명의 반도체 집적회로를 도시한 도면.1 illustrates a semiconductor integrated circuit of the present invention.
도 1은 p 도전형의 제 1 반도체 영역(4)과 n 도전형의 제 2 반도체 영역(5) 사이에 형성된 액티브 pn 접합을 이루며 반도체 기판(2)상에 형성된 광전자 전송소자(3)를 갖는 반도체 집적회로(1)를 도시한다. 광전자 전송소자(3)는 예를 들면 반도체 기판의 기본재료로서 갈륨 비화물이나 인듐 인화물을 갖는, 별도로 제조된 반도체 레이저나 적외선 전송 다이오드 칩을 이룬다. 전송소자(3)의 동작동안에 생성된 열을 소산시키기 위하여, 후자는 높은 열 도전성을 갖는 재료 특히 실리콘으로 이루어진 대영역 반도체 마운트(7)상에 열적으로 결합된다. 역방향으로 액티브 전송소자(3)의 전압 스파이크나 정전기 전하에 대한 보호를 위해, 본 발명에 따른 방법에서 반도체 마운트(7)상에 형성된 보호용 pn 접합(9)을 가지며 p 도전형의 반도체 마운트에 배치된 제 1 반도체 마운트 영역(10)과 n 도전형의 제 2 반도체 마운트 영역(11)을 가지는 보호 다이오드 형태로 소자(3)에 할당된 보호회로(8)가 제공된다. 보호 다이오드(8)의 n형 영역(11)은 반도체 마운트(7)의 표면(12)상에 배치되고 p형 영역(4)의 표면위의 도전성 소자 콘택형성층(15)에 본딩 와이어(14)를 통해 전기적으로 접속되는 금속 콘택 영역(13)에 전기적으로 접속된다. 반도체 마운트(7)의 p형 영역(10)은 전기적으로 열적으로 도전성인 얇은 금속층(16)을 통해 전송 소자(3)의 n형 영역과 전기접촉한다. 이러한 방법으로, 소자(3)의 액티브 pn 접합과 반도체 마운트(7)상에 형성된 보호회로(8)의 보호용 pn 접합(9)은 서로 평행하게 역방향 접속된다. 참조부호 17은 얇은 전기절연층을 가리킨다. 전송 소자(3)의 동작 동안에, 액티브 pn 접합(6)은 순방향 바이어스되고 반도체 마운트(7)상에 형성된 보호용 pn 접합(9)은 역방향 바이어스된다. 예를 들면 전자기 방전으로 인한 전송소자(3)의 역방향으로의 전압 스파이크는 반도체 마운트(7)에서 도전성 보호용 pn 접합(9)에 의해 효과적으로 단락되며, 그 결과 정전기 전하 또는 과전압 때문에 소자(3)의 손상이나 파괴를 효과적으로 피할 수 있게 된다. 이 경우, 보호용 pn 접합(9) 때문에 형성된 반도체 마운트(7)의 부가 캐패시턴스는 액티브 전송 소자(3)의 순방향으로 정전기 손상에 대한 보호의 측정을 제공한다.1 shows an active pn junction formed between a p-conductive first semiconductor region 4 and an n-conductive second semiconductor region 5 and has an optoelectronic transfer element 3 formed on a semiconductor substrate 2. The semiconductor integrated circuit 1 is shown. The optoelectronic transfer element 3 forms a separately manufactured semiconductor laser or an infrared transmission diode chip having, for example, gallium arsenide or indium phosphide as the base material of the semiconductor substrate. In order to dissipate the heat generated during the operation of the transmission element 3, the latter is thermally coupled on a large area semiconductor mount 7 made of a material having high thermal conductivity, in particular silicon. In order to protect against voltage spikes or electrostatic charges of the active transfer element 3 in the reverse direction, in the method according to the present invention, a protective pn junction 9 formed on the semiconductor mount 7 is disposed in a p-conductive semiconductor mount. There is provided a protection circuit 8 assigned to element 3 in the form of a protection diode having a first semiconductor mount region 10 and a second semiconductor mount region 11 of n conductivity type. The n-type region 11 of the protection diode 8 is disposed on the surface 12 of the semiconductor mount 7 and the bonding wire 14 to the conductive element contact forming layer 15 on the surface of the p-type region 4. It is electrically connected to the metal contact region 13 which is electrically connected through. The p-type region 10 of the semiconductor mount 7 is in electrical contact with the n-type region of the transmission element 3 via the thin metal layer 16 which is electrically thermally conductive. In this way, the active pn junction of the element 3 and the protective pn junction 9 of the protective circuit 8 formed on the semiconductor mount 7 are connected in reverse in parallel with each other. Reference numeral 17 denotes a thin electrically insulating layer. During operation of the transfer element 3, the active pn junction 6 is forward biased and the protective pn junction 9 formed on the semiconductor mount 7 is reverse biased. For example, the voltage spike in the reverse direction of the transmission element 3 due to electromagnetic discharge is effectively shorted by the pn junction 9 for the conductive protection in the semiconductor mount 7, and as a result, the element 3 is discharged due to electrostatic charge or overvoltage. Damage or destruction can be effectively avoided. In this case, the additional capacitance of the semiconductor mount 7 formed due to the protective pn junction 9 provides a measure of protection against electrostatic damage in the forward direction of the active transfer element 3.
Claims (10)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE19612388A DE19612388C2 (en) | 1996-03-28 | 1996-03-28 | Integrated semiconductor circuit, in particular an optoelectronic component with overvoltage protection |
| DE19612388.7 | 1996-03-28 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR20000004978A true KR20000004978A (en) | 2000-01-25 |
Family
ID=7789757
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019980707589A KR20000004978A (en) | 1996-03-28 | 1997-03-13 | Semiconductor integrated circuit |
Country Status (9)
| Country | Link |
|---|---|
| US (1) | US5990499A (en) |
| EP (1) | EP0891639A1 (en) |
| JP (1) | JPH11507182A (en) |
| KR (1) | KR20000004978A (en) |
| CN (1) | CN1214803A (en) |
| CA (1) | CA2250352A1 (en) |
| DE (1) | DE19612388C2 (en) |
| TW (1) | TW345733B (en) |
| WO (1) | WO1997037390A1 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100646569B1 (en) * | 2005-12-15 | 2006-11-15 | 엘지전자 주식회사 | Light emitting device package and method for fabricating the same |
| KR100697044B1 (en) * | 2005-08-09 | 2007-03-20 | (주)큐엠씨 | Light emitting diode and method of fabricating the same |
| KR100765021B1 (en) * | 2005-02-16 | 2007-10-09 | 산켄덴키 가부시키가이샤 | Composite semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH10303467A (en) * | 1997-04-28 | 1998-11-13 | Rohm Co Ltd | Multichip module |
| US6185240B1 (en) * | 1998-01-30 | 2001-02-06 | Motorola, Inc. | Semiconductor laser having electro-static discharge protection |
| WO2005056269A2 (en) * | 2003-12-09 | 2005-06-23 | G.L.I. Global Light Industries Gmbh | Method for the production of light-emitting semiconductor diodes on a printed circuit board, and illumination units comprising an integrated circuit board |
| DE10357818B4 (en) * | 2003-12-09 | 2009-10-08 | Odelo Gmbh | Method for producing light-emitting semiconductor diodes on a circuit board |
| EP1587151A3 (en) * | 2004-04-17 | 2011-09-28 | LG Electronics, Inc. | Semiconductor light emitting device and fabrication method thereof |
| JP4747516B2 (en) | 2004-06-08 | 2011-08-17 | 富士ゼロックス株式会社 | Vertical cavity surface emitting semiconductor laser device |
| KR100448351B1 (en) * | 2004-06-10 | 2004-09-14 | 에피밸리 주식회사 | Ⅲ-nitride semiconductor light emitting device |
| JP5055717B2 (en) * | 2005-06-20 | 2012-10-24 | 富士ゼロックス株式会社 | Surface emitting semiconductor laser |
| JP4978014B2 (en) * | 2006-01-30 | 2012-07-18 | サンケン電気株式会社 | Semiconductor light emitting device and manufacturing method thereof |
| US9195079B2 (en) | 2012-01-01 | 2015-11-24 | Acacia Communications, Inc. | Three port transceiver |
| KR101916273B1 (en) | 2012-05-30 | 2018-11-07 | 삼성전자주식회사 | Semiconductor light emitting device and manufacturing method the same |
| WO2019116981A1 (en) * | 2017-12-15 | 2019-06-20 | ローム株式会社 | Submount and semiconductor laser device |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59188181A (en) * | 1984-03-23 | 1984-10-25 | Hitachi Ltd | Silicon submount |
| KR890002811B1 (en) * | 1986-11-04 | 1989-07-31 | 삼성전자 주식회사 | Laser diode |
| JPH04365382A (en) * | 1991-06-13 | 1992-12-17 | Toshiba Corp | Semiconductor light-emitting device and its driving method |
-
1996
- 1996-03-28 DE DE19612388A patent/DE19612388C2/en not_active Expired - Lifetime
-
1997
- 1997-03-13 KR KR1019980707589A patent/KR20000004978A/en not_active Application Discontinuation
- 1997-03-13 EP EP97919273A patent/EP0891639A1/en not_active Ceased
- 1997-03-13 WO PCT/DE1997/000501 patent/WO1997037390A1/en not_active Application Discontinuation
- 1997-03-13 CN CN97193435A patent/CN1214803A/en active Pending
- 1997-03-13 CA CA002250352A patent/CA2250352A1/en not_active Abandoned
- 1997-03-13 JP JP9534789A patent/JPH11507182A/en active Pending
- 1997-03-25 TW TW086103769A patent/TW345733B/en active
-
1998
- 1998-09-28 US US09/163,599 patent/US5990499A/en not_active Expired - Lifetime
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100765021B1 (en) * | 2005-02-16 | 2007-10-09 | 산켄덴키 가부시키가이샤 | Composite semiconductor device |
| KR100697044B1 (en) * | 2005-08-09 | 2007-03-20 | (주)큐엠씨 | Light emitting diode and method of fabricating the same |
| KR100646569B1 (en) * | 2005-12-15 | 2006-11-15 | 엘지전자 주식회사 | Light emitting device package and method for fabricating the same |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1214803A (en) | 1999-04-21 |
| WO1997037390A1 (en) | 1997-10-09 |
| TW345733B (en) | 1998-11-21 |
| DE19612388C2 (en) | 1999-11-04 |
| EP0891639A1 (en) | 1999-01-20 |
| JPH11507182A (en) | 1999-06-22 |
| CA2250352A1 (en) | 1997-10-09 |
| DE19612388A1 (en) | 1997-10-02 |
| US5990499A (en) | 1999-11-23 |
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