KR20000004305A - Data interface circuit of a pdp television - Google Patents

Abstract

PURPOSE: A data interface circuit of a PDP(Plasma Display Panel) television is disclosed to easily implement a chip. CONSTITUTION: Instead of removing a demultiplexer, D-flip flops of a data storing unit are connected each other in parallel. The D flip flops are directly connected to a memory. A clock pulse is selectively provided to the D flip flops to enable the data corresponding to each of the D flip flops to be latched. Since the demuliplexer located between the memory and the data storing unit is removed, the logic is simple and the number of connection patterns between the components is diminished. Thereby, it is possible to implement the chip.

Description

A data interface circuit of a PDP television

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plasma display panel (hereinafter referred to as PDP) television, and in particular, a PDP for storing R (Red), G (Green), and B (Blue) data received from a memory unit by one horizontal line of the PDP. It relates to a data interface circuit of a television.

In general, PDP (Plasma Display Panel) is a flat panel display panel that uses a penning gas for discharge, that is, gases based on Ne or Helium gas having a relatively high air pressure (over 100 Torr). The panel which uses the light emission phenomenon obtained by discharge between the narrow electrodes covered by the dielectric material.

The penning gas is mainly Ne + Xe, Ne + He + Xe, and the reason for using such a mixed gas is that the discharge start voltage can be lowered when the mixed gas is more than one gas component. The discharge start voltage depends on the type of gas, the fanning gas pressure, and the structure and shape of the panel.

The PDP has the following advantages over other display devices.

First of all, the PDP has no limitation on the number of horizontal and vertical display lines, so that a large size can be manufactured and multiplexing technology can be used to reduce the number of driving circuits.

The large matrix display panel has a memory function that is needed to eliminate high brightness and flicker, while the CRT has a lifespan of 20,000 hours, while the PDP has a lifespan of 50,000 hours.

In addition, PDP is suitable for mass production because there are no easily broken parts other than glass, and its structure is simple, so that large panels can be manufactured, and because of its strong nonlinearity, it can have a resolution of 100 Line / inch or more.

Since the discharging material is a gas, the refractive index value is 1, which means that the light is not extinguished by the internal reflection and the external light is not reflected or scattered by the display material. In addition, unlike other flat panels, the PDP is sealed with glass above 400 ° C, which means that the PDP can operate even under high humidity conditions or the presence of reactive gases. It is only a change.

The PDP is classified into AC type PDP and DC type PDP according to the type of driving voltage applied to the discharge cell. The AC type PDP is driven by a sine wave AC voltage or a pulse voltage, while the DC type PDP is driven by a DC voltage. In addition, in the AC type PDP, the electrode is covered with a dielectric of glass, whereas in the DC type PDP, the electrode is exposed as it is and a discharge current flows while the discharge voltage is applied.

1 is a block diagram showing a schematic configuration of a typical AC type color PDP television. The AC type color PDP television includes an audio / video unit 110, an analog / digital converter 120, a memory unit 130, and data. Interface unit 140, upper and lower address driving IC unit 150-1, 150-2, scan and sustain driving IC unit 160, timing control unit 170, high voltage driving circuit unit 180, AC-DC conversion A portion 190 and a three-electrode surface discharge color PDP 200.

The audio / video unit 110 receives an NTSC composite video signal through an antenna and separates analog R (Red), G (Green), and B (Blue) signals from horizontal and vertical sync signals (Hsync, Vsync), An average picture level (APL) corresponding to an average value of the luminance signal is obtained and provided to the analog / digital converter 120. Here, the NTSC composite video signal has an interlaced scanning method in which one frame consists of two fields, odd and even, a horizontal sync signal (Hsync) has a frequency of about 15.73KHz, and a vertical sync signal (Vsync) has a frequency of about 60Hz. .

The analog / digital converter 120 receives analog R, G, and B signals from the audio / video unit 110, converts the analog R, G, and B signals into digital data, and outputs the digital data to the memory unit 130.

The memory unit 130 stores digital R, G, and B signals received from the analog / digital converter 120. In general, for gradation processing of the PDP, image data of one field must be reconstructed into a plurality of subfields, and then rearranged from the most significant bit to the least significant bit. The memory unit 130 is used as an area for storing one frame of image data.

The data interface unit 140 stores the R, G, and B data received from the memory unit 130 by one horizontal line of the three-electrode surface discharge color PDP 200, and then stores the address driving IC units 150-1, Provided in the form of data required by 150-2).

The address driver IC unit includes upper and lower address driver IC units 150-1 and 150-2, and the upper address driver IC unit 150-1 is provided with R, G, and B data received from the data interface unit 140. Address pulses are supplied to odd-numbered address electrode lines of the three-electrode surface discharge PDP 200 according to " high " and " low " The address pulses are supplied to the even-numbered address electrode lines of the three-electrode surface discharge color PDP 200 in accordance with the "high" and "low" of the received R, G, and B data.

The scan and sustain driving IC unit 160 supplies a scan pulse and a sustain pulse to the scan and sustain electrode lines of the 3-electrode surface discharge color PDP 200, respectively.

The timing controller 170 receives the horizontal and vertical synchronization signals Hsync and Vsync output from the audio / video unit 110 to generate a data read clock (data read CLK) to generate the memory unit 130 and the data interface unit. Each of them is supplied to the 140, and various logic control pulses are generated and supplied to the high voltage driving circuit unit 180.

The high voltage driving circuit unit 180 combines the DC voltage supplied from the AC-DC conversion unit 190 according to various logic control pulses output from the timing controller 170 to address, scan, and sustain driving IC unit 150-1. , High voltage control pulses required by the 150-2 and 160 may be driven to drive the three-electrode surface discharge color PDP 200. In addition, the data stream provided from the data interface unit 140 to the address driving IC units 150-1 and 150-2 is also raised to an appropriate voltage level to enable selective writing to the three-electrode surface discharge color PDP 200.

The AC-DC converter 190 generates AC voltages (220V AC, 60Hz) as inputs to generate high voltages required to combine the electrode driving pulses and all DC voltages required by each component constituting the system. Supply.

The three-electrode surface discharge color PDP 200 uses a display dimension of 853 x 3 (R, G, B) x 480.

FIG. 2 is a block diagram illustrating a partial configuration of the data interface unit illustrated in FIG. 1, wherein the data interface unit 140 may output R, G, and B data received from the memory unit 130 to a three-electrode surface discharge color PDP 200. R, G, and B data received from the memory unit 130 to be rearranged according to the R, G, and B pixel arrangements of the N) and supplied to the upper and lower address driving IC units 150-1 and 150-2. First and second data storage units 140-1 and 140-2 storing horizontal lines (853 x 3 = 2559 bits) and 48 bits R, G, and B received in parallel from the memory unit 130. A demultiplexer unit 140-3 selectively outputs data to predetermined locations of the first and second data storage units 140-1 and 140-2.

In the above description, the first and second data storage units 140-1 and 140-2 are arranged in a matrix structure of 48 (rows) by 54 (columns) so as to store one horizontal line of data (2559 bits). It consists of 48 x 54 D-flip flops. As shown in FIG. 3, each of the 48 × 54 D-flip-flops has a D input terminal connected to the demultiplexer unit 140-3 so that one bit of predetermined 48-bit data from the memory unit 130 is demultiplexer unit. The input terminal is input via D-3 (140-3), the system reference clock (clk25M) of 25 MHz is input to the clock terminal, and the enable terminal is the 54 consecutive data output periods from the memory unit 130. A pulse P_54 that is held at logic "high" is input.

Here, the use of the two data storage units 140-1 and 140-2 is because the continuity of the data must be guaranteed (the input and the output are performed simultaneously). That is, R, G, and B data (D1,1 to D1,48; D2,1 to D2,48;…; D54,1 to D54,48) of the current one horizontal line inputted from the memory unit 130 are stored. While being stored in the first data storage 140-1 in turn, the R, G, and B data (D1,1 'to D1) of the previous one horizontal line amount stored in the second data storage 140-2. 48 '; D2, 1' to D2, 48 '; ...; D54, 1' to D54, 48 'are in the form of data streams required by the upper and lower address driver IC units 150-1 and 150-2. The output operation is performed at the same time.

The output terminals of the demultiplexer 140-3 are 48 × 54 × 2 (two data storage units) = 5184 D of the first data storage unit 140-1 and the second data storage unit 140-2. The first data storage unit 140-1 is connected to the D input terminal of the flip-flop, respectively, and 48 bits of R, G, and B data are sequentially inputted from the memory unit 130 by 48 bits at a time. B is output to the predetermined place of the second data storage 140-2.

Meanwhile, the operation between the memory unit 130, the demultiplexer unit 140-3, and the first and second data storage units 140-1 and 140-2 as described above is performed at 25 MHz in FIG. 4. It is made according to the reference clock clk25M and the pulse P_54 generated and output by the timing controller 170, and more specifically, each D-flip of the first and second data storage units 140-1 and 140-2. The flop is enabled only during the logic " high " period of the pulse P_54, and latches and stores data input to the D input terminal on the rising edge of the system reference clock clk25M in the enabled state. As a result, 48 x 54 D-flip-flops of the first data storage 140-1 or the second data storage 140-2 during the logical " high " period of the pulse P_54 have one horizontal line amount. R, G, and B data are stored.

However, since the conventional data interface unit includes a demultiplexer unit for selectively connecting between the memory unit and the data storage unit, the logic is complicated, and there are too many connection patterns (data transfer patterns) between the demultiplexer unit and the data storage unit. Chip implementation was difficult.

The present invention has been made to solve the above problems, and instead of removing the demultiplexer unit, the D-flip-flops of the data storage unit are connected to each other in parallel and directly connected to the memory unit, and in this state, are connected in parallel to each other. By selectively applying a clock pulse to the D-flip-flops so that the corresponding data is latched to each D-flip-flop, the data of the PDP television is simplified and the chip is simplified by greatly reducing the number of connection patterns between components. The purpose is to provide an interface circuit.

In order to achieve the above object, a data interface circuit of a PDP television according to the present invention is a data interface circuit of a PDP television that receives and stores R, G, and B data corresponding to one horizontal line of the PDP from a memory unit. And N × M D-flip flops arranged in a matrix structure of N (rows) × M (columns), wherein the D-flip flops are connected to each other in parallel with the D input terminals for each row. A data storage unit which receives the same data from the memory unit through a data input terminal, and clock terminals are connected in parallel to each column to receive the same clock signal through the first to M clock input terminals; A clock input terminal to which the clock pulses are supplied by sequentially supplying clock pulses to the first to M clock input terminals one by one in synchronization with the timing at which R, G, and B data are input in parallel to the first to N data input terminals. And a clock signal generator configured to store R, G, and B data input to the first through N data input terminals, respectively, in N D-flip flops connected to the N-D flip-flops.

The present invention also provides two data storage units for storing data input from the memory unit and outputting data stored in the data storage unit at the same time, and storing data in one of the two data storage units. The first to M clock input terminals of the corresponding data storage unit are operated by performing an AND operation on the selection signal maintained at the start point of the one horizontal line display period of the PDP to be performed and the clock signal output from the clock signal generator. A logical AND operation of the first AND logic unit to supply to the AND and the inverted signal of the selection signal and the clock signal output from the clock signal generator so as to store data in the other one of the two data storage units. Second logical multiplications supplied to the first to M clock input terminals of the data storage unit, respectively. Preferably further comprising added.

1 is a block diagram showing a schematic configuration of a typical AC color plasma display panel television;

2 is a block diagram illustrating a part of a configuration of a data interface unit illustrated in FIG. 1;

FIG. 3 is a diagram illustrating one of a plurality of D flip-flops constituting the data storage unit shown in FIG. 2;

4 is a timing diagram of each signal used in the prior art;

5A and 5B are block diagrams illustrating a partial configuration of a data interface unit according to an embodiment of the present invention;

6 is a timing diagram of each signal used in one embodiment of the present invention.

<Description of the symbols for the main parts of the drawings>

40: data interface unit 41: first data storage unit

42: second data storage 43: clock signal generator

44: first AND product 45: second AND product

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

AC type color PDP televisions to which the present invention is applied, like the conventional technology, have an audio / video unit, an analog / digital converter, a memory unit, a data interface unit, upper and lower address driver IC units, a scan and sustain driver IC unit, and a timing controller. It consists of a high voltage driving circuit part, an AC / DC converter and a three-electrode surface discharge color PDP.

5A and 5B are block diagrams illustrating a partial configuration of a data interface unit according to an exemplary embodiment of the present invention, wherein the data interface unit 40 includes first and second data storage units 41 and 42 and a clock signal. A generation unit 43 and first and second logical product operation units 44 and 45 are provided.

The first data storage section 41 is composed of 48 × 54 D-flip flops D1,1 to D54,48 arranged in a matrix structure of 48 (rows) × 54 (columns), and the 2592 D -The flip-flops D1,1 to D54,48 are parallel to each other (D1,1 to D54,1; D1,2 to D54,2; ...; D1,48 to D54,48). Connected to each other to receive the same data from a memory unit (not shown) through the first to 48th data input terminals IN1 to IN48, and for each column (D1,1 to D1,48; D2,1 to 1). D2, 48, ... D54, 1 to D54, 48 clock terminals are connected in parallel to each other and receive the same clock signals S1 to S54 through the first to 54 clock input terminals CLK1 to CLK54, respectively.

The second data storage section 42 is composed of 48 x 54 D-flip flops D'1,1 to D'54,48 arranged in a matrix structure of 48 (rows) x 54 (columns), The 2592 D-flip flops D'1,1 to D'54,48 are each row D'1,1 to D'54,1; D'1,2 to D'54,2; D'1,48 to D'54,48 The D input terminals are connected in parallel to each other from the memory unit (not shown) through the first to 48th data input terminals IN1 'to IN48', respectively. The same data is received, and each terminal (D'1,1 to D'1,48; D'2,1 to D'2,48;…; D'54,1 to D'54,48) clock terminal They are connected in parallel to each other and receive the same clock signals S1 to S54 through the first to 54 clock input terminals CLK1 'to CLK54'.

The data input terminals IN1 to IN48 (IN1 'to IN48') of the first and second data storage units 41 and 42 are directly connected to the memory unit without the demultiplexer unit, unlike the prior art.

In addition, the demultiplexer 140-3 and the first and second data storage 140-1 are removed by removing the demultiplexer located between the first and second data storages 41 and 42 and the memory. 140-2) between 48 × 54 × 2 connection patterns and 48 connection patterns (total 5232 connection patterns) between the memory unit and the demultiplexer unit 140-3, in accordance with an embodiment of the present invention. The number of connection patterns between components, such as 48 × 2 connection patterns between the first and second data storage sections 41 and 42, is greatly reduced than before.

The clock pulse generator 43 may include first to 48 data input terminals IN1 to IN48 of the first data storage unit 41 or first to 48 data input terminals of the second data storage units 41 and 42. The first to 54 clock input terminals CLK1 to the first and second data storage units 41 and 42 in synchronization with the time point at which R, G, and B data are input in parallel by 48 bits to IN1 'to IN48'. Clock pulses are sequentially supplied to CLK54 (CLK1 'to CLK54') one by one. At this time, the clock signals S1 to S54 respectively output through the 54 output terminals of the clock pulse generator 43 are shown in FIG. 6 as signals synchronized with the system reference clock clk25M at 25 MHz.

The first AND operation unit 44 is inverted at the beginning of one horizontal line display period of the three-electrode surface discharge color PDP (not shown) so that the data stored in the first data storage unit 41 is outputted. The first to 54 clock input terminals of the first data storage unit 41 may be logically operated on the selection signal slct held during the period and the clock signals S1 to S54 output from the clock signal generator 43. It consists of 54 AND gates 44-1 to 44-54 supplied to CLK1 to CLK54, respectively.

The second AND operation unit 45 is an inverted signal of the selection signal slct and the clock signals S1 to S54 output from the clock signal generator 43 so that the data stored in the second data storage 42 is output. Is composed of 54 AND gates 45-1 to 45-54 supplied to the first to 54 clock input terminals CLK1 'to CLK54' of the second data storage unit 42 by the logical AND operation. .

Referring to the timing diagram shown in FIG. 6, the operation of the data interface unit according to the exemplary embodiment of the present invention configured as described above is as follows.

First, each AND gate 45-1 to 2 of the second AND product 45 during the one horizontal line display period in which the selection signal slct shown in FIG. 6 is inverted and maintained from logic "low" to logic "high" is maintained. Since the selection signal slct of the logic " low " is input to 45-54, the outputs of the AND gates 45-1 to 45-54 of the second AND product 45 are output from the clock signal generator 43. Regardless of the clock signals S1 to S54 applied, it is always a logic " low " so that any of the D-flip flops D'1,1 to D'54,48 provided in the second data storage 42 can be used. It is not active.

On the other hand, in the AND gates 44-1 to 44-54 of the first AND product 44 during the one horizontal line display period in which the selection signal slct is maintained at the logic " high ", the selection signal of the logic " high " Since (slct) is input, the outputs of the AND gates 44-1 to 44-54 of the first AND product 44 are the logic levels of the clock signals S1 to S54 applied from the clock signal generator 43. Is selectively logic " high ", whereby the D-flip flops D1,1 to D54,48 provided in the first data storage 41 are activated in units of columns.

More specifically, each of the AND gates 44-1 to 44-54 of the first AND product 44 is the other one in a state in which a logic "high" selection signal slct is applied to one of the two input terminals. When the logic level of the clock signal applied to the input terminal is " high ", a logic " high " (clock pulse) is applied to the clock input terminal of the first data storage unit 41 connected thereto and the logic is applied through the clock input terminal. Activates 48 D-flip-flops (located in the same column) to which "high" is applied, and then activates the 48 D-flip-flops at their respective D through first to 48 data input terminals IN1 to IN48. L, G or B data input to the input terminal is latched.

The clock signals S1 to S54 output from the clock signal generator 43 are maintained at logic "low" as shown in FIG. 6, and are sequentially synchronized with the system reference clock clk25M once at a logic "high". As a signal containing a clock pulse, the clock signal includes only one clock pulse in one clock signal during one horizontal line display period.

Therefore, the 48 × 54 D-flip flops D1,1 to D54,48 of the first data storage 41 are sequentially activated in column units in accordance with the clock signals S1 to S54 so as to display one horizontal line display period. During the first to 48th data input terminals IN1 to IN48, the corresponding R, G, or B data inputted 54 times by 48 bits is latched.

Meanwhile, as described above, R, G, and B data of one horizontal line of the three-electrode surface discharge color PDP are sequentially stored in each of the D-flip flops D1,1 to D54,48 of the first data storage unit 41. During latching, the R, G, and B data corresponding to the previous horizontal line stored in each of the D-flip flops D'1,1 to D'54,48 of the second data storage 42 are stored in the data stream. Output to the upper and lower address driver IC units.

When the R, G, and B data of one horizontal line is latched to each of the D-flip flops D1,1 to D54,48 of the first data storage unit 41 through the above process, the selection signal slct is The logic "high" is inverted from logic "low" to remain logic "low" for the display period of the next horizontal line, at which time the operation of the first and second data storage portions 41, 42 is described above. This is the opposite of the period during which the select signal slct remains logical " high. &Quot;

That is, the R, G, and B data stored in the D-flip flops D1, 1 to D54, and 48 of the first data storage unit 41 are output to the upper and lower address driving IC units in the form of a data stream. At the same time, the D-flip flops D'1,1 to D'54,48 of the second data storage 42 are inverted from the logic "low" selection signal slct and the clock signal generator. According to the clock signals S1 to S54 outputted from (43), each column is sequentially activated, and 54 bits are performed 48 times through the first to 48th data input terminals IN1 'to IN48' during one horizontal line display period. Latch the corresponding R, G, or B data input over.

As described above, in the data interface circuit of the PDP television according to the present invention, since the demultiplexer unit, which is conventionally located between the memory unit and the data storage unit, is eliminated, the logic is simplified and the number of connection patterns between components is greatly reduced, thereby facilitating chip implementation. There is.

Claims (2)

In a data interface circuit of a PDP television for receiving and storing R, G, B data corresponding to one horizontal line of a plasma display panel from a memory unit, It is composed of N × M D-flip flops arranged in a matrix structure of N (rows) × M (columns), and the D-flip-flops are connected to each other in parallel with the D input terminals for the first to N data. A data storage unit which receives the same data from the memory unit through an input terminal, and clock terminals are connected in parallel to each column to receive the same clock signal through the first to M clock input terminals; A clock input terminal to which the clock pulses are supplied by sequentially supplying clock pulses to the first to M clock input terminals one by one in synchronization with the timing at which R, G, and B data are input in parallel to the first to N data input terminals. And a clock signal generation unit configured to store R, G, and B data input to the first through N data input terminals, respectively, in N D-flip flops connected to the first D-flop flop. The method of claim 1, Two data storage units are provided to simultaneously store data input from the memory unit and output data stored in the data storage unit. One of the two data storage units logically multiplies the clock signal output from the clock signal generator and the selection signal inverted at each start time of one horizontal line display period of the PDP so as to perform data storage. A first AND operation unit for calculating and supplying the first to M clock input terminals of the data storage unit, respectively; The inverse signal of the selection signal and the clock signal output from the clock signal generator are ANDed so that the data is stored in the other one of the two data storage units, and the first to M clock input terminals of the corresponding data storage unit are logically multiplied. And a second logical product operation unit for supplying each of the data interface circuits.