JPH09288466A - Plasma display panel driving method and its driver circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a plasma display panel driving method and its driver circuit capable of reducing an invalid current without contributing at all to light emission of a cell large compared with write-in discharge and making the driver circuit compact. SOLUTION: This circuit is provided with a shift register 1 inputting the data 'causing', 'without causing' the write-in discharge based on the display data and a shift clock, a latch 2 inputting respective outputs of the shift register 1 and outputting the inputs in parallel according to a latch clock and switching elements 3 inputting the outputs of the latch 2 as data signals and controlling on/off, and the circuit is constituted so that when the switching element 3 is turned on, the output becomes a voltage of a single value, and when off, it becomes high impedance.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of driving a DC type plasma display panel among plasma displays and a driving circuit thereof, and more particularly to a pulse memory driving method thereof.

[0002]

2. Description of the Related Art Conventionally, techniques in such a field include:
For example, (1) JP-A-5-119740, (2)
Japanese Patent Application No. 7-
There was one disclosed in No. 169124. Hereinafter, the DC type plasma display panel (hereinafter, DC type PD
It is called P or panel. ) Will be described.

For example, as shown in FIG. 3, a DC type PDP
Includes a front panel substrate 11 and a rear panel substrate 12 that are arranged to face each other, and a plurality of parallel display anodes 13 and auxiliary anodes 14 are formed on the front panel substrate 11. A cathode 15 is formed on the back panel 12, a partition 18 and a priming slit 19 are formed on the rear panel substrate 12, and a display cell is formed in a partition partitioned by the partition 18, that is, at the intersection of the display anode 13 and the cathode 15. 16
However, the auxiliary cell 17 is provided at the intersection of the auxiliary anode 14 and the cathode 15.
Is formed.

The front panel substrate 11 and the rear panel substrate 12 have a cathode 15, a display anode 13 and an auxiliary anode 14.
Are arranged so as to intersect each other with a predetermined gap.
The surroundings of both substrates 11 and 12 are sealed, and a discharge gas is sealed between both substrates. The configuration of the panel having the electrode structure will be described below with reference to FIG.

The DC type PDP shown in this figure has cathodes (cathodes) K1, K2, ... Kn arranged at regular intervals.
, And anodes (display anodes) DA1, DA2, ... DAm intersecting these cathodes at right angles, and auxiliary anodes (auxiliary anodes) SA1, SA2 formed between these anodes at a ratio of 2: 1. ... with SAj. The discharge space formed by the intersection of the anode DAm and the cathode Kn is called a display cell DKnm, and the discharge space formed by the intersection of the auxiliary anode SAj and the cathode Kn is called an auxiliary cell SKnj.

A method of driving such a DC PDP will be described with reference to the timing chart of FIG. Roughly speaking, first, each auxiliary cell is discharged. This is a process of causing the display cells to perform the write discharge based on the display data at the same time as the discharge of the auxiliary cells, and then to maintain the discharge.

Further details will be described. The sustain pulse is applied to the cathode only during the period for sustaining the discharge. Width of sustain pulse t6-t7 (or t9-t
10), the voltage GND-Vk is set to a value for sustaining discharge, and when there is no write discharge, it is not discharged by the sustain pulse, but once discharge occurs by the write discharge, pulse discharge is repeated.

Further, the width t1-t3 (or t4-t6) and the voltage GND-Vs are sequentially applied to the cathode from the upper row.
The scanning pulse of c is applied, and each auxiliary cell is sequentially discharged from above by the scanning pulse and the auxiliary pulse of the auxiliary anode. When writing to the display cell, that is, when writing discharge is generated, the voltage of the anode is maintained at Va and Va-V
Between sc, the write discharge occurs at a sufficient speed due to the coupling (priming) of the display cells by the auxiliary discharge and the excited particles between the auxiliary cells. When the display cell is not written, that is, the writing discharge is not generated, the non-writing pulse is applied with the same width and timing as the scanning pulse. The non-writing pulse is a pulse on the minus side, and the amplitude is Va-Vm.

To stop the sustain discharge of the display cell, the cathode voltage is maintained at the GND level.

[0010]

However, in the above-described conventional DC type PDP driving method, the write discharge is not generated according to the display data, that is, when the non-write pulse is applied to the anode, the non-write pulse is applied. The voltage obtained by adding the voltage amplitude Vsa of the auxiliary pulse applied almost simultaneously with the voltage amplitude Va of the write pulse for the anode, that is, the change in the voltage, is instantaneously applied between the auxiliary anode and the anode. Since a capacitive component exists between the auxiliary anode and the anode and a current proportional to the voltage change amount for a certain unit time flows, a current proportional to Va + Vsa flows between the auxiliary anode and the anode.

This current is so large that it cannot be ignored in comparison with the write discharge, and it is an ineffective current that does not contribute to the light emission of the cell at all. The present invention
To provide a driving method of a plasma display panel and a driving circuit thereof which can eliminate the above-mentioned problems, reduce an ineffective current that does not contribute to light emission of a large cell in comparison with writing discharge, and make the driving circuit compact. With the goal.

[0012]

[Means for Solving the Problems]

[1] A first panel substrate and a second panel substrate are arranged to face each other with a predetermined gap, and a plurality of first electrodes provided on the first panel substrate and the first panel on the second panel substrate. A display device having a plurality of second electrodes provided so as to face and intersect with the electrode of, the first electrode selecting a writing valid state and a writing non-valid state according to a display pattern,
In the driving method of the plasma display panel, wherein the scan pulse is sequentially applied to the second electrode at substantially the same time as the write enabled / disabled state, in the write enabled state, the first electrode is The voltage is set to a dischargeable single-value voltage, and when the writing is ineffective, the first electrode is set to a high impedance state.

[2] A first panel substrate and a second panel substrate are arranged to face each other with a predetermined gap therebetween, and a plurality of first electrodes provided on the first panel substrate and the second panel substrate are provided. A display device having a plurality of second electrodes provided so as to face and intersect the first electrode, wherein the first electrode selects a writing valid state and a writing non-valid state according to a display pattern. Then, in the driving circuit of the plasma display panel, which applies the scanning pulse sequentially applied to the second electrode at substantially the same time as the writing enabled / disabled state, the writing discharge based on the display data is “generated”. , A shift register for inputting data that does not occur and a shift clock, a latch for inputting each output of the shift register, and a parallel output of the input by a latch clock, and a latch for A force is input as a data signal, and a switching element that is controlled to turn on and off is provided. When this switching element is on, the output is a single-value voltage, and when it is off, it is high impedance. Is.

[0014]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a pulse memory drive anode drive circuit diagram of a plasma display panel showing an embodiment of the present invention, FIG. 2 is a drive waveform diagram of the pulse memory drive, and FIG.
2B is an auxiliary anode waveform, FIG. 2C is a cathode waveform, FIG. 2D is an actual anode voltage waveform, and FIG.
(E) shows the actual write current waveform.

As shown in FIG. 2B, the auxiliary anode has t1-t4 (or t4-t7, t7-t10).
The auxiliary pulse is always applied in the cycle. The width of the auxiliary pulse is t1-t2 (or t4-t5, t7-t8), and the amplitude is Vm-Vsa. As shown in FIG. 2C, the rising t1 (or t) of the auxiliary pulse is applied to the cathode.
(4, t7, t10), a scanning pulse is applied almost at the same time to cause auxiliary discharge. The width of the scan pulse is t1-t3 (or t4-t6), and the amplitude is GND-Vsc.

As shown in FIG. 2 (a), the anode is synchronized with ON / OFF of the scan pulse, and according to the display data, the voltage Va is applied when writing discharge is performed, and undefined when writing discharge is not performed. That is, it is set to high impedance. Periods t3-t4, t6-
At t7, the voltage Va is applied as in the writing discharge, and the discharge is maintained by the sustain pulse applied after the cathode scanning pulse. Here, from the actual anode voltage waveform shown in FIG. 2 (d) and the actual write current waveform shown in FIG. 2 (e), write discharge occurs during the period from t1 to t3, that is, the anode voltage is Va. And t4-t
The write discharge is not generated during the period of 6, that is, the anode voltage is maintained at Va, and the write discharge is not generated during the period of t4 to t6. That is, the case where the anode voltage has a high impedance will be described.

During the period from t1 to t3, the anode voltage is maintained at Va and the normal write current flows. During the period from t4 to t6, the anode voltage is high impedance, so t4
Therefore, the anode voltage, which is Va, gradually decreases as the write current flows, and the write discharge is gradually weakened accordingly. Then, when the anode voltage reaches a certain value (Va-ΔV in the figure), the write discharge is extinguished, and as a result, the anode voltage also maintains Va-ΔV thereafter. At t6, the writing period ends and the anode voltage is V
maintained at a. In the case of the present invention, a weak write current flows even when writing is not performed, so that the memory margin characteristic deteriorates more technically, but there is no practical problem. This point will be described later in detail.

Next, a pulse memory driving anode drive circuit showing an embodiment of the present invention will be described with reference to FIG. The shift register 1 is filled with data indicating "writing" and "not writing" based on the display data, and the data is shifted by the shift clock similarly input to the shift register 1.

Each output of the shift register 1 is input to the latch 2 and output in parallel by the latch clock.
The output of the latch 2 is input to the switching element 3 as a data signal and controls the on / off of the switching element 3. When the switching element 3 is on, outputs A1, ... A
m becomes the voltage Va and becomes high impedance when the switching element is off. A transistor or the like can be used as the switching element 3.

A conventional pulse memory drive anode drive circuit has a structure as shown in FIG. That is, in FIG. 6, 101A and 101B are shift registers, 102A and 102B are latches, 103A is a switching element group (S1 to Sm), and 103B is a switching element group (W1 to Wm). When the switching elements S1, ..., Sm (push side switching elements) are switched from on to off by the drive waveform shown in FIG.
The switching elements W1, ... Wm (pull side switching elements) are switched from off to on. On the contrary, when the switching elements S1, ... Sm (push side switching elements) are switched from OFF to ON, the switching elements W1,
... Wm (pull side switching element) is switched from on to off. This switching usually takes several hundred ns,
Meanwhile, the current is Vm from Va through the switching element.
Flows to This current is generally called switching current.

On the other hand, according to the present invention, as shown in FIG. 1, in the pulse drive driving anode drive circuit, from the drive waveform of FIG. No switching current flows because it has two simple circuit configurations. In addition, the current at the time of voltage change due to the above-mentioned auxiliary anode and the capacitance component between the anodes does not change the auxiliary voltage from Vm to Vsa as compared with the conventional one, but the change of the anode voltage does not cause the write discharge. In this case, since the anode has a high impedance, the change in voltage is lower than in the conventional case. Therefore, the reactive current that does not contribute to the light emission of the panel is also reduced.

As mentioned above, according to the driving method of the DC type PDP of the present invention, as a result, the anode driving circuit can have a simple structure in which one anode driver output has one switching element. It also leads to downsizing. Next, the memory margin will be described. Figure 7
Is a plot of the minimum sustain voltage and the maximum sustain voltage (V) with respect to the write voltage (V) in the conventional and pulse memory driving according to the present invention. Here, the minimum sustaining voltage is a voltage at which all cells start sustaining discharge, and the maximum sustaining voltage is a voltage immediately before starting one-dot erroneous lighting.

A value obtained by subtracting the minimum sustain voltage from the maximum sustain voltage is called a memory margin. FIG. 8 is a graph in which the vertical axis represents the value obtained by subtracting the minimum sustain voltage from the maximum sustain voltage of each write voltage in FIG. 7, that is, the memory margin (V) and the horizontal axis represents the write voltage (V). . As shown in FIG. 7, when the write voltage is low, the minimum sustaining voltage is high in both the prior art and the present invention, and becomes a certain value as the write voltage increases. At a high write voltage, the minimum sustaining voltage of the present invention is higher than that of the conventional one. Further, the maximum sustaining voltage has a constant value in the prior art and the present invention when the writing voltage is small, and is smaller in the present invention than the conventional one when the writing voltage is large. Overall,
The maximum sustaining voltage of the present invention is smaller than that of the conventional one.

As a result of FIG. 7, the memory margin becomes an upwardly convex curve as shown in FIG. The memory margin of the present invention is smaller than that of the conventional one.
The larger the memory margin, the easier it is to set the voltage, which is also advantageous for the voltage fluctuation due to continuous lighting of the panel.
If the memory margin is 20 V or more, it is sufficient for voltage setting and voltage fluctuation. Therefore, the present invention can sufficiently endure the memory margin and has no problem.

It should be noted that the present invention is not limited to the above-described embodiment, and various modifications are possible based on the spirit of the present invention, and these are not excluded from the scope of the present invention.

[0026]

As described above, according to the present invention, the following effects can be obtained. (1) According to the first aspect of the invention, the switching circuit does not flow because one push-side switching element has a simple circuit configuration for one output of the anode driver.

Further, the current when the voltage changes due to the capacitance component between the auxiliary anodes and the anode is the same as the conventional one because the auxiliary voltage changes from Vm to Vsa, but the change in the anode voltage causes the write discharge. If it does not occur, the voltage change is lower than in the conventional case because the anode has a high impedance. Therefore, the reactive current that does not contribute to the light emission of the panel is also reduced.

(2) According to the invention described in claim 2, in addition to the effect of the above (1), the anode drive circuit can also have a simple configuration in which one anode driver output has one switching element. The circuit can be made compact.

[Brief description of drawings]

FIG. 1 is a pulse memory drive anode drive circuit diagram of a plasma display panel showing an embodiment of the present invention.

FIG. 2 is a drive waveform diagram of a pulse memory drive of a plasma display panel showing an embodiment of the present invention.

FIG. 3 is a schematic configuration diagram of a conventional DC PDP.

FIG. 4 is a cell array diagram of a conventional DC PDP.

FIG. 5 is a drive waveform diagram (timing chart) for driving a pulse memory of a conventional DC PDP.

FIG. 6 is a pulse drive driving anode drive circuit diagram of a conventional DC PDP.

FIG. 7 is a diagram showing values of a minimum sustain voltage and a maximum sustain voltage with respect to a write voltage in a conventional pulse memory drive and a pulse memory drive according to the present invention.

8 is a diagram in which the vertical axis represents the value obtained by subtracting the minimum sustain voltage from the maximum sustain voltage of the individual write voltages in FIG. 7, that is, the vertical axis represents the write voltage.

[Explanation of symbols]

 1 shift register 2 latch 3 switching element

 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Atsushi Takahashi 1-7-12 Toranomon, Minato-ku, Tokyo Oki Electric Industry Co., Ltd.

Claims (2)

[Claims] 1. A first panel substrate and a second panel substrate are arranged to face each other with a predetermined gap therebetween, and a plurality of first electrodes provided on the first panel substrate and the second panel substrate are provided on the second panel substrate. A display device having a plurality of second electrodes provided so as to oppose and intersect with a first electrode, wherein the first electrode selects a writing valid state and a writing non-valid state according to a display pattern. A driving method of a plasma display panel, wherein scanning pulses are sequentially applied to the second electrode at substantially the same time as the writing enabled / disabled state, wherein the first electrode is used in the writing enabled state. Is set to a single voltage capable of discharging, and the first electrode is set to a high impedance state when the writing is ineffective, a driving method of a plasma display panel. 2. A first panel substrate and a second panel substrate are arranged to face each other with a predetermined gap therebetween, and a plurality of first electrodes provided on the first panel substrate and the second panel substrate are provided on the second panel substrate. A display device having a plurality of second electrodes provided so as to oppose and intersect with a first electrode, wherein the first electrode selects a writing valid state and a writing non-valid state according to a display pattern. In the drive circuit of the plasma display panel, a scan pulse is sequentially applied to the second electrode at substantially the same time as the write valid / invalid state, (a)
A shift register for inputting data and a shift clock that "write" or "do not write" the writing discharge based on the display data; and (b) each output of the shift register is input,
The latch includes a latch whose input is output in parallel by a clock, and (c) a switching element whose output is input as a data signal and whose on / off is controlled. (D) The switching element is on. A driving circuit for a plasma display panel, wherein the first electrode is driven so that the output has a single voltage in the case and has a high impedance in the case of off.