KR100481324B1 - Driving apparatus and method of plasma display panel - Google Patents

Abstract

The present invention provides a driving apparatus of a plasma display panel to improve the light emitting efficiency by shortening the interval between driving pulses by reducing the time for loading a video signal to the IC by improving the structure of a driving IC (Integrated Circuit) and It is about a method.

In the conventional drive IC structure of AC PDP, the turn-on time of the cells in the panel should be shortened to reduce the period of the sustain pulse, but if the width of the sustain pulse and the scan pulse are excessively reduced, the discharge of the PDP cell becomes unstable. There is a problem in that the light emission efficiency is lowered since the width of the pulse cannot be reduced below a predetermined time required by.

In order to solve this problem, the present invention provides an X, Y, Z driver IC structure for driving a PDP, wherein the X, Y, Z driver ICs sequentially shift n-bit data in synchronization with a clock input to the other side. And a latch means for latching the m-bit data output from the shift register to a clock input to the other side to minimize the data load time.

Description

Driving apparatus and method of plasma display panel

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving apparatus and method of a plasma display panel, and more particularly, to shorten the interval between driving pulses by shortening the time required to load a video signal to an IC by improving a driving IC (Integrated Circuit) structure. The present invention relates to a driving apparatus and a method of a plasma display panel for improving efficiency.

As the modern society is called the information society, the importance of the display device is increasing with the development and spread of the information processing system, and the types thereof are gradually diversifying.

CRT (Cathode Ray Tube), which has been used most often as a display device, has various problems such as large size, high operating voltage, and distortion of display. Recently, research and development of various flat panel display devices having a matrix structure have been actively conducted.

Among the flat panel display devices, a plasma display panel (hereinafter, referred to as PDP), which is a light emitting device, is used to display a moving image or a still image by using a gas discharge phenomenon inside the PDP.

Meanwhile, a circuit diagram of one of the plasma display apparatuses according to the related art will be described with reference to FIGS. 1, 2, 3, and 4.

First, as shown in FIG. 1, a three-electrode surface discharge PDP 10 composed of M × N pixels having a matrix form as one of AC PDPs, and R (Red) and G (Green) input from the outside. And a microcomputer 120 for digitizing B (Blue) analog image data and outputting R, G and B digital image data, and outputting various control signals according to the R, G and B digital image data and an external signal, and the microcomputer. Memory unit 130 for storing the R, G, B digital image data output from the frame 120, frame-by-color, bit-by-bit, and the M Y sustain electrode line in accordance with the control signal of the microcomputer 120 ( Y ₁ ~Y _M) and the Y sustain driver 140 for supplying a first drive pulse, the M Z sustain electrode lines according to a control signal of the microcomputer (120) (Z ₁ ~Z _M) corresponding to each of the Z sustain driver 150 for supplying a second drive pulse train in common to the above, and The corresponding R, G, and B digital image data of the N pixels (R, G, and B cells) of the Y and Z sustain electrode lines currently scanned among the _M Y and Z sustain electrode lines Y _{1 to} Z _M are The first and second address drivers 161 and 162 are inputted from the memory unit 130 and supplied to the N R, G and B address electrode lines R _{1 to} B _N.

The three-electrode surface discharge PDP 10 has a front substrate 11 that is a display surface of an image as shown in FIGS. 2 and 3, and a rear surface disposed parallel to the front substrate 11 with a predetermined distance therebetween. 3N + 1 partition walls 13 arranged between the front substrate 11 and the front substrate 11 and the back substrate 12 to form a discharge space, and the back substrate 12 of the front substrate 11. M Y and Z sustain electrode lines Y ₁ , Z ₁ , Y ₂ , Z ₂ ,..., Y _M-1 , Z _M-1 , which are alternately arranged to be orthogonal to the partition 13 on the opposite side to the partition wall 13. Y _M , Z _M and a plurality of Y and Z sustain electrode lines (Y _{1 to} Z _M ) formed on the rear substrate 12 between the partition walls 13 and in parallel with the partition walls 13. N R, G, and B address electrode lines causing discharge (R ₁ , G ₁ , B ₁ , R ₂ , G ₂ , B ₂ , ..., R _N-1 , G _N-1 , B _N-1 , R _N , G _N , B _N ), the back substrate 12, the partition 13, and the R, G, and B address electrode lines R _{1 to} B _{N in} the discharge space, respectively, to discharge each cell. It consists of N R, G, B phosphor layers 14a, 14b, 14c which respectively emit red, green, and blue visible light.

The M Y and Z sustain electrode lines (Y _{1 to} Z _M ) and the N R, G, and B address electrode lines (R _{1 to} B _N ) are M × N pixels R, G, and B in matrix form. Cell), and the M Z sustain electrode lines Z _{1 to} Z _M are all connected in parallel.

In addition, a dielectric layer 15 is formed on the M Y and Z sustain electrode lines Y _{1 to} Z _M to limit the discharge current when each cell is discharged. The dielectric layer 15 is formed upon discharge of each cell. A magnesium oxide (MgO) protective film 16 is formed to protect the M Y and Z sustain electrode lines Y _{1 to} Z _M and the dielectric layer 15 from sputtering. Discharge gas is injected.

The Y sustain driver 140 includes a plurality of integrated ICs, and output pins of the respective driving ICs are connected to _M Y sustain electrode lines Y _{1 to} Y _M in one-to-one correspondence (M pieces). Y and the sustain electrode lines (Y ₁ ~Y _M) should be a total of M number of drive IC output pins due to the independent operation of the gain), Z sustain driver 150 is composed of one driving IC 1 outputs of the pin interconnected in parallel the M Z sustain electrode lines it is connected to the (Z ₁ ~Z _M).

In addition, the first address driver 161 may include the odd-numbered address electrode lines R ₁ , B ₁ , G ₂ ,... R _{N −} among the _N R, G, and B address electrode lines R _{1 to} B _N. R, G, and B digital image data are respectively supplied to ₁ , B _N-1 , and G _N , and the second address driver 162 is an even-numbered address electrode line G ₁ , R ₂ , B _2. R, G, and B digital image data are supplied to G _N-1 , R _N , B _N ) to lower the addressing frequency.

The conventional plasma display device configured as described above has a 2 ^X gray scale image on a three-electrode surface discharge PDP according to the ADS subfield (Addressing and Display System sub-field) method, which is one of several driving methods. The following describes the process of displaying.

The ADS subfield method is driven by dividing one frame into a plurality of subfields according to the grayscale to be implemented. Each subfield is driven by being divided into a reset period, an address period, and a sustain period.

Here, the address periods of the respective subfields are equally allocated, but the sustain periods are bit weights of the R, G, and B digital image data supplied through the _N R, G, and B address electrode lines R _{1 to} B _N. Since it is differently assigned to each other, the gradation of the image can be realized by combining each subfield (using the integration effect of the eyes).

For example, in order to realize 2 ^X gradation, R, G, and B analog image data are digitized into X bits of R, G, and B digital image data (lowest B ₁ to highest B _X ), and one frame is X sub The fields SF _{1 to} SF _X are divided, and the sustain period of each subfield SF _{1 to} SF _X is 2 ⁰ : 2 ¹ : 2 ² :. 2 ^X-2 : 2 ^X-1 is assigned.

First, the microcomputer 120 digitizes R, G, and B analog image data input from the outside, and outputs X-bit R, G, and B digital image data (B _{1 to} B _X ), and the R, G, B Various control signals are output in accordance with digital image data and external signals.

In this case, the R, G, and B digital image data output from the microcomputer 120 are stored in the memory unit 130 for each frame, color, and bit.

Thereafter, in the address period of each subfield SF _{1 to} SF _X , the Y sustain driver 140 and the Z sustain driver 150 are all Y and Z sustain electrode lines Y ₁ according to the control signal of the microcomputer 120. Supply erase pulses in one step, write pulses in two steps, and erase pulses in three steps to ˜Z _M ), respectively, on the N R, G, and B address electrode lines R _{1 to} B _N , respectively. provided R, G, B phosphor layers (14a, 14b, 14c) to form a wall charge on the surface to lower the address discharge voltage of each cell is performed after, M of Y sustain electrode lines to step 4 (Y ₁ ~Y _M ) Sequentially supply scan pulses of a predetermined voltage.

Z in the M, the polarity and the scan pulse opposite to the sustain electrode lines (Z ₁ ~Z _M) during the sequential scan pulse is supplied to the M Y sustain electrode lines (Y ₁ ~Y _M) in said step 4 a pulse voltage By supplying this, the M Y and Z sustain electrode lines Y _{1 to} Z _M are sequentially scanned one pair (Y and Z sustain electrode line pairs).

In addition, in step 4, the first and second address drivers 161 and 162 are configured to have N R, G, and B address electrodes while the M Y and Z sustain electrode lines Y _{1 to} Z _M are sequentially scanned in pairs. Supplying the corresponding address pulses (1 bit value of the R, G, B digital image data) synchronized with the scan pulses to the lines R _{1 to} B _N of each cell supplied with a logic " high " The address discharge is caused to occur inside the discharge space.

In this case, the first and second address drivers 161 and 162 may be configured as B ₁ → SF ₁ of R, G, and B digital image data B _{1 to} B _X of X bits corresponding to each of R, G, and B cells. , B ₂ → SF ₂ ,. It is supplied to B _X-1 → SF _X-1 and B _X → SF _X respectively.

In addition, when an address discharge occurs in the discharge space of each cell, the discharge gas injected into the discharge space is ionized by electrons and ions to form a plasma state, and particles excited by collision in the plasma state fall to the bottom state. In addition, each of the R, G, and B phosphor layers 14a, 14b, and 14c emits ultraviolet rays, and each of the R, G, and B phosphor layers 14a, 14b, and 14c is excited by the collision of ultraviolet rays. Each emits blue visible light, and the red, green, and blue visible light are emitted to the outside through the front substrate 11.

On the other hand, when the address periods of the respective subfields SF _{1 to} SF _X are completed, the Y and Z sustain drivers 140 and 150 perform M Y and Z sustain electrode lines Y ₁ to Z according to the control signal of the microcomputer 120. The first and second sustain pulses are supplied to Z _M ) to maintain the discharge and light emission of each of the R, G and B cells during the period in which the first and second sustain pulses are supplied (sustain period).

That is, as illustrated in FIG. 4, scan pulses are sequentially supplied using a shift register, and then sustain pulses of a predetermined interval are simultaneously supplied to maintain discharge and emission of each cell.

Here, Tm is a time required for loading a video signal.

At this time, each subfield SF ₁ to SF _X has SF ₁ : SF ₂ :. SF _X-1 : SF _X = 2 ⁰ : 2 ¹ :... 2 ^X-2 : Sustain pulses in proportion to 2 ^X-1 are supplied.

When the sustain period of the last subfield SF _X is completed through the above process, a grayscale image of one frame is displayed on the three-electrode surface discharge PDP 10.

However, the X, Y, Z driving IC structure of the conventional AC PDP has to reduce the turn-on time of the cells in the panel in order to reduce the period of the sustain pulse, but if the width of the sustain pulse and the width of the scan pulse are excessively reduced, the PDP cell Since the discharge becomes unstable, the width of the pulse cannot be reduced to less than a predetermined time required for discharge, and thus there is a problem that the luminous efficiency is lowered.

Therefore, the present invention improves the structure of a driving IC (Integrated Circuit) to reduce the time to load the video signal to the IC (IC) to shorten the interval between the driving pulse to improve the luminous efficiency of the plasma display panel drive device And to provide a method.

The technical means of the present invention for achieving the above object is, in the X, Y, Z drive IC structure for driving a PDP, the X, Y, Z drive IC is a n-bit data input to the clock input to the other side A shift register for synchronously shifting and outputting m-bit data and latching means for latching the m-bit data output from the shift register to a clock input to the other side to minimize data load time.

In addition, the method of the present invention for achieving this object is a first step of storing n bits of data in advance in the time domain of the sustain pulse period for the number of scans required in one period, and n previously stored in the first step The second step is to shorten the sustain period by shifting the bit data sequentially in the scan pulse period generated by the sustain pulse to reduce the time for loading the n bit data.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 5 is a block diagram of an X, Y, and Z driving IC for driving a PDP according to the present invention, in which n-bit data input is sequentially shifted in synchronism with a clock input to the other side to obtain m-bit data. The shift register 101 to be output is comprised and the latch part 102 which latches the m-bit data output from the said shift register 101 to the clock input to the other side, and minimizes data load time.

Referring to Figures 5 and 7 attached to the operation and effect of the present invention configured as described above are as follows.

First, a shift register of n × m bits is created to store all the required scans in one period in a time domain with sufficient margin, and then scan sequentially.

That is, the driving device of the plasma display panel includes a horizontal electrode controller (not shown) for outputting inputted n-bit data, and a driving unit (not shown) for driving the horizontal electrode of the plasma display panel (not shown). It consists of.

The n-by-m-bit shift register in the driving unit sequentially shifts n-bit data in synchronization with a clock input to the other side and stores the m-bit data in advance.

At this time, the interval receiving m-bit data is a time corresponding to tl as shown in FIG.

And, the point in time of the scan pulse section is the time for the driving unit to send data to the plasma display panel for scanning.

On the other hand, since ☆ time of the left lighting pulse section has a time of tf, there is enough time to load data, but ☆ time of the scan pulse section has a short time to load data, so the bottleneck that determines the sustain period is determined. Becomes

Therefore, if you receive the data to be scanned by n × 5 in advance for tl and store it in an area with sufficient margin of the sustain pulse period, and then sequentially shift the scan pulse period generated by the sustain pulse, tm as in the conventional method. This eliminates the time to load and scatter n bits of data while the Y and Z drive ICs are equally feasible.

In this way, the sustain period is shortened and the luminous efficiency can be improved.

On the other hand, the X driving IC reduces the loading time of the video signal to the driving IC to shorten the sustain period, thereby improving luminous efficiency. As shown in FIG. The video signal is loaded and output at the time of the data pulse period in synchronization with the scan pulse generated by the sustain pulse.

Thus, the tl time must be at least greater than the time for loading the video signal.

The proposed scheme saves the video signal in advance in the predetermined time domain, i.e., tm interval, before applying the data pulse as many times as necessary, and then synchronizes the stored video signal with the scan pulse generated by the sustain pulse. If the shift is sequentially performed during the data pulse period, the time required to load the video signal at tl time is reduced, thereby shortening the sustain period to improve luminous efficiency.

As described above, the present invention improves the structure of the driving IC to shorten the time for loading a video signal into the driving IC, thereby shortening the interval between driving pulses, thereby reducing the driving time of the entire panel. It has the effect of improving the noise and removing various noises.

1 is a block diagram showing one configuration of a conventional plasma display device;

FIG. 2 is a side cross-sectional view of one pixel of the three-electrode surface discharge plasma display panel (hereinafter, abbreviated as three-electrode surface discharge PDP) shown in FIG. 1;

3 is an overall electrode structure diagram of the three-electrode surface discharge PDP shown in FIG.

4 is a time chart of a drive signal supplied to a scan electrode according to the prior art;

Fig. 5 is a schematic diagram of an X, Y, Z driving IC for driving a PDP applied to the present invention.

6 is a time chart of a driving signal supplied to a scan electrode;

(A) is a driving pulse waveform diagram according to the prior art,

(B) is a time chart of the drive signal proposed in the present invention.

7 is a time chart of the data drive signal proposed in the present invention.

*** Explanation of symbols for the main parts of the drawing ***

101: shift register 102: latch portion

Claims (3)

In the X, Y, Z drive IC structure for driving the PDP, The X, Y and Z driving ICs include a shift register for sequentially shifting n-bit data input in synchronization with a clock input to the other side and outputting m-bit data; And latching means for latching m-bit data output from the shift register to a clock inputted to the other side to minimize data load time. A first step of storing n bits of data in advance in the time domain of the sustain pulse period for as many scans as necessary in one period; The second step is to shorten the sustain period by reducing the time for loading the n-bit data by sequentially shifting the n-bit data previously stored in the first step in the scan pulse period generated by the sustain pulse Method of driving a plasma display panel, characterized in that. A first step of storing R, G, and B data (n bits) in advance in a predetermined time region before applying the data pulse as many times as the number of data pulses required for one cycle; Load the R, G, B data (n bits) by sequentially shifting the R, G, B data (n bits) previously stored in the first step in a data pulse period in synchronization with the scan pulse generated by the sustain pulse. And a second step of reducing the time required to shorten the sustain period.