KR19990069782A - Apparatus and method for driving a plasma display panel - Google Patents

Abstract

The present invention relates to a driving apparatus and a driving method of a plasma display panel in which a driving IC (Integrated Circuit) structure is improved to shorten a time for loading a video signal into an IC, ≪ / RTI >

In the driving IC structure of the conventional AC PDP, the turn-on time of the cells in the panel is reduced in order to reduce the period of the sustain pulse. However, when the width of the sustain pulse and the width of the scan pulse are excessively reduced, the discharge of the PDP cell becomes unstable, The width of the pulse can not be reduced below a predetermined time required for the light emission efficiency.

To solve this problem, the present invention provides an X, Y, and Z drive IC structure for driving a PDP, wherein the X, Y, and Z drive ICs synchronize the input n-bit data with a clock input to the other, And latch means for latching the m-bit data output from the shift register to a clock input to the other side to minimize the data load time.

Description

Apparatus and method for driving a plasma display panel

The present invention relates to an apparatus and a method for driving a plasma display panel. More particularly, the present invention relates to an improved driving IC (Integrated Circuit) structure to reduce the time for loading a video signal into an IC, And more particularly, to an apparatus and a method for driving a plasma display panel.

Since Hyundai is called as an information society, the importance of display devices is increasing with the development and spread of information processing systems, and their kinds are also diversified.

The CRT (Cathode Ray Tube), which has been used most frequently as a display device in the past, has various problems such as a large size, a high operating voltage, and display distortion, Recently, various flat display devices having a matrix structure have been actively developed and developed.

An apparatus for displaying a moving image or a still image by using a gas discharge phenomenon inside the PDP, which includes a plasma display panel (hereinafter abbreviated as PDP), which is an emission type device among the above-mentioned flat display devices, is referred to as a plasma display device.

Meanwhile, a configuration circuit diagram of one of the plasma display devices according to the related art will be described with reference to FIGS. 1, 2, 3, and 4. FIG.

First, as shown in FIG. 1, one of the AC PDPs is a three-electrode surface discharge PDP 10 having M × N pixels in a full screen form, and R (Red), G (Green) A microcomputer 120 for outputting R, G and B digital image data by digitizing B (Blue) analog image data and outputting various control signals according to the R, G and B digital image data and an external signal; A memory 130 for storing the R, G, and B digital image data output from the image sensing unit 120 for each frame, each color, and each bit; and a control unit 130 for controlling the M Y sustain electrode lines Y ₁ ~Y _M) and the Y sustain driver 140 for supplying a first drive pulse, the M Z sustain electrode lines according to a control signal of the microcomputer (120) (Z ₁ ~Z _M) corresponding to each of the A Z sustain drive unit 150 for supplying a second drive pulse string commonly to the Z sustain drive unit 150, G, and B digital image data of N pixels (R, G, and B cells) constituted by the Y and Z sustain electrode lines to be currently scanned among the _M Y and Z sustain electrode lines Y _{1 to} Z _M And first and second address driver units 161 and 162 for receiving the signals from the memory unit 130 and supplying the _N address signals to the _N R, G and B address electrode lines R _{1 to} B _N.

2 and 3, the three-electrode surface discharge PDP 10 includes a front substrate 11, which is a display surface of an image, and a rear substrate 11, which is parallel to the front substrate 11, A plurality of barrier ribs 13 arranged between the front substrate 11 and the rear substrate 12 to form discharge spaces and a plurality of barrier ribs 13 formed between the front substrate 11 and the rear substrate 12, And Y sustain electrode lines Y ₁ , Z ₁ , Y ₂ , Z ₂ , ..., Y _M-1 , Z _M-1 , and Y _{M that} are alternately arranged on the opposite surfaces of the barrier ribs 13, Y _M, Z _M), and each of the partition wall 13 with the rear substrate 12 is formed on a parallel with the partition wall 13, the M and Y and Z sustain electrode lines (Y ₁ ~Z _M) between N number of R, G, B address electrode lines, causing a discharge _{(R 1, G 1, B} 1, R 2, G 2, B 2, ..., R N-1, G N-1, B N-1, R _N , G _N , and B _N ), a rear substrate 12, a barrier rib 13, and R, G, and B Phosphor layers 14a, 14b, and 14c formed on the address electrode lines R _{1 to} B _N , respectively, and emit red, green, and blue visible light, respectively, upon discharge of each cell .

The M and Y sustain electrode lines Y _{1 to} Z _M and the N R, G, and B address electrode lines R _{1 to} B _{N are} arranged in a matrix of M × N pixels (R, G, and B) Cell, and the M Z sustain electrode lines Z _{1 to} Z _M are all connected in parallel.

A dielectric layer 15 is formed on the Y and Z sustain electrode lines Y _{1 to} Z _M to limit the discharge current during discharge of each cell. On the dielectric layer 15, A magnesium oxide (MgO) protective film 16 for protecting the M Y and Z sustain electrode lines Y _{1 to} Z _M and the dielectric layer 15 from sputtering is formed. Inside each discharge cell, A discharge gas is injected.

The Y sustain driver 140 is composed of a plurality of driving ICs (Integrated Circuit), and the output pins of the driving ICs are connected in one-to-one correspondence to the _M Y sustain electrode lines Y _{1 to} Y M Y and the sustain electrode lines (Y ₁ ~Y _M) should be a total of M number of drive IC output pins due to the independent operation of the gain), Z sustain driver 150 is composed of one driving IC 1 outputs of the pin And are connected to M Z sustain electrode lines (Z _{1 to} Z _M ) connected in parallel to each other.

In addition, the first address driver 161 applies the odd-numbered address electrode lines R ₁ , B ₁ , G ₂ , ..., R _{N- 1} among the _N R, G, and B address electrode lines R _{1 to} B _N , _1, B _N-1, G _N), the R, G, supplies a B digital image data and the second address driver 162, an address electrode lines positioned in the even-numbered (G _1, R _2, B ₂ in , ... G _N-1 , R _N , and B _N ), respectively, to lower the addressing frequency.

The image of the conventional ADS sub-field of one of a number of driven plasma display apparatus according to the technique (Addressing and Display System sub-field ) three-electrode surface, depending on how the discharge 2 ^X gradation on PDP image (gray scale) constructed as described above A description will be given of the process of displaying the information.

In the ADS subfield method, one frame is divided into a plurality of subfields to be driven according to gray levels to be implemented. Each subfield is driven by a reset period, an address period and a sustain period.

Here, the address periods of all the subfields are all assigned equally, but the sustain period is the same as the bit period of the R, G, B digital image data supplied through the _N R, G, and B address electrode lines (R _{1 to} B _N ) , It is possible to realize the gradation of the image by using the combination of the subfields (using the integration effect of the eyes).

For example, R, G, and B analog image data are digitized into R, G, and B digital image data (lowest B ₁ to highest B _x ) of X bits for the implementation of 2 ^X gradations, field is divided into (SF ₁ ~SF _X), the sustain period of each subfield (SF ₁ ~SF _X) is 2 ^0: 2 ^1: 2 ^2: ... 2 ^X-2 : 2 ^X-1 .

First, the microcomputer 120 digitizes R, G, and B analog image data input from the outside to output X-bit R, G, and B digital image data (B _{1 to} B _X ) And outputs various control signals in accordance with digital image data and an external signal.

At this time, the R, G, and B digital image data output from the microcomputer 120 are stored in the memory unit 130 by frame, color, and bit.

The Y sustain drive unit 140 and the Z sustain drive unit 150 drive the Y and Z sustain electrode lines Y _{1 and} Y ₁ according to a control signal of the microcomputer 120 in the address period of each of the subfields SF _{1 to} SF _X , ~Z _M) in sseoneotgi to erase (erase) pulse, step 2, step 1 (write) pulse, and the erasing pulse supplied to the third step the N R, G, B, respectively on the address electrode lines (R ₁ ~B _N) Wall charges are formed on the surfaces of the formed R, G, and B phosphor layers 14a, 14b, and 14c to lower the address discharge voltage of each cell to be performed thereafter, and M sustain electrode lines Y _{1 to} Y _M The scan pulse of a predetermined voltage is sequentially supplied.

Z in the M, the polarity and the scan pulse opposite to the sustain electrode lines (Z ₁ ~Z _M) during the sequential scan pulse is supplied to the M Y sustain electrode lines (Y ₁ ~Y _M) in said step 4 a pulse voltage The M Y and Z sustain electrode lines Y _{1 to} Z _M are sequentially scanned by a pair of Y and Z sustain electrode line pairs.

In addition, in the fourth step the M and Y and Z sustain electrode lines (Y ₁ ~Z _M) during the scanning by one pairs in sequence the first and second address driving unit 161 and 162 includes N R, G, B address electrode (1 bit value of R, G, and B digital image data) synchronized with the scan pulse to the lines R _{1 to} B _N and supplies the address pulse So that an address discharge is generated within the discharge space.

At this time, the first and second address driving units 161 and 162 output B _{1 to} SF ₁ among the R, G, and B digital image data (B _{1 to} B _X ) of X bits corresponding to the respective R, , B ₂ ? SF ₂ , ... B _X-1 SF _X-1 , and B _X SF _X , respectively.

When an address discharge is generated in the discharge space of each cell, the discharge gas injected into the discharge space is ionized into electrons and ions to become a plasma state. In the plasma state, the particles excited by collision fall into a ground state The phosphor layers 14a, 14b, and 14c emit ultraviolet rays toward the respective R, G, and B phosphor layers 14a, 14b, and 14c while being excited by ultraviolet rays, Blue, and blue visible light are emitted to the outside through the front substrate 11. The red,

On the other hand, each of the sub-fields (SF ₁ ~SF _X) when the address period is completed, Y and Z, the sustain driver 140 and 150 are lines of Y and the sustain electrode Z M in response to a control signal of the microcomputer 120 of the (Y ₁ ~ Z _M ), and the discharge and light emission of each of the R, G, and B cells are maintained during the period (the sustain period) during which the first and second sustain pulses are supplied.

That is, as shown in FIG. 4, a scan pulse is sequentially supplied using a shift register, and a sustain pulse having a constant interval is simultaneously supplied to sustain discharge and light emission of each cell.

Here, Tm is a time required for loading a video signal.

At this time, in each of the subfields SF ₁ to SF _X , SF ₁ : SF ₂ : ... SF _X-1 : SF _X = 2 ⁰ : 2 ¹ : ... 2 ^X-2 : 2 ^X-1 .

After the sustain period of the last sub-field SF _X is completed through the above-described process, a gray-scale image of one frame is displayed on the three-electrode surface discharge PDP 10.

However, if the width of the sustain pulse and the width of the scan pulse are excessively reduced, it is necessary to reduce the turn-on time of the cells in the panel in order to reduce the period of the sustain pulse. The width of the pulse can not be reduced below a predetermined time required for the discharge, resulting in a problem that the luminous efficiency is lowered.

Therefore, the present invention improves the driving IC (Integrated Circuit) structure to reduce the time for loading a video signal into an IC, And a method thereof.

According to an aspect of the present invention, there is provided an X, Y, and Z driving IC structure for driving a PDP, wherein the X, Y, and Z driving ICs receive n-bit data, And latch means for latching the m-bit data output from the shift register to a clock input to the other side to minimize the data load time.

According to another aspect of the present invention, there is provided a method for driving a plasma display panel, comprising: a first step of storing n-bit data in a time domain of a sustain pulse period as many times as necessary for one scan period; Bit data is sequentially shifted in a scan pulse period generated by the sustain pulse to reduce the time for loading the n-bit data, thereby shortening the sustain period.

1 is a block diagram showing a configuration of one of conventional plasma display devices.

FIG. 2 is a side cross-sectional view of one pixel of the three-electrode surface discharge plasma display panel (hereinafter abbreviated as a three-electrode surface discharge PDP) shown in FIG.

3 is an overall electrode structure view of the three-electrode surface discharge PDP shown in FIG.

FIG. 4 is a time chart of a driving signal supplied to a scan electrode according to a conventional technique. FIG.

5 is a configuration diagram in an X, Y, and Z drive IC for driving a PDP according to the present invention;

6 is a time chart of a driving signal supplied to the scan electrode,

(A) is a drive pulse waveform diagram according to the prior art,

(B) is a time chart of the drive signal proposed in the present invention.

7 is a time chart of the data driving signal proposed in the present invention.

DESCRIPTION OF THE REFERENCE SYMBOLS

101: shift register 102: latch unit

Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 5 is a block diagram of an X, Y, and Z driving IC for driving a PDP according to the present invention. The input n bit data is sequentially shifted in synchronization with a clock input to the other side, And a latch unit 102 for latching the m-bit data output from the shift register 101 to a clock input to the other side to minimize a data load time.

The operation and effect of the present invention will be described with reference to FIGS. 5 and 7. FIG.

First, a shift register of n × m bits is created, and all of the necessary number of scans within one cycle are stored in a time region in which a margin is sufficient, and sequentially scanned.

That is, the driving apparatus of the plasma display panel includes a horizontal electrode control unit (not shown) for outputting the input n-bit data and a driving unit (not shown in the figure) for driving the horizontal electrodes of the plasma display panel .

An n × m bit shift register in the driving unit sequentially shifts n-bit data in synchronization with a clock input to the other side, and stores the m-bit data in advance.

At this time, the period of receiving the m-bit data is a time corresponding to tl as shown in FIG.

The time point of the scan pulse interval is a time required for the driving unit to scan the data to the plasma display panel.

On the other hand, since the time point of the lighting pulse section on the left side is tf, there is sufficient time to load data, but since the data loading time is short in the scan pulse section, the bottleneck, which determines the sustain cycle, .

Therefore, if data to be pre-scanned by n x 5 during tl is received and stored in advance in a sufficient margin of the sustain pulse period, and then shifted sequentially in the scan pulse period generated by the sustain pulse, (Here, the Y and Z drive ICs can be implemented in the same way).

In this case, the sustain period is shortened and the luminous efficiency can be improved.

As shown in FIG. 7, in the conventional method, the X driving IC reduces the loading time of the video signal to the driving IC to shorten the sustain period to improve the luminous efficiency. In the conventional method, The video signal is loaded and is output at the time point of the data pulse period synchronized with the scan pulse generated by the sustain pulse.

Therefore, the time tl must be at least greater than the time for loading the video signal.

In the proposed method, a video signal is pre-stored in a predetermined time period before a data pulse is applied, that is, a tm period, and then the stored video signal is synchronized with a scan pulse generated by a sustain pulse The time for loading the video signal at the time tl is shortened to shorten the sustain period to improve the luminous efficiency.

As described above, the present invention improves the structure of the driving IC to reduce the time for loading a video signal into the driving IC, thereby shortening the interval between driving pulses to reduce the driving time of the entire panel, And it is possible to remove various noises.

Claims (3)

In an X, Y and Z drive IC structure for driving a PDP, The X, Y, and Z driving ICs include a shift register that sequentially shifts input n-bit data in synchronism with a clock input to the other and outputs the m-bit data, And latch means for latching data of m bits output from the shift register to a clock input to the other side to minimize data load time. A first step of storing n bits of data in advance in a time domain of a sustain pulse period by a necessary number of scans in one cycle, And a second step of sequentially shifting n-bit data previously stored in the first step to a scan pulse period generated by a sustain pulse to reduce the time for loading the n-bit data to shorten the sustain period And driving the plasma display panel. A first step of storing R, G and B data (n bits) in advance in a predetermined time region before applying a data pulse for the number of data pulses required for one cycle, G, and B data (n bits) are sequentially shifted in a data pulse period in synchronization with a scan pulse generated by a sustain pulse in order to load the R, G, and B data (n bits) And a second step of decreasing the sustain period by decreasing the time required to sustain the plasma display panel.