KR100403511B1 - PDTV's address driver circuit - Google Patents

Abstract

The present invention converts a composite video signal received from the outside into digital R (Red), G (Green), B (Blue) data to supply to the address electrode lines of the plasma display panel (PDP), respectively. It relates to an address driving circuit.

According to the present invention, an address driver IC outputs R, G, and B data of m bits (where m is a multiple of 3) input through m output terminals arranged in succession. And a data interface unit for supplying the corresponding R, G, and B data to each input terminal of the address driver IC in consideration of the changed input / output relationship of the address driver IC.

When using an address driver IC that has four input terminals and outputs m-bit R, G, and B data input through each input terminal through m output terminals arranged in succession, the output terminal and the address of the data interface unit as shown in the present invention. Since the twist of the data transmission pattern between the input terminals of the driving IC is greatly reduced as compared with the related art, it is possible to easily implement the chip of the data interface unit.

Description

An address driving circuit of a PDP television

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a Plasma Display Panel (PDP) TV, and more particularly, to convert composite video signals received from the outside into digital R (Red), G (Green), and B (Blue) data to address PDPs The present invention relates to an address driving circuit of a PDTV each of which is supplied to a.

In general, PD is coated on a flat panel display panel using a penning mixed gas for discharging, that is, gases based on neon or helium (Ne) or helium (He) gas having a relatively high air pressure (over 100 Torr). The panel which uses the light emission phenomenon obtained by discharging between narrow electrodes.

The penning gas is mainly Ne + Xe, Ne + He + Xe, and the reason for using such a mixed gas is that the discharge start voltage can be lowered when the mixed gas is more than one gas component. The discharge start voltage depends on the type of gas, the fanning gas pressure, and the structure and shape of the panel.

The PD has the following advantages over other display devices.

First of all, the PD is not limited to the number of horizontal and vertical display lines, so that a large size can be manufactured and a multiplexing technique can be used to reduce the number of driving circuits.

The large matrix display panel has a memory function, which is necessary to eliminate high brightness and flicker, while the CRT has a lifespan of 20,000 hours while the PDIP has a lifespan of 50,000 hours.

In addition, PDP is suitable for mass production because there are no easily broken parts other than glass, and because the structure is simple, it is possible to manufacture large panels and have a resolution of 100 Line / inch or more due to strong nonlinearity.

Since the discharging material is a gas, the refractive index value is 1, which means that the light is not extinguished by the internal reflection and the external light is not reflected or scattered by the display material. In addition, unlike other flat panels, PD is sealed with glass at 400 ℃ or higher, which means that PD can operate even under high humidity conditions or the presence of reactive gases. It is only a change.

The PDs are classified into AC PDs and DC PDs according to the type of driving voltage applied to the discharge cells. The AC type PD is driven by a sinusoidal AC voltage or a pulse voltage, while the DC type PD is driven by a DC voltage. In addition, in the AC type PD, the electrode is covered with a dielectric of glass, whereas in the DC type PD, the electrode is exposed as it is and a discharge current flows while the discharge voltage is applied.

1 is a block diagram illustrating a schematic configuration of a general PDTV. The AC type PDPD includes an audio / video unit 110, an analog / digital converter 120, a memory unit 130, and a data interface unit ( 140, upper and lower address driving integrated circuit (150-1, 150-2), scan and sustain driving IC (160), timing controller 170, high voltage driving circuit 180, AC-DC The conversion unit 190 and the three-electrode surface discharge color PD 200.

The audio / video unit 110 receives an NTSC composite video signal through an antenna and separates analog R (Red), G (Green), and B (Blue) signals from horizontal and vertical sync signals (Hsync, Vsync), An APL (Average Picture Level) corresponding to an average value of the luminance signal is obtained and provided to the analog / digital converter 120. Here, the NTSC composite video signal has an interlaced scanning method in which one frame consists of two fields, odd and even, a horizontal sync signal (Hsync) has a frequency of about 15.73KHz, and a vertical sync signal (Vsync) has a frequency of about 60Hz. .

The analog / digital converter 120 receives analog R, G, and B signals from the audio / video unit 110, converts the analog R, G, and B signals into digital data, and outputs the digital data to the memory unit 130.

The memory unit 130 stores digital R, G, and B signals received from the analog / digital converter 120. In general, the image data of one field must be reconstructed into a plurality of subfields for grayscale processing of PDPD, and then rearranged from the most significant bit to the least significant bit, and the image data inputted by interlaced scanning is converted into sequential scanning and displayed. The memory unit 130 is used as an area for storing one frame of image data.

The data interface unit 140 temporarily stores the R, G, and B data received from the memory unit 130 and provides the data in the form of data required by the address driver IC units 150-1 and 150-2. .

The address driver IC unit includes upper and lower address driver IC units 150-1 and 150-2, and the upper address driver IC unit 150-1 is provided with R, G, and B data received from the data interface unit 140. Address pulses are supplied to odd-numbered address electrode lines of the three-electrode surface discharge PD 200 according to " high " and " low " Address pulses are supplied to even-numbered address electrode lines of the 3-electrode surface discharge color PD 200 according to the "high" and "low" of the received R, G, and B data.

An analog / digital converter 120 for converting the NTSC composite image signal received through the antenna into digital R, G, and B data and supplying them to the address electrode lines of the three-electrode surface discharge color PD 200; The memory unit 130, the data interface unit 140, and the upper and lower address driving IC units 150-1 and 150-2 are collectively referred to as an 'address driving circuit'.

The scan and sustain driving IC unit 160 supplies a scan pulse and a sustain pulse to the scan and sustain electrode lines of the three-electrode surface discharge color PD 200.

The timing controller 170 receives the horizontal and vertical synchronization signals Hsync and Vsync output from the audio / video unit 110 to generate a data read clock (data read CLK) to generate the memory unit 130 and the data interface unit. Each of them is supplied to the 140, and various logic control pulses are generated and supplied to the high voltage driving circuit unit 180.

The high voltage driving circuit unit 180 combines the DC voltage supplied from the AC-DC conversion unit 190 according to various logic control pulses output from the timing controller 170 to address, scan, and sustain driving IC unit 150-1. , To generate the high voltage control pulse required by the 150-2, 160 to drive the three-electrode surface discharge color PD200. In addition, the data stream provided from the data interface unit 140 to the address driving IC units 150-1 and 150-2 is also raised to an appropriate voltage level to enable selective writing to the three-electrode surface discharge color PD 200.

The AC-DC converter 190 generates AC voltages (220V AC, 60Hz) as inputs to generate high voltages required to combine the electrode driving pulses and all DC voltages required by each component constituting the system. Supply.

The three-electrode surface discharge color PD 200 has a display dimension of 853 × 3 (R, G, B) × 480.

FIG. 2 is a block diagram illustrating an internal configuration of the memory unit illustrated in FIG. 1, wherein the memory unit 130 includes a data rearranging unit 130-1, an address generator 130-2, and a control clock generator ( 130-3, first and second frame memories 130-4 and 130-5, and a data selector 130-6.

The data rearranging unit 130-1 rearranges the R, G, and B data provided in parallel by the analog / digital converter 120 so that the R, G, and B data are stored in the first or second frame memory 130. -4, 130-5) to be stored for each bit having the same weight and for each of the R, G, and B data.

The address generator 130-2 writes the data in a different order in the first or second frame memories 130-4 and 130-5 to convert the image data input by the interlaced scan method into the progressive scan method and display the same. Provide the address and read address.

More specifically, the address generator 130-2 may store odd-numbered address electrode line data of one horizontal display line among one frame of image data stored in the first or second frame memories 130-4 and 130-5. The read address is provided to repeat the process of reading the even-numbered address electrode line data after being read.

In addition, the address generator 130-2 may store image data corresponding to each subfield in the gray level processing of the 3-electrode surface discharge color PD 200 in the first or second frame memories 130-4 and 130-5. A read address is provided to be read in turn from and supplied to the data interface unit 140.

The control clock generator 130-3 writes / reads addresses necessary for the first and second frame memories 130-4 and 130-5 by inputting the horizontal and vertical synchronization signals Hsync and Vsync and the main clock. A logic control pulse necessary for the clock and the memory unit 130 is generated and supplied.

Each of the first and second frame memories 130-4 and 130-5 has a frame amount of 853 × 3 (R, G, B) × 480 × 8 bits when 2 ⁸ = 256 gray scales are implemented. It can store R, G, and B data (approximately 10 Mbits).

The data selector 130-6 may store a total of 3 bits (R, G) of 16 bits of R, G, and B data among the data stored in the first or second frame memories 130-4 and 130-5 in the read mode. , B) x 16 bits are selected and output to the data interface unit 140 in parallel.

More specifically, in order to arrange the 2559 address electrode lines of the 3-electrode surface discharge color PD 200, R1, G1, B1, R2, G2, B2,... , R853, G853, and B853, the data selector 130-6 includes (R1 to R16, G1 to G16, B1 to B16), (R17 to R32, G17 to G32, and B17 to B32). R, G, and B data are output in 48-bit order.

3 is a memory map structure diagram of a data interface unit that temporarily stores R, G, and B data received from the data generation unit illustrated in FIG. 2, wherein the data interface unit 140 has a matrix structure of 48 (rows) × 54 The (column) memory map stores one horizontal display line, that is, R, G, and B data of 853 x 3 (R, G, B) = 2559 bits. The 48 (row) x 54 (column) memory maps are divided into two for convenience and used as two 24 (row) x 54 (column) memory maps 140-1 and 140-2.

That is, R, G, and B data (R1 to R16, G1 to G16, and B1 to B16) output in parallel by 48 bits from the data selection unit 130-6 of the memory unit 130 shown in FIG. R17 to R32, G17 to G32, B17 to B32)... Are stored as shown in FIG. 3 from the first column to the last column of each of the two 24 (row) x 54 (column) memory maps 140-1 and 140-2.

4 is a diagram illustrating input and output terminals of an address driver IC included in the upper and lower address driver IC units shown in FIG. 1, wherein the address driver IC includes four input terminals a, b, c, and d. And 64 output terminals (a1, b1, c1, d1, a2, ..., a16, b16, c16, d16) and 16 times in parallel by 4 bits through the four input terminals a to d. The R, G, and B data inputted over are arranged in the order of input, and are output in parallel through the 64 output terminals a1 to d16.

That is, 4-bit R, G, and B data input first through the four input terminals a to d of the address driving IC are output through the four output terminals a1 to d1, and finally 4 Bits R, G, and B data are output through four output terminals a16 to d16.

Next, the mutual correspondence state between the output terminal of the data interface unit 140 and the input terminal of each address driving IC will be described.

In order to make it easier to understand the correspondence state between the data interface unit 140 and the input / output terminals of each address driver IC, the following is included in the upper address driver IC unit 150-1 so that The address driving ICs responsible for the 64 address electrode lines R1, B1, G2, ..., R41, B41, G42, and R43 located in front of the odd-numbered address electrode lines will be described as an example.

The 64 address electrode lines R1, B1, G2, ..., R41, B41, G42, and R43 in charge of the address driver IC and the 64 output terminals a1 to d16 of the address driver IC correspond one-to-one, respectively. In this case, the R, G, and B data respectively input to the four input terminals a to d of the address driver IC 16 times are shown in Table 1 below.

One 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 a R1 B3 G6 R9 B11 G14 R17 B19 G22 R25 B27 G30 R33 B35 G38 R41 b B1 G4 R7 B9 G12 R15 B17 G20 R23 B25 G28 R31 B33 G36 R39 B41 c G2 R5 B7 G10 R13 B15 G18 R21 B23 G26 R29 B31 G34 R37 B39 G42 d R3 B5 G8 R11 B13 G16 R19 B21 G24 R27 B29 G32 R35 B37 G40 R43

As can be easily seen from Table 1, each of the input terminals a to d of the address driver IC is mixed with R, G, and B data for 16 times in which 4 bits are input in parallel at one time. When R, G, and B data are mixed and input to the input terminal, the data of the data interface unit 140 fixed as shown in the memory maps 140-1 and 140-2 of the data interface unit 140 shown in FIG. Considering the storage state, the data transmission pattern between the data output terminal of the data interface unit 140 and the input terminals a to d of the address driver IC is very severely twisted.

As described above, the data transmission pattern twisting phenomenon between the output terminal of the data interface unit 140 and the input terminal of the address driver IC may be considered to be very severe in the input terminal of the remaining address driver IC.

As described above, the data transmission pattern between the output terminal of the data interface unit and the input terminal of each address driving IC disposed above and below the PD has been severely twisted, which makes it difficult to implement a chip of the data interface unit.

The present invention has been made to solve the above problems, the address driver IC outputs a plurality of bits of R, G, B data input through one input terminal through the output terminals arranged in succession, the data The interface unit is configured to supply the corresponding R, G, and B data to each input terminal of the address driver IC in consideration of the input / output relationship of the address driver IC so that the data transfer pattern between the output terminal of the data interface unit and the input terminal of the address driver IC can be changed. It is an object of the present invention to provide an address driving circuit of PDTV with reduced twist.

In order to achieve the above object, the PDP TV address driving circuit temporarily stores R, G, and B data separated by bit weights by M bits per column in a 3M (row) x N (column) matrix structure. A PD drive address driving circuit having a data interface unit for storing and rearranging and outputting the data stream in a form of a data stream required by a plurality of address driver ICs. First to fourth input terminals for simultaneously receiving B data one bit at a time and first to fourth m output terminals (where m is a multiple of 3) connected to the address electrode line of the PD1 in a one-to-one correspondence; The m, R, G, and B data, which are inputted m times by 1 bit through the first input terminal, are arranged in a sequence of being received sequentially The first to m th output terminals and the m, R, G and B data, which have been inputted m times by 1 bit through the second input terminal, are arranged in the order of input and are continuously arranged; output through m + 1 to 2m output terminals, and sequentially arrange the m, R, G, and B data received m times one bit at a time through the third input terminal in the order of input; Outputs through 2m + 1 to 3m output terminals, and sequentially arranges the m, R, G, and B data, which are input m times one bit at a time through the fourth input terminal, in the order of input. Output through the 3m + 1 to 4m output terminal.

1 is a block diagram showing a schematic configuration of a typical PDTV,

2 is a block diagram illustrating an internal configuration of a memory unit illustrated in FIG. 1;

3 is a memory map structure diagram of a data interface unit that temporarily stores R, G, and B data received from the data generation unit shown in FIG. 2;

4 is a diagram illustrating input and output terminals of an address driver IC included in the upper and lower address driver IC units shown in FIG. 1;

5 is a diagram illustrating input and output terminals of an address driving IC according to an exemplary embodiment of the present invention.

<Description of Symbols for Main Parts of Drawings>

140: data interface unit 140-1, 140-2: memory map

a, b, c, d: address driver IC input terminal

a1-a18, b1-b18, c1-c18, d1-d18: address driving IC output terminal

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

The PDTV to which the present invention is applied, like the prior art, includes an audio / video unit, an analog / digital converter, a memory unit, a data interface unit, upper and lower address driving IC units, a scan and sustain driving IC unit, a timing control unit, and a high voltage driving unit. It consists of a circuit part, an AC / DC conversion part, and a 3-electrode surface discharge color PD.

In addition, in the following description, components that work the same as the prior art are denoted by the same reference numerals as the prior art.

FIG. 5 is a diagram illustrating an input / output terminal of an address driving IC according to an embodiment of the present invention, wherein the address driving IC is configured to receive R, G, and B data simultaneously from the data interface unit 1 to 1 at the same time. First to 72th output terminals a1, a2, and fourth connected to the fourth input terminals a, b, c, and d and the address electrode line of the 3-electrode surface discharge color PD 200 shown in FIG. 1 in a one-to-one correspondence. ..., a18, b1, b2, ..., b18, c1, c2, ..., c18, d1, d2, ..., d18).

Unlike the prior art, the address driving IC outputs 18 bits of R, G, and B data input through one input terminal through consecutively arranged output terminals. That is, the address driving ICs sequentially arrange the 18-bit R, G, and B data inputted 18 times one bit through the first input terminal a in the order of receiving the first to 18th consecutively arranged. Outputs through the output terminals a1, a2, ..., a18, and arranges 18 bits of R, G, and B data inputted 18 times one bit through the second input terminal b in the order of input. 18-bit R, G output through the 19 th to 36 th output terminals b1, b2,..., B18 arranged in succession, and received 18 times by 1 bit through the third input terminal c. And B data are arranged in the order of input and output through the 37 th to 54 th output terminals (c1, c2,..., C18) continuously arranged, and 18 times per bit through the fourth input terminal d. 55th to 72nd output terminals d1 and d2 arranged consecutively by arranging the 18-bit R, G, and B data inputted in the order received; , ..., d18).

In the data interface unit, like the prior art ²⁸ = the R, G, B data separated by each bit weight to the 256 gray implemented as two 24 (rows) × 54 (columns), the structure shown in Figure 3 the memory map Saving.

However, the data interface unit of the present invention supplies the corresponding R, G, and B data to each of the input terminals a to d of the address driver IC in consideration of the changed input / output relationship of the address driver IC. A data stream supplied to each of the input terminals a to d of the address driving IC shown in FIG. 5 and each of the input terminals a to d of the address driving IC shown in FIG. 4 in the conventional data interface unit 140 is shown. The data arrangement of the data stream supplied to the is different.

72 address electrode lines R1 and B1 included in the upper address driving IC unit 150-1 and positioned in front of the odd-numbered address electrode lines of the 3-electrode surface discharge color PD 200 so that the above description can be easily understood. A description will be given by taking an address driving IC which is in charge of, G2, ..., R47, B47, G48) as an example.

When the 72 address electrode lines R1 to G48 in charge of the address driving IC and the 72 output terminals a1 to d16 of the address driving IC are in one-to-one correspondence, each of the address driving ICs is performed 18 times. R, G, and B data respectively inputted through the four input terminals a to d are shown in Table 2 below.

One 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 a R1 B1 G2 R3 B3 G4 R5 B5 G6 R7 B7 G8 R9 B9 G10 R11 B11 G12 b R13 B13 G14 R15 B15 G16 R17 B17 G18 R19 B19 G20 R21 B21 G22 R23 B23 G24 c R25 B25 G26 R27 B27 G28 R29 B29 G30 R31 B31 G32 R33 B33 G34 R35 B35 G36 d R37 B37 G38 R39 B39 G40 R41 B41 G42 R43 B43 G44 R45 B45 G46 R47 B47 G48

As can be easily seen from Table 2, each of the input terminals a to d of the address driver IC is mixed with R, G, and B data for 18 times of inputting data in parallel 4 bits at a time. Referring to the memory map structure of the data interface unit, the memory map portion corresponding to each of the first to fourth input terminals a to d is much less distributed compared to the prior art for one input terminal. The twist of the data transfer pattern between the negative output terminal and the input terminals a to d of the address driver IC is much less than before.

In addition, it can be estimated that the twist of the data transmission pattern between the output terminal of the data interface unit and the input terminal of the remaining address driving IC is similarly reduced.

As described above, if the twist of the data transmission pattern between the output terminal of the data interface unit and the input terminal of the address driving IC is greatly reduced, the chip implementation of the data interface unit is much easier.

On the other hand, the present invention is not limited to the number of R, G, B data inputs of the address driver IC as described above, but the number corresponding to a multiple of three (three times, six times, nine times, twelve times). ) Are all possible.

As described above, since the twist of the data transmission pattern between the output terminal of the data interface unit and the input terminal of the address driving IC is configured to be greatly reduced as compared with the related art, the chip of the data interface unit can be easily implemented.

Claims (1)

R (Red), G (Green), and B (Blue) data separated by bit weights are temporarily stored in 3M (row) x N (column) matrix structure with M bits per column. In the address drive circuit of a plasma display panel (PDP) TV having a data interface for rearranging and outputting the data stream in the form of a required data stream, The address driving IC may include first to fourth input terminals that simultaneously receive R, G, and B data from the data interface unit one bit at a time, and first to fourth m output terminals connected in a one-to-one correspondence to the address electrode line of the PD. (Where m is a multiple of 3) and arranged sequentially in order that m-bit R, G, and B data received m-by-bit input one time through the first input terminal are arranged in the order of input. The first to m th output terminals and the m, R, G and B data, which have been inputted m times by 1 bit through the second input terminal, are arranged in the order of input and are continuously arranged; output through m + 1 to 2m output terminals, and sequentially arrange the m, R, G, and B data received m times one bit at a time through the third input terminal in the order of input; 2 m + 1 to 3m + 1 to 3m output terminals which are outputted through the 3m output terminal and arranged sequentially in order of receiving the R, G, and B data of m bits inputted m times by 1 bit through the fourth input terminal. The address driving circuit of PDTV, characterized in that output through the 4m output terminal.