KR20000003876A - Interrupt control apparatus - Google Patents

Abstract

PURPOSE: An interrupt control apparatus is provided, which controls an interrupt of an interrupt process system to decrease an unnecessary power waste. CONSTITUTION: An interrupt control apparatus comprises: a plurality of D flip-flop (100_1, 100_2, 100_n) for corresponding to an each interrupt source; an interrupt controller (200) for outputting a signal adaptive to system by an interrupt signal of D flip-flops (100_1, 100_2, 100_n); and a clock providing unit (300) for inputting the interrupt signal provided from the interrupt source and a display signal of the control circuit and for providing a clock signal to the control circuit when at least one signal between the interrupt signal and the display signal is active. Therefore, a waste of an unnecessary power is prevented in the system which a probability of an interrupt occurrence is low.

Description

Interrupt Control Unit (APPARATUS FOR CONTROLLING INTERRUPT)

The present invention relates to an apparatus for receiving interrupt signals from an interrupt source and outputting a control signal for causing the interrupt processing system to perform an interrupt, and more particularly, to an interrupt control apparatus capable of reducing unnecessary power consumption.

In general, interrupt events occur very rarely compared to the execution of instructions by a microprocessor. However, conventionally, a state machine configured in an interrupt controller is designed to always operate. Even if the state machine stays in the same state because no external interrupt has occurred, the interrupt controller continues to consume power. In systems with low interrupt probability, the average power consumption of the interrupt controller amounts to 30% of the maximum power consumption.

1 is a block diagram illustrating a circuit configuration of a conventional interrupt controller.

Referring to FIG. 1, the interrupt controller includes a plurality of D flip-flops 10_1, 10_2, and 10_N and an interrupt control circuit 20. Control signals are input to the D flip-flops 10_1, 10_2, and 10_N from corresponding interrupt sources INT 0, INT 1, and INT n, respectively. The D flip-flops 10_1, 10_2, and 10_n output an interrupt signal input in synchronization with the clock signal MCLK to the control circuit.

In the conventional interrupt controller, the clock signal MCLK is continuously input to the D flip-flops 10_1, 10_2, 10_N and the interrupt control circuit 20 to wait for the input of the interrupt regardless of the operation state of the interrupt controller. Power is consumed because the D flip-flops 10_1, 10_2, 10_N and the interrupt control circuit 20 are in an operating state according to the input of the clock signal.

Operation of the interrupt controller by the input of the clock signal in the system having a low probability of interruption causes unnecessary power consumption.

Accordingly, an object of the present invention is to solve the above-mentioned problems, and to provide an interrupt controller having a circuit capable of preventing unnecessary power consumption from being interrupted in an interrupt controller of a system having a low interrupt probability.

1 is a block diagram showing a circuit configuration of a conventional interrupt controller in a block; And

2 is a circuit diagram illustrating a circuit configuration of an interrupt controller according to a preferred embodiment of the present invention.

* Description of the symbols for the main parts of the drawings *

10_1, 10_2, 10_n, 100_1, 100_2, 100_n, 320: D flip-flop

20, 200: interrupt control circuit 300: clock supply unit

310: noah gate 330: oa gate

According to a feature of the present invention for achieving the object of the present invention as described above, an apparatus for receiving interrupt signals from at least one interrupt source and outputting a control signal for causing the interrupt processing system to perform an interrupt: Control means for receiving the interrupt signal in synchronization with a clock signal and outputting the control signal; A clock supply for supplying the clock signal to the control means when the interrupt signal provided from the interrupt source and a signal indicating whether the control circuit is in operation are input, and the at least one of the signals is activated Means;

In a preferred embodiment, the clock supply means inputs an interrupt signal provided from the interrupt source and a signal indicating whether the control circuit is in operation to determine whether at least one of the signals is active. Means for detecting whether; And switching means for supplying the clock signal to the control means depending on whether the detection means is detected.

(Example)

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

The present invention relates to an apparatus for receiving interrupt signals from at least one interrupt source and outputting a control signal for causing the interrupt processing system to perform an interrupt. It has a configuration that can be prevented. The interrupt control apparatus inputs a control means for receiving the interrupt signal and outputting the control signal in synchronization with a predetermined clock signal, and inputting an interrupt signal provided from the interrupt source and a signal indicating whether the control circuit operates. Clock supply means for supplying the clock signal to the control means when at least one of the signals is active.

2 is a circuit diagram illustrating a circuit configuration of an interrupt controller according to a preferred embodiment of the present invention.

Referring to FIG. 2, the interrupt controller receives an interrupt signal from the plurality of D flip-flops 100_1, 100_2 and 100_n and the D flip-flops 100_1, 100_2 and 100_n respectively corresponding to an interrupt source. An interrupt control circuit 200 for outputting suitable signals and an interrupt signal provided from the interrupt sources and a signal indicating whether the control circuit is in operation are input so that at least one of the signals is active. And a clock supply unit 300 for supplying the clock signal to the control means.

The interrupt signals INT 0, INT 1, INT n provided from the interrupt sources are asynchronous signals. These asynchronous signals are input to the D flip-flops 100_1, 100_2, 100_n and synchronized.

The interrupt control circuit 200 gives priority to each interrupt when several interrupt signals are input from the D flip-flops at the same time, or outputs a control signal so that the microprocessor performs an operation corresponding to the request of the interrupt source. . The D flip-flops 100_1, 100_2, 100_n and the interrupt control circuit 200 operate in synchronization with the clock signal MCLK.

The interrupt sources and the interrupt control circuit 200 are high active outputting a high level signal when making an interrupt request and performing interrupt processing, respectively.

The clock supply unit 300 includes a NOR gate 110, a D flip-flop 320, and an ora gate 330. The NOR gate 310 performs a NOR operation on the interrupt signals INT 0, INT 1, INT n provided from the respective interrupt sources and the enable signal Enabled from the interrupt control circuit 200. Detects whether at least one of the signals is active. The NOR gate 310 outputs a low level signal when at least one of the signals input from the interrupt sources and the interrupt control circuit 200 is activated to a high level.

The D flip-flop 320 outputs the signal input from the NOR gate 310 to the output terminal Q in synchronization with the clock signal MCLK. The OR gate 330 inputs the output signal of the D flip-flop 320 and the clock signal MCLK to perform an OR operation. The OR gate 330 provides a clock signal MCLK to the D flip-flops 100_0, 100_1, and 100_n and the interrupt control circuit 200 when a low level signal is input from the D flip-flop. If the D flip-flop 320 outputs a high level signal, the output of the OR gate 330 becomes high and cannot provide the clock signal MCLK to the D flip-flop and interrupt control circuit 200. Therefore, the D flip-flops 100_0, 100_1, and 100_n and the interrupt control circuit 200 do not operate.

As described above, the interrupt controller of the present invention receives the clock signal only when the interrupt signal is input from the interrupt sources or when the interrupt control circuit 200 performs the interrupt process. Therefore, when the interrupt is not generated and the interrupt controller is not performing the interrupt processing, the circuits constituting the interrupt controller do not operate, thereby preventing unnecessary power consumption. The power consumed by these interrupt controllers is 10% of the maximum power consumption.

In the above, the configuration and operation of the circuit according to the present invention are shown in accordance with the above description and drawings, but this is merely described, for example, and various changes and modifications are possible without departing from the spirit of the present invention. .

According to the present invention as described above, unnecessary power is prevented from being consumed in an interrupt controller of a system having a low probability of interrupt occurrence.

Claims (2)

An apparatus for receiving interrupt signals from at least one interrupt source and outputting a control signal for causing the interrupt processing system to perform an interrupt: Control means for receiving the interrupt signal in synchronization with a predetermined clock signal and outputting the control signal; A clock supply for supplying the clock signal to the control means when the interrupt signal provided from the interrupt source and a signal indicating whether the control circuit is in operation are input, and the at least one of the signals is activated Means for including an interrupt controller. The method of claim 1, The clock supply means, Means for inputting an interrupt signal provided from the interrupt source and a signal indicating whether the control circuit is in operation to detect whether at least one of the signals is active; And switching means for supplying the clock signal to the control means in accordance with the detection of the detection means.