JP2007102643A - Key scanning circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a key scanning circuit, capable of reducing the software processing load of a CPU while ensuring the freedom of design, and also shortening the processing time, from the viewpoint of various problems of a conventional key scanning circuit, and further a key scanning circuit capable of performing rapid processing even if the CPU is in a sleep state. <P>SOLUTION: The key scanning circuit including the CPU, a memory device, an input/output port, and an interruption controller comprises a chattering removal circuit and a bypass circuit of the chattering removal circuit, so that a key input signal is switched either to the chattering removal circuit or to the bypass route by software control. A one-chip microcomputer is used for the CPU or the like, and key scanning function is constituted using each input/output port of GPIO (general purpose input output port). <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a key scan circuit, and more particularly to a key scan circuit suitable for a configuration using a one-chip microcomputer.

Various computers are often equipped with various input means, including numeric keys, but it is possible to detect which key has been operated in order to efficiently transmit key operation signals to the computer with fewer signal lines. Perform key scan processing. Further, when a mechanical switch is operated and turned on / off, the signal rises or falls momentarily, but in reality, the potential fluctuates in the order of ms. This is called chattering, and if this fluttering is counted in a counting circuit or the like, it causes a malfunction, so a chattering removal circuit is added. Conventionally, the basic function of the chattering removal circuit is that after detecting that a key switch is operated, the key signal detection for which a chattering occurs is masked for a certain period of time, and then a central processing unit (hereinafter referred to as “CPU”). An interrupt request was generated. However, with the method of masking the entire key signal detection every time any key is operated, it becomes impossible to detect other keys operated during masking. Therefore, for example, Japanese Patent Laid-Open No. 2-170615 “chattering prevention device” proposes a method in which masking means is individually provided for each input key group signal.
On the other hand, as a method for realizing a key scan circuit, a microcomputer (custom LSI) dedicated to key scan has been conventionally used, but in recent years, a one-chip microcomputer has become mainstream. A one-chip microcomputer (hereinafter referred to as “one-chip microcomputer”) includes a memory, an input / output interface circuit (I / O), a CPU, and the like in one integrated circuit (Large Scale Integrated Circuit: LSI) chip. It has a function as a microcomputer by itself. These one-chip microcomputers are mounted on computer peripheral devices such as a keyboard and share the control of each peripheral device instead of the main CPU, thereby reducing the burden on the main CPU, as well as home appliances, automobiles, It is also used to control devices in various fields such as industrial equipment and game machines.

  FIG. 8 is a block diagram showing an example of a one-chip microcomputer. A one-chip microcomputer 100 shown in this example includes a CPU 101 that performs overall control, an external parallel controller (EXT MEMORY INTERFACE) 102 connected to an external memory, and the like, and transfers data without being controlled by the CPU 101. DMA (Direct Memory Controller) 103, internal RAM (INTERNAL RAM) 104, internal ROM (INTERNAL ROM) 105, interrupt controller (ICTL) 106, analog / digital conversion circuit (ADC) 107, digital An analog conversion circuit (DAC) 108, a synchronous serial interface (SPI) 109, and an asynchronous serial interface that converts a parallel signal into a serial signal, or conversely converts a serial signal sent from a serial device into a parallel signal. (Universa l Asynchronous Receiver Transmitter (UART) 110, parallel interface (General Purpose Input Output Port: GPIO) 111, which functions as a general-purpose input / output port, and key scan that connects a key matrix such as an external keyboard to be scanned A circuit 112, a timer (TIMER) 113 that is equipped with a counter and counts time, a power management unit (POWER MANAGEMENT) 114 that performs control to shift to a low power consumption mode, and generates each clock signal to each functional block circuit A clock circuit (CLKGEN) 115 for controlling supply / stop of the clock signal is provided, and each is connected by an internal bus line 116.

FIG. 9 shows a conventional key scan circuit using a key scan circuit 112 of a one-chip microcomputer. The key scan circuit 112 has a dedicated hardware configuration that matches the key matrix 117 of the target keyboard. Yes. FIG. 10 is a schematic configuration diagram showing an example of a key scan circuit using the GPIO 111 normally mounted on a one-chip personal computer. In any circuit, the input / output terminals of the key matrix 117 are connected to the input / output ports of the key scan circuit 112 and the GPIO 111, and necessary signals are sequentially supplied from the respective output ports. When one of the keys in the key matrix 117 is operated by sensing, the CPU 101 is interrupted via the interrupt controller (ICTL) 106, and the key operated by the control of the CPU 101 is detected and illustrated. Is transmitted to the main CPU in which is omitted.
Japanese Patent Laid-Open No. 2-170615

However, according to the above-described prior art, there are the following problems. First, if all the controls are realized by software as disclosed in Patent Document 1, the load on the CPU increases and the processing is slowed down. In the case of a keyboard that is used for simple setting of a home electronic device such as the PCM recorder exemplified in the publication, the processing load is small, but in the case where many key operations are performed in a short time like a keyboard of a personal computer or the like. However, there is a drawback that a high processing speed is required for the CPU.
If a one-chip microcomputer is used, the burden on the main CPU can be reduced. However, as shown in FIG. In addition to the fixed number of ports, the chattering removal period (temporal timing) is fixed to some extent, so if the number of keys is different or different types of keyboards, the hardware is configured accordingly. Therefore, the degree of freedom of design is greatly impaired.
On the other hand, as shown in FIG. 10, in the case of using the one-chip microcomputer GPIO, the degree of freedom of design is improved, but the GPIO is basically a control function of the input / output port. There is a problem that it is necessary to control all of the chattering removal function, and the processing amount of software related to the key scan control is greatly increased.
In general, if the computer does not perform a new operation for a certain period of time, the CPU is put into the sleep state from the viewpoint of power saving, etc., but it takes a little time to start from the sleep state to the normal startup state. It becomes. In the key scan operation, if the related CPU is in the sleep state, when a key operation occurs, it takes time to first bring up the CPU from the sleep state, and then a chattering removal period is required. The time was added in time series, which hindered rapid processing.
The present invention has been made in view of such problems of the conventional key scan circuit, and is capable of reducing the software processing burden while ensuring the degree of freedom of design, and further, An object of the present invention is to provide a key scan circuit that enables quick processing even when the CPU is in a sleep state.

In order to achieve the above object, in the key scan circuit according to claim 1 of the present invention, a central processing unit (CPU) that performs control such as key scan, a memory device that stores programs and various data, and a plurality of input devices. In a key scan circuit comprising an input / output port having an output means and an interrupt controller for executing interrupt processing for the CPU, a chattering removal circuit, a chattering removal circuit bypass circuit, and an input terminal of the input / output port And a switching circuit for switching the key switch input signal to the chattering elimination circuit or the bypass circuit, and the switching circuit is controlled by software.
According to a second aspect of the present invention, there is provided the key scan circuit according to the first aspect, wherein the chattering removal circuit includes a plurality of cascade-connected flip-flop circuits (FF circuits), means for supplying a clock signal to the flip-flop circuits, An OR circuit using the Q output signal of the flip-flop circuit as an input signal, and supplying the key switch signal to the D input terminal of the flip-flop circuit in the foremost stage, and at the D input terminal of the other flip-flop circuit The Q terminal output of the preceding flip-flop circuit is supplied.
3. The key scan circuit according to claim 1, wherein the chattering removal circuit has a variable frequency dividing function for dividing a clock signal, and the chattering removal is performed by controlling the frequency division ratio by software. The feature is that the period can be controlled.
The key scan circuit according to claim 4, wherein when the central processing unit (CPU) is in a sleep state and a key switch signal is input, the chattering removal circuit is bypassed. It is characterized in that it comprises means for supplying a key switch signal to the input port and controlling the switching circuit so as to switch to the chattering removal circuit side after a lapse of a required time.

In the key scan circuit according to the first aspect of the present invention, a central processing unit (CPU) for performing control such as key scan, a memory device for storing programs and various data, and an input / output port having a plurality of input / output means A key scan circuit using, for example, a one-chip microcomputer, and a chattering removal circuit and a chattering removal circuit bypass circuit at the input end of the input / output port. And a switching circuit for switching the key switch input signal to either the chattering removal circuit or the bypass circuit, and the switching circuit is configured to be controlled by software. Bypass the direct key switch signal through the interrupt controller with the CP It can be supplied to the. In addition, if a general-purpose input / output port (GPIO) mounted on a one-chip microcomputer is used as the input / output port, it is possible to change the number of input or output ports according to the type of the target keyboard or the like. This is made possible by wear control, which greatly improves the degree of freedom in design.
According to a second aspect of the present invention, there is provided the key scan circuit according to the first aspect, wherein the chattering removal circuit includes a plurality of cascade-connected flip-flop circuits (FF circuits), means for supplying a clock signal to the flip-flop circuits, A logical sum circuit that uses the Q output signal of the flip-flop circuit as an input signal, and supplies the key switch signal to the D input terminal of the flip-flop circuit in the forefront stage. Since the chattering removal circuit is configured by hardware so as to supply the Q terminal output of the circuit, the load on the CPU is reduced and the processing speed can be increased.

4. The key scan circuit according to claim 3, wherein the chattering removal circuit has a variable frequency dividing function for dividing a clock signal, and the chattering removal period is controlled by software by controlling the frequency division ratio. Therefore, the chattering removal timing time can be changed in accordance with the chattering occurrence time of the target key input device.
A key scan circuit according to a fourth aspect of the present invention is the key scan circuit according to the first to third aspects, wherein when the central processing unit (CPU) is in a sleep state and a key switch signal is input, the chattering removal circuit is bypassed and the key switch signal is transmitted. Since it is provided with means for controlling the switching circuit to switch to the chattering removal circuit side after the required time has elapsed, when the CPU is in a sleep state, the CPU is immediately activated upon occurrence of a key switch, Thereafter, the chattering removal circuit can be controlled to function, and the time required for each can be partially parallelized, so that the processing can be speeded up.

Hereinafter, the present invention will be described in detail with reference to embodiments shown in the drawings. However, the components, types, combinations, shapes, relative arrangements, and the like described in this embodiment are merely illustrative examples and not intended to limit the scope of the present invention only unless otherwise specified. .
FIG. 1 is a block diagram showing an embodiment of a key scan circuit according to the present invention. The key scan circuit 1 shown in this example includes a central processing unit (CPU) 2 that controls the key scan circuit 1, an interrupt controller (ICTL) 3 that executes an interrupt to the CPU when a key switch is operated, and a key A scan unit 4 is included, and these are connected by an internal bus line 5. Further, the key scanning unit 4 includes a general-purpose input / output port GPIO6. Among the input ports, a first input port IN1 and a second input port to which a key switch signal is supplied from a key matrix 7 such as an external keyboard. Chattering removal circuits ch1, ch2, and ch3 and bypass routes BP1, BP2, and BP3 that bypass the chattering removal circuits ch1, SW2, and SW3 are added to the input port IN2 and the third input port IN3, respectively. The Y-axis signal lines (horizontal lines) Y1, Y2, and Y3 of the key matrix 7 (3 × 3 matrix in this example) such as an external keyboard that is the control target are respectively connected to the output terminals OUT1, OUT2, and OUT3. Are connected directly to the three output ports OP1, OP2, and OP3 of the GPIO 6. The X-axis signal lines (vertical lines) X1, X2, and X3 are connected to terminals I1, I2, and I3, and the changeover switch SW1, It is configured to be connected to the input ports IN1, IN2, and IN3 of the GPIO 6 through the common terminals of SW2 and SW3. The resistor R inserted between each of the input terminals I1, I2, and I3 and the power supply line VCC is a pull-up resistor for applying a voltage to each.

The key scan circuit shown in FIG. 2 has the same configuration as that shown in FIG. 1, but the change-over switches SW1, SW2, and SW3 are set to bypass the chattering removal circuits ch1, ch2, and ch3. The parts are different, and the description thereof will be described later.
In this configuration, first, the basic operation of the key scan circuit will be described. When power is turned on in this circuit, there are various control methods. For example, the Y-axis signal lines Y1, Y2, and Y3 of the key matrix 7 are set at regular intervals via the output ports OP1, OP2, and OP3 of the GPIO 6. Scan control for switching to a low potential is performed (specifically, grounding is sequentially performed). In this case, the input ports IN1, IN2, and IN3 of the GPIO 6 are sequentially scanned while a low potential is applied to one Y-axis signal line. Thus, the potentials of the input terminals I1, I2, and I3, that is, the potentials of the X-axis signal lines X1, X2, and X3 of the key matrix 7 are monitored. At this time, since a high potential is applied to each of the input terminals I1, I2, and I3 through the pull-up resistor R, the high potential is held when the key is not pressed, but the key is operated. Those that are pressed (pressed) are connected to the Y-axis line, and therefore have a low potential. Therefore, the CPU 2 determines which key is pressed from the scan information of the Y-axis signal line on the output port side, the scan information of the X-axis signal line of the input port, and the potential information of each port. Can do.
Note that the potential relationship need not be limited to this example, and conversely, a high potential may be supplied from the output port, and a high potential may be detected by a scanning operation at the input port.

  FIG. 3 is a block diagram showing an example of chattering removal circuits ch1, ch2, and ch3 used in the present invention. In this example, four delay flip-flop circuits (Delay flip-flops: D-FF) 8 to 11 connected in cascade, and a frequency divider (DIVIDER) 12 that divides a clock signal supplied to each flip-flop circuit, A logical sum circuit 13 having the Q output signal of each flip-flop circuit as an input signal, and supplying an external key switch signal to the D input terminal of the flip-flop circuit 8 at the front stage, The D input terminal of the circuit is configured to supply the Q terminal output of the preceding flip-flop circuit. The delay type flip-flop circuit (D-FF circuit), as is well known, transmits the state input to the D terminal to the Q terminal in response to the supply of the clock signal. Will be delayed. In this example, since four stages are connected in cascade, the high / low potential of the D input terminal of the flip-flop circuit 8 at the front stage is sequentially transmitted, and as a result, the fourth flip-flop 11 is delayed by four clocks. Leads to Q terminal. Further, since the output of the OR circuit 13 becomes a low potential only when all of the input signals are at a low potential, the output becomes a high potential when any one of the inputs is at a high potential. That is, if even one of the inputs of the OR circuit 13 is at a high potential, the output becomes a high potential.

4 and 5 are diagrams for explaining the operation of the chattering removal circuit shown in FIG. 3. FIG. 4 is a signal waveform diagram when chattering does not occur, and FIG. 5 is a signal waveform diagram when chattering occurs. is there. Hereinafter, an operation example of the scan circuit of the present invention will be described with reference to this signal waveform diagram.
FIG. 5A shows a clock signal waveform supplied to the flip-flop circuit. When a key belonging to the chattering removal circuit shown in this figure is pressed, the input terminals belonging to the system among the input terminals IN1, IN2, and IN3 of the GPIO 6 are low potentials as shown in FIG. It becomes. When this signal is input to the D terminal of the first-stage flip-flop circuit 8, the signal is transferred to the Q output terminal of the flip-flop circuit 8 in response to the next clock signal input, as shown in FIG. Thus, a low potential is transmitted as the output A. Similarly, this signal is sequentially transmitted to the subsequent flip-flop circuits 9, 10, and 11, and output B shown in FIG. 4D, output C shown in FIG. 4E, and output D shown in FIG. It becomes. Assuming that chattering does not occur at this time, the pressed key maintains the same state at least during the chattering removal period. Therefore, the signals A, B, C, and D at the Q output terminals of the flip-flop circuits 8 to 11 are all A low potential is input to the logic circuit 13. As a result, the output of the OR circuit 13 becomes a low potential and is supplied to the corresponding input port (IN) of the GPIO 6 in FIG.

FIG. 4 is a signal waveform diagram when chattering occurs. As shown in FIG. 4B, after the pressed key signal input once becomes low potential, it becomes high potential again after, for example, three clocks. In this case, when the low potential input to the D terminal of the flip-flop circuit 8 is transmitted to the Q output of the last flip-flop circuit 11, the potential of the Q output signal (output A) of the first-stage flip-flop circuit 8 is high. As a result, the output of the logic circuit 13 does not become a low potential, and a high potential is transmitted to the CPU 2 after all.
If it can be determined that chattering has occurred in this way, the subsequent processing can be handled by various methods. For example, if chattering is not detected, processing can be started as soon as the detected key signal is true, or if chattering is detected, it is assumed that the key operation has been performed only once. It is possible to take measures such as processing or processing only the input detection signal after the chattering removal period has passed as a true key signal input. As described above, when it is confirmed that chattering does not occur, the method of processing as a true key input immediately can perform a quick and efficient process when using a keyboard with a low degree of chattering. there is a possibility.

  FIG. 6 is a flowchart for explaining another embodiment of the present invention, and the processing procedure shown in this example relates to processing when the CPU 2 is in a sleep state. That is, when the process is started, first, the operation of the key switch is waited (S1). When the key operation is detected (S1 Yes), it is determined whether or not the CPU 2 is in the sleep state, and the CPU 2 is in the sleep state. If it is in the state (S2 Yes), the switch SW is switched to the bypass route BP of the chattering removal circuit ch shown in FIGS. 1 and 2 (S3). After that, it is determined whether or not a predetermined time (chattering removal period) has elapsed, and after waiting for the passage (S4 Yes), the switch SW is switched to the chattering removal circuit ch side (S5). The signal processing is transmitted to the CPU 2 (S6). When it is determined in S2 that the CPU 2 is not in the sleep state (No in S2), the process proceeds to S5, the switch SW is switched to the chattering removal circuit side (S5), and the chattering function is operated to activate the key switch signal. Is transmitted to the CPU 2. According to this example, there is an effect of speeding up the process as compared with the case where the CPU 2 in the sleep state directly performs the key scan process. That is, when the CPU 2 is in the sleep state, the key switch signal is sent to the input port of the GPIO 6 via any of the bypass routes BP1 to BP3 that bypass the chattering section removal circuit of the key scan section 4 as shown in FIG. Since the signal is transmitted to any one of IN1 to IN3, this signal is immediately supplied to the CPU 2 or transmitted to a circuit for controlling the CPU 2 to cancel the sleep. It is clear that the rise of the CPU 2 is quicker than canceling. When the chattering section removing circuit ch is bypassed and the sleep state release trigger is supplied to the CPU 2, the switch SW is immediately switched to the chattering removing circuit side without waiting for the CPU 2 to rise. According to this process, the CPU 2 rises during the chattering removal time, and the key scan process can be started immediately after the chattering removal period, so that a quick process is possible.

FIG. 7 is a block diagram showing still another modified embodiment of the present invention, and controls the surplus ports of the GPIO 6 corresponding to the keyboard to be controlled by other function control using the degree of freedom of the design of the GPIO 6. The case of using is shown. That is, in this example, the number of key matrixes 7 of the keyboard to be controlled is 2 × 3, which is smaller than that shown in FIG. Therefore, this port is controlled as the fourth output port OP4, and the lighting of the light emitting diode (LED) 15 is controlled via the inverter circuit 14 with the output. In this way, GPIO allows each port to function as an input or an output by software, so if a key scan circuit is configured by GPIO instead of a dedicated key scan circuit as in the prior art, each device In addition, it is possible to make full use of a flexible usage method utilizing the characteristics of the original GPIO.
Although not shown, the frequency dividing circuit shown in FIG. 3 can divide the frequency of the supplied clock signal in various ways. Therefore, the chattering removal period can be freely changed by configuring the frequency division ratio so as to be set by software and changing the clock frequency supplied to the flip-flop circuit D-FF. Therefore, it is possible to change to an optimum value according to the characteristics of the target keyboard. For example, when the supplied clock frequency is 32.768 kHz and the division ratio of the divider circuit (DIVIDER) is 1/16, 1/32, 1/64, 1/128, 1/256, respectively. Since the frequency after frequency division is 2.048 kHz, 1.02 kHz, 512 Hz, 256 Hz, and 128 Hz, the chattering removal period can be adjusted in the range of 1.46 msec to 23.44 msec by adjusting this to time. become. The chattering portion removal period can be adjusted in fine steps by increasing the number of flip-flop stages in the circuit shown in FIG.

Although several embodiments have been described above, the present invention is not necessarily limited to these examples, and various modifications are possible. For example, switching of the chattering removal circuit and its bypass can be applied not only in the sleep state of the CPU but also in normal key operations, and processing for absorbing the time required for interrupt processing in the chattering removal period is also possible. That is, in order to perform CPU interrupt control early, the chattering elimination circuit is usually switched to the chattering elimination circuit bypass route, and when a key operation is detected, a signal is input for interrupt processing to the CPU, and then the chattering elimination circuit side immediately If the control is performed so that the chattering removal time partly passes in parallel during the time required for interrupting the CPU, it is effective in speeding up the processing.
In the configuration example of the one-chip microcomputer shown in FIG. 8, the case where both the key scan and the GPIO are provided is illustrated. However, in the present invention, the GPIO functions as the key scan. It can be deleted unless a dedicated key scan is required. Further, the chattering elimination circuit used in the present invention is not limited to the one shown in FIG. 3, and it is needless to say that various well-known ones can be applied. The OR circuit OR in the block configuration diagram shown is not limited to this, and any circuit may be used as long as it functions similarly.

1 is a schematic block diagram of a key scan circuit according to an embodiment of the present invention. It is a general | schematic block diagram explaining operation | movement of the key scan circuit which concerns on one Embodiment of this invention. It is a block diagram which shows an example of the chattering removal circuit used for one Embodiment of this invention. It is a signal waveform diagram explaining operation | movement of the chattering removal circuit used for one Embodiment of this invention. It is a signal waveform diagram explaining operation | movement of the chattering removal circuit used for one Embodiment of this invention. It is a flowchart which shows the example of control of the key scan circuit which concerns on one Embodiment of this invention. FIG. 6 is a schematic block diagram of a key scan circuit according to a modified embodiment of the present invention. It is a block block diagram which shows an example of a one-chip microcomputer. It is a general | schematic block diagram which shows an example of the conventional key scan circuit. It is a general | schematic block diagram which shows an example of the conventional key scan circuit.

Explanation of symbols

  1 key scan circuit, 2, 101 central processing unit (CPU), 3, 106 interrupt controller, 4 key scan unit, 5, 116 bus line, 6, 111 general-purpose input / output port (GPIO), 7, 117 key matrix, 8 -11 Flip-flop circuit, 12 divider circuit, 13 OR circuit, 14 inverter circuit, 15 light emitting diode (LED), 100 one-chip microcomputer, 102 parallel controller, 103 DMA, 104 internal RAM, 105 internal ROM, 107 analog -Digital conversion circuit (ADC), 108 Digital-analog conversion circuit (DAC), 109 Synchronous serial interface (SPI), 110 Asynchronous serial interface (UART), 111 General-purpose input / output port (GPI) ), 112 key scan circuit, 113 a timer (TIMER), 114 power management unit, 115 a clock circuit (CLKGEN), SW1, SW2, SW3 bypass-switching switch.

Claims (4)

  A central processing unit that performs control such as key scanning, a memory device that stores programs and various data, an input / output port having a plurality of input / output means, and an interrupt controller that executes interrupt processing for the central processing unit A chattering removal circuit at the input terminal of the input / output port, a chattering removal circuit bypass circuit, and a switching circuit for switching a key switch input signal to the chattering removal circuit or the bypass circuit. And a key scan circuit, wherein the switching circuit is controlled by software.   The chattering removal circuit includes a plurality of cascaded flip-flop circuits, means for supplying a clock signal to the flip-flop circuits, and an OR circuit using the Q output signal of each flip-flop circuit as an input signal, The key switch signal is supplied to the D input terminal of the first flip-flop circuit, and the Q terminal output of the preceding flip-flop circuit is supplied to the D input terminal of the other flip-flop circuit. The key scan circuit according to claim 1.   The chattering removal circuit includes a variable frequency dividing function for dividing a clock signal, and is configured to control a chattering removal period by controlling the frequency division ratio by software. 2. The key scan circuit according to 2.   When the central processing unit is in a sleep state and a key switch signal is input, the chattering removal circuit is bypassed and the key switch signal is supplied to the input port and switched to the chattering removal circuit side after a lapse of a required time. 4. The key scan circuit according to claim 1, further comprising means for controlling the switching circuit.

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