JP2013008133A - Clock control circuit for microcomputer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the clock control circuit of a microcomputer for normally continuing an operation under execution by preventing any failure from being generated by the switching of a processor clock.SOLUTION: A clock control circuit 110 of a microcomputer for changing a processor clock 132 of a processor 102 includes: a frequency divider 114 for generating a processor clock 132 by frequency-dividing an input clock (PLL clock 130); and a change enable circuit 122 for detecting the synchronizing timing of the processor clock 132 and the clock (peripheral clock 134, communication clock 136) of another circuit, and for outputting a change enable signal 140 for instructing the change of a frequency-division ratio to the frequency-divider 114.

Description

  The present invention relates to a clock control circuit for a microcomputer capable of switching a processor clock.

  Field devices that detect flow rate, temperature, pressure, and the like differ in accuracy required depending on the site and situation, and various products are produced. Since it is costly to carry out a unique design in each of various products, commonality among products is currently being promoted. For example, a microcomputer is commonly used among products.

  Field equipment is instrumentation equipment for monitoring a plant, and power consumption is extremely reduced in order to reduce running costs. Specifically, the internal power line and the signal line are in the same state, and the supply power is limited. Therefore, the mounted microcomputer or the like needs to operate with less power.

  However, with the recent technological development, field devices are also required to have various functions and gradually become more sophisticated. Along with this higher functionality, a configuration for switching the system clock of a microcomputer has been proposed. In such a configuration, power is stored in advance in an external circuit of the microcomputer, and when the processor is overloaded, this stored power is used to raise the system clock and operate at high speed (hereinafter referred to as “turbo operation”). When the power stored in the external circuit decreases or the processor load is reduced, the system clock is lowered to operate at low speed. Thereby, it can operate | move using little electric power effectively.

  Patent Document 1 discloses a technique for restricting switching of a system clock because a control cycle and timing of control software that operates based on a timer for time synchronization synchronized with the system clock of the microcomputer is shifted by switching the system clock of the microcomputer. Is described. Specifically, in Patent Document 1, switching from low-speed operation to high-speed operation is not limited because it usually does not interfere with control, and switching from high-speed operation to low-speed operation is a sleep that stops the system clock. It is said that it is restricted only at the time of transition to the state.

JP 2002-49610 A

  The technique of Patent Document 1 is a technique for preventing a shift in control cycle and timing of control software that operates based on a timer for timekeeping. Therefore, no mention is made of any problems that occur in the hardware mounted on the microcomputer as the system clock is switched. In the technique of Patent Document 1, the switching from the high speed operation to the low speed operation is performed only at the time of transition to the sleep state in which the system clock is stopped. Under other circumstances, the frequency of the system clock is not decreased. Such control in a field device with limited power supply causes a power shortage.

  When the frequency of the processor clock, peripheral clock, communication clock, etc. is increased by switching the system clock, the operating frequency of the peripheral circuit falls outside the allowable range, or the communication I / O whose communication speed with the outside is specified by the interface There is a possibility that the communication operation of the F circuit may be disconnected, and the operation being executed cannot be continued normally. In such a case, even during switching from the low speed operation to the high speed operation (by increasing the frequency), there is a possibility that the operation being executed cannot be continued normally.

  The present invention has been made in view of such a problem, and provides a clock control circuit for a microcomputer that can prevent a problem from being caused by switching of a processor clock and can continue an operation being executed normally. The purpose is to do.

  In order to solve the above-described problem, a typical configuration of the present invention includes a frequency divider that generates a processor clock by dividing or multiplying an input clock in a clock control circuit of a microcomputer that can change a processor clock of a processor. A change enable circuit that detects a synchronization timing of the multiplier and a clock of another circuit and outputs a change enable signal that instructs the divider or the multiplier to change the division ratio or the multiplication ratio; It is characterized by providing.

  According to the above configuration, the switching of the frequency of the processor clock is performed by changing the division ratio of the frequency divider that generates the processor clock (or the multiplication ratio of the multiplier). This change is performed between the processor clock and other circuits. This is implemented by detecting the synchronization timing with the clock and outputting the change enable signal. Therefore, it is possible to increase or decrease the frequency of the processor clock while maintaining the synchronous relationship between the processor clock and the clocks of other circuits. Therefore, it is possible to prevent a problem from occurring due to switching of the frequency of the processor clock and to continue the operation being executed normally.

  In order to solve the above problems, another typical configuration of the present invention is to generate a processor clock by dividing or multiplying an input clock in a microcomputer clock control circuit capable of changing a processor clock of a processor, and A divider that outputs a clock warning signal before the processor clock, a clock that generates a clock for another circuit by dividing or multiplying the input clock, and a clock warning signal that is output before the clock for the other circuit The synchronization timing of the processor clock and the clocks of other circuits is detected based on the clock notice signal of the frequency divider or multiplier, and the division ratio or multiplication ratio is changed for each frequency divider or multiplier. A change enable circuit for outputting a change enable signal to be instructed.

  According to the above configuration, the change enable circuit detects in advance the synchronization timing immediately after the processor clock and the clock of another circuit based on the clock notice signal, and the change enable signal is output. As a result, it is possible to cope with the case where the frequency of the processor clock is high and the change of the division ratio is not in time when the change enable signal is output after detecting the synchronization timing.

  In order to solve the above-described problem, another typical configuration of the present invention is a frequency division for generating a processor clock by dividing or multiplying an input clock in a microcomputer clock control circuit capable of changing a processor clock of a processor. A frequency divider or a multiplier, a frequency divider or a multiplier for generating a clock of another circuit by dividing or multiplying an input clock, and outputting a clock warning signal before the clock of the other circuit, and a clock warning signal And a synchronization circuit that shifts the timing of the processor clock based on the above and maintains the synchronization relationship with the clocks of other circuits.

  According to the above configuration, the synchronization circuit adjusts the timing of the processor clock based on the clock notice signal so that the synchronization relationship between the processor clock and the clocks of other circuits is maintained. Therefore, when changing the processor clock, it is possible to immediately reflect the change in the division ratio of the divider that generates the processor clock (or the multiplication ratio of the multiplier) without waiting until the timing of synchronization with the clock of another circuit. Become.

  The clock of the other circuit is a peripheral clock of a peripheral circuit cooperating with the processor or a communication clock of a communication I / F circuit that communicates with an external device, and a frequency divider that generates a clock of the other circuit or It is preferred that the divider ratio or multiplier ratio of the multiplier is not changed during operation.

  According to the above configuration, since a constant clock is supplied to the peripheral circuit and the communication I / F circuit, the operation frequency of the peripheral circuit is out of the allowable range, or the communication I / O in which the communication speed with the outside is regulated. It is possible to avoid disconnecting the communication operation of the F circuit. That is, the processing operation of the peripheral circuit being executed and the communication operation of the communication I / F circuit can be normally continued.

  According to the present invention, it is possible to provide a clock control circuit for a microcomputer that can prevent a problem caused by switching of processor clocks and can normally continue an operation being executed.

It is a figure which shows the block diagram which shows schematic structure of the clock control circuit of the microcomputer concerning 1st Embodiment of this invention. 2 is a timing chart when switching the turbo operation of the clock control circuit of the microcomputer shown in FIG. 2 is a timing chart when switching a low-speed operation of the clock control circuit of the microcomputer shown in FIG. It is a block diagram which shows schematic structure of the clock control circuit of the microcomputer concerning 2nd Embodiment of this invention. FIG. 5 is a timing chart when switching the turbo operation of the clock control circuit of the microcomputer shown in FIG. 4. FIG. It is a figure which shows the block diagram which shows schematic structure of the clock control circuit of the microcomputer concerning 3rd Embodiment of this invention. It is a timing chart at the time of turbo operation switching of the clock control circuit of the microcomputer shown in FIG. It is a block diagram which shows schematic structure of the clock control circuit of the microcomputer as a comparative example with respect to this invention.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. The dimensions, materials, and other specific numerical values shown in the embodiments are merely examples for facilitating understanding of the invention, and do not limit the present invention unless otherwise specified. In the present specification and drawings, elements having substantially the same function and configuration are denoted by the same reference numerals, and redundant description is omitted, and elements not directly related to the present invention are not illustrated. To do.

[First embodiment]
FIG. 1 is a block diagram showing a schematic configuration of a clock control circuit (hereinafter referred to as “clock control circuit 110”) of the microcomputer according to the first embodiment of the present invention. As shown in FIG. 1, in the first embodiment, the microcomputer 100 includes a processor 102, a peripheral circuit 104, a communication I / F circuit 106, a bus 108, and a clock control circuit 110. The clock control circuit 110 includes a multiplier 112, frequency dividers 114, 116, and 118, a change enable register 120, a change enable circuit 122, and a clock setting register 124. The microcomputer 100 is used for, for example, a field device.

  The processor 102, peripheral circuit 104, communication I / F circuit 106, change enable register 120, and clock setting register 124 are connected via the bus 108. The processor 102 is hardware for operating software, and mainly performs arithmetic processing. The peripheral circuit 104 is hardware that performs a predetermined processing operation in cooperation with the processor 102, and includes various controllers, a ROM, a RAM, and the like. The communication I / F circuit 106 communicates with an external device via the communication bus 126.

  The multiplier 112 multiplies the external clock 128 to generate a PLL clock 130 as an input clock that is input to the frequency dividers 114, 116, and 118. The frequency divider 114 divides the PLL clock 130 to generate a processor clock 132 to be supplied to the processor 102. The frequency divider 116 generates a peripheral clock 134 (a clock of another circuit) to be supplied to the peripheral circuit 104. The frequency divider 118 generates a communication clock 136 (a clock of another circuit) to be supplied to the communication I / F circuit 106. The PLL clock 130, the processor clock 132, the peripheral clock 134, and the communication clock 136 are also supplied to the change enable circuit 122.

  In the clock setting register 124, the multiplication ratio of the multiplier 112 and the division ratios of the frequency dividers 114, 116, and 118 are set. The clock setting register 124 uses the set multiplication ratio as the multiplication ratio setting signal 142, the set division ratios as the division ratio setting signals 144, 146, and 148, and the multiplier 112 and the respective dividers 114. , 116, 118.

  In the clock control circuit 110, even if a new division ratio is set in the clock setting register 124, the new division ratio is not immediately reflected in the frequency dividers 114, 116, and 118. The frequency division ratios of the frequency dividers 114, 116, and 118 are changed through a predetermined procedure. The predetermined procedure is a procedure from 1) to 4) below.

  1) As the processor 102 sets a new division ratio in the clock setting register 124, data indicating that the new division ratio is valid is written in the change enable register 120. 2) The change enable register 120 outputs a division ratio change request signal 138 to the change enable circuit 122. 3) The change enable circuit 122 that has detected the division ratio change request signal 138 detects the synchronization timing of the valid edges of the processor clock 132, the peripheral clock 134, and the communication clock 136, and divides them into the frequency dividers 114, 116, and 118. A change enable signal 140 for instructing a change in the ratio is output. 4) The frequency dividers 114, 116, 118 detect the change enable signal 140 and change the frequency division ratio to the one indicated by the frequency division ratio setting signals 144, 146, 148 output from the clock setting register 124.

  Hereinafter, the operation of the clock control circuit 110 will be described with a specific example. FIG. 2 is a timing chart when the clock control circuit 110 switches the turbo operation. FIG. 3 is a timing chart when the clock control circuit 110 is switched at a low speed. In FIG. 2, the frequency division ratio of the frequency divider 114 that generates the processor clock 132 is schematically 4 (frequency division by 4), and the frequency division ratio of the frequency divider 116 that generates the peripheral clock 134 is 8 (frequency division by 8). ), The frequency dividing ratio of the frequency divider 118 that generates the communication clock 136 is set to 16 (frequency division of 16), and the frequency dividing ratio of the frequency divider 114 that generates the processor clock 132 as the switching to the turbo operation is set to 2 (2 frequency division). The case of changing to (lap) is illustrated. FIG. 3 illustrates switching from the turbo operation to the low speed operation in which the frequency of the processor clock 132 is lowered and returned to the original state (the frequency dividing ratio of the frequency divider 114 is set to 4 (divided by 4)).

  As shown in FIG. 2, after the system operation starts, when the processor 102 is overloaded and the turbo operation is necessary, the processor 102 adds a new frequency divider 114 to the clock setting register 124 via the bus 108. The ratio is set to 2 (divided by 2). The new frequency division ratio of 2 set in the clock setting register 124 is output to the frequency divider 114 as the frequency division ratio setting signal 144.

  The processor 102 writes data indicating the setting valid to the change enable register 120 in order to validate the frequency division ratio setting value 144 output from the clock setting register 124. The change enable register 120 receives the writing of the data indicating that the setting is valid, and outputs a frequency division ratio change request signal 138 to the change enable circuit 122 to indicate that the frequency division ratio change request has occurred. To communicate.

  When the change enable circuit 122 detects the frequency division ratio change request signal 138, the change enable circuit 122 detects the timing (synchronization timing) at which all of the processor clock 132, the peripheral clock 134, and the communication clock 136 rise in synchronization with the PLL clock 130. Then, along with the detection of the synchronization timing, a change enable signal 140 that instructs the frequency dividers 114, 116, and 118 to change the frequency division ratio is output. Here, the change enable signal 140 is output for one cycle of the PLL clock 130. The change enable signal 140 is also supplied to the change enable register 120, and when this is detected, the frequency division ratio change request signal 138 is stopped.

  When the frequency dividers 114, 116, 118 detect the change enable signal 140, the frequency dividers 114, 116, 118 change the frequency division ratios indicated by the frequency division ratio setting signals 144, 146, 148 output from the clock setting register 124. As a result, the frequency division ratio of the frequency divider 114 that generates the processor clock 132 is switched to 2, and the processing capability of the processor 102 is improved by the turbo operation.

  Note that the processor clock 132 is supplied to the processor 102 that mainly performs arithmetic processing, and the maximum frequency is set higher than the frequency of the peripheral clock 134. Further, the frequency of the peripheral clock 134 of the peripheral circuit 104 that cooperates with the processor 102 is set higher than the frequency of the communication clock 136. The frequency of the processor clock 132 during the turbo operation is set so as to maintain a synchronous relationship with clocks of other circuits (peripheral clock 134 and communication clock 136) even after switching.

  As shown in FIG. 3, after switching to turbo operation, when the processor 102 detects that turbo operation is not required, the processor 102 connects the clock setting register 124 via the bus 108 to reduce the frequency of the processor clock 132. 4 is again set as the frequency division ratio of the frequency divider 114 (4 frequency division). The division ratio of 4 set in the clock setting register 124 is output to the frequency divider 114 as the division ratio setting signal 144.

  The processor 102 writes data indicating the setting valid to the change enable register 120 in order to validate the frequency division ratio setting value 144 output from the clock setting register 124. The change enable register 120 receives the writing of the data indicating that the setting is valid, and outputs a frequency division ratio change request signal 138 to the change enable circuit 122 to indicate that the frequency division ratio change request has occurred. To communicate.

  When the change enable circuit 122 detects the frequency division ratio change request signal 138, the change enable circuit 122 detects the timing (synchronization timing) at which all of the processor clock 132, the peripheral clock 134, and the communication clock 136 rise in synchronization with the PLL clock 130. Then, along with the detection of the synchronization timing, a change enable signal 140 that instructs the frequency dividers 114, 116, and 118 to change the frequency division ratio is output.

  When the frequency dividers 114, 116, 118 detect the change enable signal 140, the frequency dividers 114, 116, 118 change the frequency division ratios indicated by the frequency division ratio setting signals 144, 146, 148 output from the clock setting register 124. As a result, the frequency division ratio of the frequency divider 114 that generates the processor clock 132 is switched again to 4, and the frequency of the processor clock 132 is lowered. By reducing the frequency of the processor clock 132, power consumption and heat generation of the microcomputer 100 can be suppressed.

  Although the case where the frequency division ratio is returned to 4 again from the turbo operation has been described here, the present invention is not limited to this, and the frequency of the processor clock can be further reduced. Even in this case, the frequency of the processor clock 132 is set so that the synchronous relationship with the clocks of other circuits (peripheral clock 134, communication clock 136) can be maintained even after switching. For example, the frequency division ratio of the frequency divider 114 of the processor clock 132 may be set to 8.

  According to the configuration described above, the frequency of the processor clock 132 can be increased or decreased without changing the frequencies of the peripheral clock 134 of the peripheral circuit 104 and the communication clock 136 of the communication I / F circuit 106. . If the frequency of the peripheral circuit 104 or the communication I / F circuit 106 is changed during the execution of the operation (during the processing operation or the communication operation), the operation may not be normally continued. For example, if the communication clock 136 is increased while the communication speed of the communication I / F circuit 106 is set to 9600 bps and the communication operation is being executed at the communication speed, the synchronization relationship with the external device is broken and the communication operation is normal. May not be able to continue.

  Here, since the frequency of the processor clock 132 is switched without switching the frequency of other circuits (peripheral circuit 104 and communication I / F circuit 106), the operation being executed can be normally continued. Switching of the frequency of the processor clock 132 is performed by the change enable circuit 122 detecting the synchronization timing of the peripheral clock 134 and the communication clock 136. Therefore, even after the switching of the processor clock 132, the processor clock 132 and the peripheral clock are switched. The synchronization relationship between the clock 134 and the communication clock 136 can be maintained. Therefore, even when the processor clock 132 is switched during access from the processor 102 to another circuit (peripheral circuit 104, communication I / F circuit 106), the operation can be normally continued.

  In the clock control circuit 110, it is not necessary to change the frequency dividing ratio of the frequency dividers 116 and 118. By making it possible to change the frequency dividing ratios of the frequency dividers 116 and 118, the width that can be handled by the microcomputer 100 is widened, so that common use between products can be promoted.

(Comparative example)
FIG. 8 is a block diagram showing a schematic configuration of a clock control circuit (hereinafter referred to as “clock control circuit 410”) of a microcomputer as a comparative example for the present invention. As shown in FIG. 8, in this comparative example, the microcomputer 400 includes a processor 102, a peripheral circuit 104, a communication I / F circuit 106, a bus 108, and a clock control circuit 410. The clock control circuit 410 includes a multiplier 112, a frequency divider 414, and a clock setting register 124.

  In the clock control circuit 410 of the comparative example, the multiplier 112 multiplies the external clock 128 to generate the PLL clock 130. The frequency divider 414 divides the PLL clock to generate a system clock 430a. A processor clock 432, a peripheral clock 434, and a communication clock 436 are generated from the system clock 430a and supplied to the processor 102, the peripheral circuit 104, and the communication I / F circuit 106, respectively. The multiplication ratio of the multiplier 112 and the division ratio of the frequency divider 414 are set to values indicated by the multiplication ratio setting signal 142 and the division ratio setting signal 444 issued from the clock setting register 124.

  In the clock control circuit 410 of the comparative example, when the processor 102 is overloaded and the turbo operation is necessary after the system operation starts, the processor 102 adds a new multiplier 112 to the clock setting register 124 via the bus 108. A new frequency division ratio of the frequency divider 114 is set. The new multiplication ratio and the new division ratio set in the clock setting register 124 are output to the multiplier 112 and the frequency divider 414 as the multiplication ratio setting signal 142 and the division ratio setting signal 444, respectively, and reflected. As a result, the system clock 430a is switched at high speed, and the frequencies of the processor clock 432, the peripheral clock 434, and the communication clock 436 are increased.

  If the processor 102 detects that the turbo operation is unnecessary after switching the turbo operation, the system clock 430a is switched to a low speed in the same procedure as described above, and the frequencies of the processor clock 432, the peripheral clock 434, and the communication clock 436 are changed. Be lowered.

  In the comparative example described above, the clock frequency of the peripheral circuit 104 and the communication I / F circuit 106 is also switched with the switching of the system clock 430a. Therefore, there is a possibility that the peripheral circuit 104 and the communication I / F circuit 106 cannot normally continue the operation being executed. On the other hand, according to the clock control circuit 110 according to the first embodiment, it is possible to prevent a problem from occurring due to switching of the processor clock, and to continue the operation being executed normally.

(Application examples)
As an application example of the clock control circuit 110 according to the first embodiment, it is possible to synchronize with other circuits on condition that the idle state of other circuits (the peripheral circuit 104 and the communication I / F circuit 106) can be detected. It is also possible to change the frequency division ratio at the same time as all the frequency dividers 114, 116, 118 at the timing when the frequency division ratio change request signal 138 is output without waiting for the timing. As a result, the synchronization relationship between the clocks can be maintained, and the processor clocks can be switched quickly without causing a problem.

[Second Embodiment]
FIG. 4 is a block diagram showing a schematic configuration of a clock control circuit (hereinafter referred to as “clock control circuit 210”) of the microcomputer according to the second embodiment of the present invention. As shown in FIG. 4, in the second embodiment, the clock control circuit 210 in the microcomputer 200 generates the frequency divider 114 that generates the processor clock 132, the frequency divider 116 that generates the peripheral clock 134, and the communication clock 136. A frequency divider 118 is provided.

  The frequency divider 114 outputs a clock warning signal 254 before the processor clock 132, the frequency divider 116 outputs a clock warning signal 256 before the peripheral clock 134, and the frequency divider 118 clocks before the communication clock 136. A notice signal 258 is output. The change enable circuit 222 detects the synchronization timing of the processor clock 132, the peripheral clock 134, and the communication clock 136 based on the clock notice signals 254, 256, and 258, and changes enable signals to the frequency dividers 114, 116, and 118, respectively. 140 is output.

  FIG. 5 is a timing chart when the clock control circuit 210 switches the turbo operation. As shown in FIG. 5, in the second embodiment, the change enable circuit 222 detects in advance the synchronization timing immediately after the processor clock 132, the peripheral clock 134, and the communication clock 136 based on the clock notice signals 254, 256, and 258. The change enable signal 140 is output earlier than in the first embodiment. Therefore, the case where the frequency of the processor clock 132 is high and the change enable signal 140 is output after the synchronization timing is detected cannot be changed in time.

  When the power supply is limited as in a field device, the clock notice signals 254, 256, and 258 are output only when the change enable register 120 outputs the division ratio change request signal 138. It is good to configure. As a result, it is not necessary to always output the clock notice signals 254, 256, and 258, so that power saving can be achieved.

[Third embodiment]
FIG. 6 is a block diagram showing a schematic configuration of a clock control circuit (hereinafter referred to as “clock control circuit 310”) of the microcomputer according to the third embodiment of the present invention. As shown in FIG. 6, the third embodiment is different from the second embodiment in that a clock control circuit 310 in a microcomputer 300 includes a synchronization circuit 322. Hereinafter, the operation of the synchronization circuit 322 will be described. In addition, about the element which has the function and structure substantially the same as 2nd Embodiment, duplication description is abbreviate | omitted by attaching | subjecting the same code | symbol.

  FIG. 7 is a timing chart when the clock control circuit 310 switches the turbo operation. As shown in FIG. 7, in the third embodiment, when a new division ratio of the frequency divider 114 is output as the division ratio setting signal 144 from the clock setting register 124, the new division ratio is immediately set. Reflected. Since the frequency division ratio of the frequency divider 114 is reflected without waiting for the synchronization timing with the peripheral clock 134 and the communication clock 136, the processing capability of the processor 102 can be immediately increased. However, since the synchronization relationship between the processor clock 132, the peripheral clock 134, and the communication clock 136 is not maintained as it is, there is a possibility that data is lost or it is difficult to continue normal operation. .

  Therefore, the synchronization circuit 322 adjusts the processor clock 132 to synchronize and output the clock at the timing when the peripheral clock 134 and the communication clock 136 are synchronized. However, if the processor clock 132 is simply output in synchronization with the synchronization timing with other circuits, the interval from the immediately preceding rising edge (pulse) is less than or equal to the period of the processor clock 132 at that time, so an instantaneously high frequency Thus, the processor 102 is operated. If this high frequency exceeds the operable frequency range of the processor 102, the processor 102 may hang up, be reset, or malfunction.

  Therefore, when the synchronization circuit 322 detects that the timing for synchronizing the clocks of the other circuits has arrived based on the clock notice signals 256 and 258 of the other circuits (peripheral clock 134, communication clock 136), the synchronization is performed. The output of the processor clock 132 immediately before the timing is thinned out, waits for processing to output the clock at the synchronous timing. In FIG. 7, the synchronization circuit 322 stops the rise (pulse) of the processor clock 132 immediately before the synchronization timing and matches the synchronization timing with the peripheral clock 134 and the communication clock 136.

  As a result, the processor clock 132 can be output at the synchronization timing while preventing the operating frequency of the processor 102 from becoming abnormally high. Therefore, it is possible to continue the operation of the processor 102 safely. In order to realize the above-described operation, it is necessary to output the clock notice signals 256 and 258 of other circuits before one clock of the processor clock 132.

  That is, according to the configuration of the third embodiment, a request to change the division ratio of the processor clock 132 is immediately reflected to obtain a high processing capability, and the operation of the processor 102 can be continued normally and Can be synchronized.

  As mentioned above, although preferred embodiment of this invention was described referring an accompanying drawing, it cannot be overemphasized that this invention is not limited to this example. It will be apparent to those skilled in the art that various changes and modifications can be made within the scope of the claims, and these are naturally within the technical scope of the present invention. Understood.

  For example, in the present embodiment, the configuration in which the frequency division ratios of the frequency dividers 114, 116, and 118 that generate the processor clock 132 are changed has been described. However, the frequency division ratio of the multiplier may be changed in place of the frequency divider. Alternatively, it may be configured to generate a clock having an arbitrary magnification by combining a frequency divider and a multiplier.

  The present invention can be used for a clock control circuit of a microcomputer that can switch a processor clock.

DESCRIPTION OF SYMBOLS 100, 200, 300 ... Microcomputer, 102 ... Processor, 104 ... Peripheral circuit, 106 ... Communication I / F circuit, 108 ... Bus, 110, 210, 310 ... Clock control circuit, 112 ... Multiplier, 114, 116, 118 ... Frequency divider, 120 ... change enable register, 122, 222 ... change enable circuit, 124 ... clock setting register, 126 ... communication bus, 128 ... external clock, 130 ... PLL clock (input clock), 132 ... processor clock, 134 ... Peripheral clock, 136 ... Communication clock, 138 ... Division ratio change request signal, 140 ... Change enable signal, 142 ... Multiplication ratio setting signal, 144,146,148 ... Division ratio setting signal, 254, 256, 258 ... Clock notice Signal, 322 ... Synchronization circuit

Claims (4)

In the microcomputer clock control circuit that can change the processor clock of the processor,
A frequency divider or multiplier for dividing or multiplying an input clock to generate the processor clock; and
A change enable circuit that detects a synchronization timing of the processor clock and a clock of another circuit and outputs a change enable signal that instructs the frequency divider or multiplier to change the division ratio or the multiplication ratio;
A microcomputer clock control circuit comprising: In the microcomputer clock control circuit that can change the processor clock of the processor,
A frequency divider or a multiplier for dividing or multiplying an input clock to generate the processor clock and outputting a clock warning signal before the processor clock;
A frequency divider or a multiplier for dividing or multiplying an input clock to generate a clock for another circuit and outputting a clock warning signal before the clock for the other circuit;
A change that detects the synchronization timing of the processor clock and the clock of the other circuit based on the clock notice signal and instructs the frequency divider or multiplier to change the division ratio or the multiplication ratio. A change enable circuit for outputting an enable signal;
A microcomputer clock control circuit comprising: In the microcomputer clock control circuit that can change the processor clock of the processor,
A divider or multiplier for dividing or multiplying an input clock to generate the processor clock;
A frequency divider or a multiplier for dividing or multiplying an input clock to generate a clock for another circuit and outputting a clock warning signal before the clock for the other circuit;
A synchronization circuit that shifts the timing of the processor clock based on the clock notice signal and maintains a synchronous relationship with the clock of the other circuit;
A microcomputer clock control circuit comprising:   The clock of the other circuit is a peripheral clock of a peripheral circuit that cooperates with the processor or a communication clock of a communication I / F circuit that communicates with an external device, and a frequency divider that generates a clock of the other circuit or 4. The microcomputer clock control circuit according to claim 1, wherein a frequency division ratio or a frequency multiplication ratio of the multiplier is not changed during operation.

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