KR20000003533A - Input frequency judging method to revise clock of microwave oven - Google Patents

Abstract

PURPOSE: An input frequency judging method to revise the clock of a microwave oven is provided to make a cooking hour accurate and to improve the reliability of the product by judging the frequency and revising counting of the clock. CONSTITUTION: An input frequency judging method to revise the clock of a microwave oven comprises:register storing process(S2) at a routine(S1) of an interrupt by an interrupt signal input from outside; judging(S3) the completion of the frequency judge after storing the register value of a timer at the register storing process; processing the interrupt signal input from the outside to the judging process of the setting up frequency judging flag for the set up delayed time at a delayed time operation process(S4); and processing to a first count judging process(S6) if the interrupt signal and the flag are set up according to the result of the frequency judging flag setting up judging process(S5).

Description

Input Frequency Determination Method for Clock Calibration of Microwave Oven

The present invention relates to an input frequency determination method for correcting a clock of a microwave oven, and more particularly, even when an external power source frequency such as 65 Hz, 55 Hz, 45 Hz, etc., which is an unstable frequency other than 50 Hz or 60 Hz is input thereto. The present invention relates to a method for determining an input frequency for correcting a clock of a microwave oven, by which a frequency to be corrected can be corrected.

In general, the counting operation of the clock applied to the microwave is operated by reading the power frequency of the region. As shown in FIG. 1, the AC power input from the outside is DC power through the transformer T and the rectifier 70. Rectified and converted into clock pulses through the smoothing unit 71, and applied to the switching unit 72. Then, the switching unit 72 performs a switching operation periodically by an input signal, and an interrupt signal is periodically input to the external input terminal EXINT of the microcomputer 73 by this switching operation. At this time, the timer 74 performs a count operation on the microcomputer 73 at a period of time (0.2 msec). Therefore, the microcomputer 73 may determine the power frequency currently input by reading a count value output from the timer 74 during a period when the interrupt signal is input due to the switching operation of the switching unit 72. . The microcomputer 73 applies a predetermined signal to the clock controller 75 so that the correct time is counted.

That is, as shown in FIG. 2, when a 60 Hz power frequency is input, one period T1 is 16.67 msec, and when a 50 Hz power frequency is input, one period is 20 msec. Therefore, as shown in FIG. 3A, the microcomputer internally decrements the counter operation sequentially (in this case, the timer period is 0.2 msec and the counter data is a hexadecimal register).

At this time, a rising edge is generated at the A position as the commercial frequency input during the internal counter operation is continuously shown in FIG. Then, at this time, the counter value of the internal timer T3 (the register value at which the timer counters at a period of 0.2 msec) is read to determine that the current frequency is 60 Hz.

In addition, when a rising edge occurs at the B position as the commercial frequency input during the internal counter operation is shown in FIG. 3C, the microcomputer 73 reads the counter value of the internal timer T3 at the present frequency. Determines that is 50 Hz.

Therefore, if the current determined input frequency is 60 Hz, the microcomputer 73 counts 1 second when an interrupt occurs 60 times through the external input terminal. Also, if the current determined frequency is 50 Hz, the microcomputer 73 interrupts the external input terminal. If it occurs 50 times, this time is counted as 1 second to maintain accurate clock operation.

On the other hand, it is possible to determine the power frequency by the interrupt signal input to the external input terminal as described above is possible by performing the counter operation while reducing the register value, which is the hexadecimal data of the timer in 0.2msec period, that is, shown in FIG. As shown in the figure, the hexadecimal data of the timer is counted down from $ FF to 0.2msec. When the interrupt signal is input from $ B1 (15.6 msec) to $ A7 (17.6msec), the rated frequency is 60. If the interrupt signal is input at a time S2 between $ A (19.0 msec) and $ 96 (21.0 msec), the rated frequency at this time is determined as 50 hertz.

A detailed frequency determination method as shown in FIG. 5 is as follows.

First, the interrupt routine S51 proceeds to the register storing step S52 by the interrupt signal input from the outside. Therefore, in the register storing step S52, the register value of the timer is stored and the flow proceeds to the frequency determination end determination step S3. Therefore, if it is determined that the input frequency determination is not finished as determined by the frequency determination end determination step (S53), the process proceeds to the delay time operation step (S4). Therefore, the delay time operation step S4 proceeds to the frequency determination flag setting determination step S55 with a delay time set for the interrupt signal input from the outside. Therefore, when it is determined in the frequency determination flag setting determination step (S55) that the flag for counting the input interrupt signal and the internal timer is set, the process proceeds to the first count determination step (S56).

Therefore, when it is determined in the first counter determination step S56 that the timer counter value when the rising edge is generated from the input interrupt signal is greater than $ 96, the process proceeds to the second counter determination step S77. Therefore, when it is determined in the second counter determination step (S57) that the timer counter value when the rising edge is generated is not greater than or equal to $ A0 in the input interrupt signal, the 50 Hz first flag setting determination step (S58). Proceed to).

Therefore, if it is determined in the 50 Hz single flag setting decision step (S58) that the current 50 Hz flag is determined once, proceed to the frequency judging flag setting step (S62) to reset the frequency judgment flag according to the input frequency, The process proceeds to the mother counter setting step (S63). Therefore, in this timer counter setting step S63, the register value, which is a timer count, is input again as $ FF, and the flow advances to the timer operation step S64. Therefore, in this timer operation step (S64), the $ FF register value, which is the current timer townter, is decremented at 0.2msec period and proceeds to the register loading step (S66) to read the currently output register value and return to the main routine. The routine returns to the routine S51 to repeat the loop.

On the other hand, if it is determined in the second counter determination step S57 that the timer counter value when the rising edge is generated from the input interrupt signal is greater than $ A0, the process proceeds to the third counter determination step S59. At this time, if it is determined in the third counter determination step S59 that the timer counter value when the rising edge is generated from the input interrupt signal is greater than $ A7, the process proceeds to the fourth counter determination step S60. Therefore, if it is determined in the fourth counter determination step (S60) that the timer counter value when the rising edge is generated is not greater than or equal to $ B1 from the input interrupt signal, the 60Hz one time flag setting determination step (S61). Proceed to). Therefore, if it is determined in the 60 Hz one time flag setting determination step (S61) that the input 60 Hz flag setting is determined once, the process proceeds to the frequency determination flag setting step (S62) and repeats the operation for frequency determination again. In addition, if it is determined that the inputted 60 Hz flag setting is not one time, that is, the determination is made twice, the determination process of the frequency determination end flag proceeds to step S65. Accordingly, in this frequency determination end flag setting step (S65), an end flag is set according to the frequency determination and the process proceeds to the register loading step (S66). Therefore, the register load step S66 reads the current register value and performs a clock count operation by the frequency set to return to the main routine.

On the other hand, if it is determined in the 50 Hz one time flag setting determination step (S58) that the current 50 Hz flag setting is not one time, that is, if it is determined as two times, the loop as described above in the frequency determination end flag setting step (S65). Do this.

As described above, the AC input waveform is converted into a clock pulse to read the internal counter value of the rising edge of the waveform to determine whether the input power frequency is 50 Hz or 60 Hz so that the clock is counted. It's working.

However, by counting the clock using the frequency input from the microwave in this way, it is possible to have a precise clock function at a low price, but in a country where the frequency is unstable, the user is mistaken that the microwave oven itself is abnormal due to the fast or slow clock. Also, due to the inaccurate time set for cooking, a phenomenon such as burning of food appears due to exceeding a predetermined cooking time, resulting in a problem that the reliability of the product is lowered.

Therefore, the present invention was devised to compensate for such a problem, and even though the unstable frequencies such as the conventional 65 Hz, 55 Hz and 45 Hz were input, the frequency was determined to be close to 50 Hz and 60 Hz, but in the present application, 50 Hz Even if input frequency of unstable power frequency such as 65Hz, 55Hz and 45Hz is inputted, it is possible to determine the corresponding frequency and perform the counting operation of the clock accurately. The purpose is to provide an input frequency determination method for clock correction.

In order to achieve the above object, the present invention provides a frequency determination flag setting process of setting a flag for counting an interrupt signal according to an input frequency by an internal timer with a set delay time, and an interrupt signal according to an input frequency having a first count value. If the range is within the first frequency determination process to read the register value at this time to determine the frequency of 45Hz, and if the interrupt signal according to the input frequency is within the second count value range, the register value at this time is read to the frequency of 50Hz A second frequency judging process for judging, a third frequency judging process for reading a register value at this time and judging it as a frequency of 55 hertz when the interrupt signal according to the input frequency is within the third count value range, and an interrupt signal according to the input frequency Is within the range of the fourth count value, the register value is read and 60 Hz is read. And a fourth frequency judging process for judging by frequency, and a fifth frequency judging process for reading a register value at this time and judging at a frequency of 65 hertz if the interrupt signal according to the input frequency is within the fifth count value range. .

1 is a view for explaining a frequency determination operation for the clock counter of the conventional microwave oven.

2 is a diagram illustrating one period of a clock pulse according to each rated frequency according to an input frequency.

3 is a diagram illustrating input frequency determination in a conventional microcomputer.

4 is a view for explaining determination of an input frequency by a clock pulse output from a conventional timer.

FIG. 5 is a flowchart for explaining conventional input frequency detection by frequency determination applied to FIG. 4; FIG.

6 is a view for explaining the determination of the input frequency by the clock pulse output from the timer according to the present invention.

FIG. 7 is a flow chart illustrating input frequency detection of the present invention in accordance with the frequency determination applied to FIG. 6; FIG.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

According to the present invention, the interrupt signal inputted from the outside is further subdivided to decrease the register value, which is the hexadecimal data of the timer, by 0.2 msec period, and to read the register value when the rising edge occurs in the interrupt signal input when the counter operation is performed. Determine the frequency.

That is, as shown in FIG. 6, when the hexadecimal data of the timer is counted down from $ FF to 0.2msec period, the interrupt signal is inputted from section A between $ B8 (14.2msec) and $ B2 (15.4msec). The rated frequency of is determined to be 65Hz, and when the interrupt signal is input to the B section between $ AF (16.0msec) and $ A9 (17.6msec), which is an internal counter, the rated frequency is determined to be 60Hz, and the interrupt signal If the internal counter when is input is in the range of section C between $ A6 (17.8msec) and $ A1 (18.8msec), the rated frequency at this time is determined as 55Hz.

If the internal counter when the interrupt signal is input is in the range of D between $ 9E (19.4 msec) and $ 98 (20.6 msec), the rated frequency is determined as 50 Hz, and the internal counter when the interrupt signal is input. If the range is E, between $ 95 (21.2 msec) and $ 8F (22.4 msec), then the rated frequency is determined to be 45 hertz. Therefore, even if the input frequency is unstable to some extent, it is possible to determine the frequency for accurate clock operation by reading the register value of the internal counter according to the corresponding frequency.

Here, the input frequency determination method for clock correction proceeds to the register storage step S2 in the interrupt routine S1 by the interrupt signal input from the outside, as shown in FIGS. 7A and 7B. Therefore, the register storing step S2 stores the register value of the timer and proceeds to the frequency determination end determination step S3. Therefore, when it is determined that the input frequency determination is not finished as determined by the frequency determination end determination step S3, the process proceeds to the delay time operation step S4. Therefore, the delay time operation step S4 proceeds to the frequency determination flag setting determination step S5 with a delay time set for the interrupt signal input from the outside. Therefore, if it is determined in the frequency determination flag setting determination step S5 that the flag for counting the interrupt signal and the internal timer that is input after the input delay time is inputted, the flow proceeds to the first count determination step S6.

Therefore, when it is determined in the first counter determination step S6 that the timer counter value when the rising edge is generated is less than $ 8F in the input interrupt signal, the process proceeds to the second counter determination step S7. Then, when it is determined in the second counter determination step S7 that the timer counter value when the rising edge is generated is not greater than or equal to $ 95 as a result of the input interrupt signal, the 45 Hz first flag setting determination step S8 is performed. Proceed to Therefore, if it is determined in the 45 Hz first flag setting decision step S8 that the current 45 Hz flag setting is determined once, that is, when flag 1 is not set, the process proceeds to the frequency determination flag setting step S21. Therefore, in this timer resetting step S21, the register value, which is a timer count, is input again as $ FF, and the flow advances to the timer operation step S22. Therefore, in this timer operation step (S22), the $ FF register value, which is the current timer townter, is decremented at 0.2msec period, and the register load step (S24) is read to read the current register value and returned to the main routine. The loop returns to the routine S1 to resume operation of the loop.

On the other hand, if it is determined in the second counter determination step S7 that the timer counter value when the rising edge is generated is greater than or equal to $ 95 in the input interrupt signal, the process proceeds to the third counter determination step S9. In this case, when it is determined that the timer counter value when the rising edge is generated from the input interrupt signal is greater than $ 98 as a result of the determination in the third counter determination step S9, the process proceeds to the fourth counter determination step S10. Therefore, if it is determined in the fourth counter determination step (S10) that the timer counter value when the rising edge is generated is not greater than or equal to $ 9E in the input interrupt signal, the 50Hz one-time flag setting determination step (S11). Proceed to). Therefore, if it is determined in the 50 Hz one time flag setting determination step (S11) that the input 50 Hz flag setting is determined once, the process proceeds to the frequency determination flag setting step (S21) and repeats the operation for frequency determination again. In addition, if it is determined that the input 50Hz flag setting is not one time, that is, if it is determined two times, the process proceeds to the frequency determination end flag setting step (S24). Accordingly, in this frequency determination end flag setting step (S24), the end flag is set in accordance with the frequency determination, and the process proceeds to the register loading step (S25). Therefore, in this register loading step (S25), the current counting register value is read and a clock count operation by the frequency set to return to the main routine is performed.

If it is determined in the fourth counter determining step S10 that the timer counter value when the rising edge is generated is greater than or equal to $ 9E in the input interrupt signal, the process proceeds to the fifth counter determining step S12. In this case, when it is determined that the timer counter value when the rising edge is greater than $ A1 is determined as the result of the determination in the fifth counter determination step S12, the process proceeds to the sixth counter determination step S13. Therefore, if it is determined in the sixth counter determination step (S13) that the timer counter value when the rising edge is generated is not greater than or equal to $ A6 in the input interrupt signal, the 55Hz one time flag setting determination step (S14). Proceed to). Therefore, if it is determined in the 55 Hz one-time flag setting determination step (S14) that the input 55 Hz flag setting is determined once, the process proceeds to the frequency determination flag setting step (S21) and repeats the operation for frequency determination again. In addition, if it is determined that the input 50Hz flag setting is not one time, that is, if it is determined two times, the process proceeds to the frequency determination end flag setting step (S24). Accordingly, in this frequency determination end flag setting step (S24), the end flag is set in accordance with the frequency determination, and the process proceeds to the register loading step (S25). Therefore, in this register loading step (S25), the current counting register value is read and a clock count operation by the frequency set to return to the main routine is performed.

In addition, when it is determined in the sixth counter determination step S13 that the timer counter value when the rising edge is generated is greater than or equal to $ A6 in the input interrupt signal, the process proceeds to the seventh counter determination step S15. . In this case, if it is determined that the timer counter value when the rising edge is greater than $ A9 is determined as the result of the determination in the seventh counter determination step (S15), the process proceeds to the eighth counter determination step (S16). Therefore, if it is determined in the eighth counter determination step (S16) that the timer counter value when the rising edge is generated is not greater than or equal to $ AF as a result of the input interrupt signal, the 60Hz one time flag setting determination step (S17). Proceed to). Therefore, if it is determined in the 60 Hz one time flag setting determination step (S17) that the input 60 Hz flag setting is determined once, the process proceeds to the frequency determination flag setting step (S21) and repeats the operation for frequency determination again. In addition, if it is determined that the input 50Hz flag setting is not one time, that is, if it is determined as two times, the process proceeds to the frequency determination end flag setting step S24 and operates in the loop described above.

On the other hand, if it is determined in the eighth counter determination step (S16) that the timer counter value when the rising edge is generated is greater than or equal to $ AF from the input interrupt signal, the process proceeds to the ninth counter determination step (S18). . In this case, when it is determined in the ninth counter determination step S18 that the timer counter value when the rising edge is generated is greater than $ B2 in the input interrupt signal, the flow proceeds to the tenth counter determination step S19. Therefore, when it is determined in the tenth counter determination step (S19) that the timer counter value when the rising edge is generated is not greater than or equal to $ B2 in the input interrupt signal, the 65Hz one-time flag setting determination step (S20). Proceed to). Therefore, if it is determined in the 65 Hz one-time flag setting determination step (S20) that the input 65 Hz flag setting is determined once, the process proceeds to the frequency determination flag setting step (S21) and repeats the operation for frequency determination again. In addition, if it is determined that the inputted flag setting of 65 Hz is not one time, that is, if it is determined two times, the process proceeds to the frequency determination end flag setting step (S24).

Meanwhile, as a result of the determination in the frequency determination flag setting determination step (S5), a flag for counting the interrupt signal and the internal timer input after a predetermined time delay operation is not set or the first counter determination step (S6) and the third counter. If it is determined in the determination step (S9), the fifth counter determination step (S12), the seventh counter determination step (S15) and the ninth counter determination step (S18) that the value of each counter is smaller than the set value, the frequency The process proceeds to the determination flag setting step S21 to repeat the loop.

As such, the present invention enlarges the input frequency band as much as possible to determine the respective frequency bands according to the corresponding frequency even if the input frequency is unstable, so that accurate time correction of the clock can be performed even if the input frequency is unstable to enable accurate cooking according to the cooking time. Of course, there is an effect that improves the reliability of the product.

Claims (3)

A frequency judgment flag setting process of setting a flag for decreasing and counting an interrupt signal according to an input frequency to a predetermined time by an internal timer with a set delay time, and if the interrupt signal according to an input frequency is within a first count value range, A first frequency determination process of determining a first frequency by reading a register value of a second frequency, and a second frequency determination of reading a register value at this time and determining it as a second frequency when an interrupt signal according to an input frequency is within a second count value range. The third frequency determination process of reading the register value at this time and determining the third frequency when the interrupt signal according to the input frequency is within the third count value, and the interrupt signal according to the input frequency is within the fourth count value range. In this case, the fourth frequency determination process of reading the register value at this time and judging by the fourth frequency, Interrupt signal and the fifth count values within the range of a fifth frequency is determined process input frequency determination method for clock calibration of microwave oven consisting of reading the register value in this case is determined by a sixth frequency corresponding to the frequency. 2. The method of claim 1, wherein when the decrement timer time of the timer is 0.2 msec, the first frequency determination process determines that the register value range, which is the first count range is greater than $ 8F and less than $ 95, is determined as 45 Hz, and the second frequency is determined. In the judging process, the register value range, which is the second count range, is determined to be 50 Hz when it is greater than $ 98 and less than $ 9E. In the third frequency judgment process, the register value range, which is greater than $ A1 and is less than $ A6, is 55 Hz. In the fourth frequency determining process, the register value range that is the second count range is greater than $ A9 and less than $ AF, which is determined as 60 Hz. In the fifth frequency determination process, the register value range is the fifth count range is $ The input frequency determination method for the clock correction of the microwave oven, characterized in that the determination is 70Hz when larger than B2 and less than $ B8. According to claim 1, If the frequency determined in each frequency determination process is input to the external input terminal (EXINT) input frequency for the clock correction of the microwave, characterized in that the clock counter operation to determine this as 1 second Judgment method.