JPS6123738B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention is applied to an electrical device having a motor or the like used in a commercial power source, or a clock or timer device that measures time based on the frequency of the input power source, and is applied to the device by discriminating the frequency of the input commercial power source. The present invention relates to a commercial power supply frequency discriminating device that sets a frequency to match the frequency of the commercial power supply.

Hereinafter, the conventional device and the present invention will be explained using a watch as an example.

A frequency obtained from an oscillation element with high frequency stability, such as a crystal resonator, or a commercial power supply frequency is used as a reference frequency in a digital counting type clock or timer device. Since the former is more expensive than the latter, the latter is generally used in devices where commercial power frequency can be easily obtained. However, as is well known, the commercial power frequency is 50Hz or 60Hz depending on the region, so conventionally,
This was dealt with by distinguishing between 50Hz-only models and 60Hz-only models, limiting the frequencies used, and installing a 50/60Hz switch.

FIG. 1 is a circuit diagram of a general digital clock that counts the commercial power frequency.

In the figure, reference numeral 1 denotes a clock LSI, which is configured to take in a reference frequency, perform counting, carry, and decoding for display. 2 is a clock light emitting diode (LED), which displays a clock according to the signal from LSI 1. 3 is a transformer, and 4 is a diode that rectifies the commercial power supply and supplies DC voltage to LSI 1. 5 and 6 are rectifier diodes for supplying DC power to the LSI 1 and the light emitting diode 2. 7 is a resistor, and the reference frequency is supplied to the LSI 1 through this resistor 7. A capacitor 8 smoothes the power rectified by the diode 4. 9
10 is a switch for setting the time, and 10 is a switch for switching to 50Hz or 60Hz depending on the power frequency used. LSI1 is this 50/60Hz
The state of the changeover switch 10 is read and a count number corresponding to one second is set.

As shown in this example, conventional devices of this type required a changeover switch depending on the frequency used. The product was shipped as a 50Hz-only model with a device equipped with a similar changeover switch on the outside, and a short-circuit inside the product with a connecting wire. In the former case, there were many problems due to improper selection of the changeover switch, and in the latter case, the same product required two types, one for 50Hz and one for 60Hz, which was extremely inconvenient for product management. .

This invention was made to eliminate the drawbacks of the conventional ones as mentioned above, and the frequency of the power supply is 50
Hz or 60Hz is automatically determined, and the device can be automatically set to a state that matches the input frequency.

An embodiment of the present invention will be described below with reference to the drawings. FIG. 2 is a block diagram showing an embodiment of the present invention, in which 21 is a clock generator that outputs a rectangular wave signal (hereinafter referred to as clock) formed from the commercial power frequency, and 22 is a clock generator that outputs a clock falling point. A falling detection section 23 detects the rising edge of the clock and outputs a rising pulse. 24 is a first detection section that is set by the falling pulse of the clock.
Flip-flop (hereinafter referred to as F/F1), 26
27 is an oscillator that outputs a reference frequency signal with a frequency sufficiently higher than the commercial power supply frequency; 29 is a 1/n frequency dividing circuit; 30 is a counting section that counts the number of frequency-divided pulses; 31 is a comparison section that compares the counted value with a constant; 3
2 is a 50/60Hz determining section, 33 is a 50Hz processing section that receives a command from the determining section 32 and sets the operating frequency of the clock, and 34 is a 60Hz processing section.

Next, the operation of this embodiment will be explained using the waveform diagram shown in FIG. 3. In addition, in Figure 3 A to N,
The solid line shows the waveform at 60Hz, and the broken line shows the waveform at 50Hz. FIG. 3A shows the waveform of the commercial power frequency signal, and FIG. 3B shows the clock waveform. This shaped clock is sent to the falling edge detection section 22 and the rising edge detection section 23, and the falling edge detection section 22 receives a pulse (hereinafter referred to as DN pulse) synchronized with the falling edge of the clock as shown in FIG. ) occurs. Similarly, rise detection section 2
3 generates a pulse (hereinafter referred to as UP pulse) synchronized with the rising edge of the clock, as shown in FIG. 3D. F/F1 (24) is set by the DN pulse and outputs “H” to its output terminal,
Open the gate of gate circuit 1 (25). The UP pulse is generated when the gate of gate circuit 1 (25) is opened.
Set F/F2 (26) and output "H". In other words, after the DN pulse, only the UP pulse is effective for F/F2.
(26) can be set. This is to prevent malfunctions caused by shortening the clock cycle when the power is turned on. Figure 3 F/F
1 (24) is shown, and the output waveform of F/F2 is shown in the same figure.

On the other hand, as shown in FIG.
(28). Gate circuit 2 (28) is F/F
2 (26) is outputting "H", the gate is opened and the reference frequency signal is input to the 1/n frequency dividing circuit 29. FIG. 3H shows a reference frequency signal input to the 1/n frequency divider circuit 29. The 1/n frequency divider circuit 29 divides the input reference frequency signal by 1/n and sends a pulse signal of the divided frequency as shown in FIG. The counting section 30 counts the number of pulses and sequentially sends the number to the comparison section 31. The comparison unit 31 compares a preset constant (“15” in this embodiment) with the count value input from the counting unit 30, and when the count value reaches “15”, the 50/60Hz determination is made. A reading end signal is output to the section 32. FIG. 3 shows the output waveform of the determination section 32. Note that the constant given to the determination unit 32 in advance is such that the time for counting pulses is longer than 1/60 second and is 1/50.
It is set to last for a period of time shorter than seconds. 50／
When the counting end signal is input from the comparison section 31, the 60Hz determination section 32 discriminates the polarity of the clock and determines the frequency of the input power source. If the clock is “H” (positive polarity), it is determined to be 60Hz, if it is “L” (negative polarity), it is determined to be 50Hz, and depending on each state, the
A determination signal is given to the Hz processing section 33 and the 60 Hz processing section 34, and at the same time, F/F1 (24) and F/F2 (26) are reset to put them in a standby state for the next determination.

When the 50Hz processing section 33 receives a signal, the clock is read 50 times as one second, and the 60Hz processing section 3
When 4 receives a signal, it sets the operating frequency of the clock so that 60 clock readings equals 1 second.

Next, a description will be given of an embodiment in which the configuration of the embodiments described above is implemented using a stored program method, which is a so-called microcomputer, in which the configuration of the embodiments described above can be achieved on a program at extremely low cost.

Figure 4 has recently begun to be used for various purposes.
This is a schematic diagram of automatic 50/60Hz frequency discrimination in a control system using a single-chip CPU with all built-in ROM, RAM, program counter, etc.

41 is a one-chip CPU that forms input ports I ₁ ~In, output ports O ₁ ~On, and the CPU clock.
It has OSC IN input, etc. 21 is a clock generator that shapes the commercial frequency and outputs a rectangular wave; 27
is a reference frequency signal generator, and the above 1-chip CPU
41 OSCIN is input. This oscillator 2
7 configures the software timer inside the CPU, so in order to obtain an accurate oscillation frequency,
Use a crystal oscillator, ceramic oscillator, etc.

FIG. 5 shows an example of a flowchart of a 50/60 Hz determination routine based on the stored program method when this one-chip CPU 41 is used, and its operation will be explained below.

In FIG. 5, after the start, a clock is input in routine 44, and if the state of the clock is "H", the routine waits until the clock becomes "L" without exiting routine 44. If the clock is "L", the routine advances to routine 45, and when the clock is input again and its state becomes "H", the routine advances to routine 46. Therefore, the clock is “L”
The routines 45 and 46 can be exited in the subsequent "H" state. This corresponds to detecting the rising edge of the clock. Routine 4
In step 6, a timer created by software is activated, and after a certain period of time, the number of counters provided in the memory is increased by one. This counter is reset at the start to start from 0. When the counter reaches a certain constant (in this embodiment, "15"), the routine proceeds to routine 47. In routine 47, the clock is input again and the state of the clock is determined. The counting time is set to be the midpoint between 1/60 seconds and 1/50 seconds, as in the embodiment shown in Fig. 3. Therefore, the result of the above judgment is "H".
If so, the frequency of the input power supply is 60Hz, and “L”
If so, it is 50Hz, so the same as above
Performs 60Hz processing and 50Hz processing.

Note that in the above embodiment, the clock is read in the 50/60Hz determination unit when the count value of the counter reaches a certain value, but if one cycle of the clock ends before the count value reaches the constant value, If the clock is "H", it is immediately determined to be 60Hz, and if one cycle of the clock does not end even if the count value reaches a certain value, that is, if it is "L", it is determined to be 50Hz. The same frequency determination as in the above embodiment can be performed.

Furthermore, in the above embodiment, a reference frequency signal having a frequency sufficiently higher than that of the clock is generated, and counting is performed based on that signal. However, the structure is not limited to this.
configured as a single timer with an intermediate length of period,
The same operation as in the above embodiment can be performed by driving this timer with the output of F/F2 and inputting the timer end output to the 50/60 Hz determining section to determine the state of the clock.

Note that in the above embodiment, 1 of the commercial power frequency signal
Although the time of the cycle is detected and the determination is made between 50Hz and 60Hz, the same effect can be obtained not only with one cycle but also with multiple cycles. In addition, in the example, one judgment
Although 50 Hz and 60 Hz are determined and such processing is performed, it is more reliable if a plurality of frequencies are determined and the frequency is determined when the same determination is made a predetermined number of times.

As described above, according to the present invention, the frequency is determined by counting the number of cycles of the reference signal and determining the polarity of the pulse when the counted value reaches the reference constant value. Since the discrimination can be performed automatically, the conventional Schmitt circuit and one-shot circuit can be omitted, and the circuit configuration can be simplified. Also,
The use of a single-chip CPU has the advantage that an inexpensive and highly reliable device can be easily obtained.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram of a watch equipped with a conventional 50/60Hz changeover switch, Fig. 2 is a block diagram of an embodiment of the present invention, Fig. 3 is an output waveform diagram of each part, and Fig. 4
The figure shows a schematic block diagram of another embodiment of the present invention using a one-chip CPU, and FIG. 5 is a flowchart of its operation. In the figure, 21 is a clock signal generator, 22
23 is a falling detection section, 23 is a rising detection section, 27 is a reference frequency signal oscillator, 29 is a 1/n frequency dividing circuit,
30 is a counting section, 31 is a comparison section, 32 is a 50/60Hz judgment section, 33 and 34 are processing sections, 41 is 1 chip
It is the CPU. In the figures, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] 1. A device that discriminates when the polarity of an input commercial power source changes and outputs a rising pulse signal when the polarity changes to positive and a falling pulse signal when the polarity changes to negative; an oscillator that outputs a reference signal with a frequency f that is sufficiently higher than the frequency; a gate circuit that passes the reference signal from the time when it receives a rising pulse following the falling pulse; and a cycle of the reference signal that passes through this gate circuit. Compare the count value of the above-mentioned counting unit with a constant set in advance to a number greater than nf/60 and smaller than nf/50 (however, n is an integer), and calculate the count value of the above-mentioned counting unit. A comparator section that outputs a counting end signal when the count reaches the above constant, and a comparator section that discriminates the polarity of the input power supply at the time when the counting end signal is received from this comparator section. a 50/60 Hz determination unit that outputs a frequency signal of 60 Hz when the frequency is negative, and closes the gate circuit;
A commercial power supply frequency determination device comprising: a processing device that sets a power supply device driven by the commercial power supply to match the frequency according to the determination result. 2. A patent claim comprising a 50/60 Hz determination unit configured to perform the operation of discriminating the polarity of the input power supply multiple times upon receiving the counting end signal, and output a frequency signal when the results match a predetermined number of times. A commercial power supply frequency determination device according to scope 1. 3. A commercial power supply frequency determination device according to claim 1, comprising a determination unit configured to determine 60Hz if the polarity of the commercial power supply becomes positive before the count of the counting unit reaches a constant. .