KR20000003446A - Poly silicon film evaporation method of a semiconductor device - Google Patents
Poly silicon film evaporation method of a semiconductor device Download PDFInfo
- Publication number
- KR20000003446A KR20000003446A KR1019980024688A KR19980024688A KR20000003446A KR 20000003446 A KR20000003446 A KR 20000003446A KR 1019980024688 A KR1019980024688 A KR 1019980024688A KR 19980024688 A KR19980024688 A KR 19980024688A KR 20000003446 A KR20000003446 A KR 20000003446A
- Authority
- KR
- South Korea
- Prior art keywords
- thin film
- polysilicon thin
- polysilicon
- mark
- semiconductor device
- Prior art date
Links
- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims abstract description 43
- 229920005591 polysilicon Polymers 0.000 title claims abstract description 42
- 239000004065 semiconductor Substances 0.000 title claims abstract description 10
- 238000001704 evaporation Methods 0.000 title abstract description 6
- 238000000034 method Methods 0.000 claims abstract description 30
- 238000005259 measurement Methods 0.000 claims abstract description 14
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims abstract description 8
- 238000004544 sputter deposition Methods 0.000 claims abstract description 5
- 229910052786 argon Inorganic materials 0.000 claims abstract description 4
- 239000010409 thin film Substances 0.000 claims description 19
- 238000000151 deposition Methods 0.000 claims description 12
- 238000004519 manufacturing process Methods 0.000 claims description 5
- 238000007736 thin film deposition technique Methods 0.000 claims 3
- 230000008020 evaporation Effects 0.000 abstract description 3
- 230000008021 deposition Effects 0.000 description 7
- 239000010408 film Substances 0.000 description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 238000002955 isolation Methods 0.000 description 2
- 239000010410 layer Substances 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000002425 crystallisation Methods 0.000 description 1
- 230000008025 crystallization Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 230000006641 stabilisation Effects 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28525—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising semiconducting material
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
- H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/485—Bit line contacts
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
Abstract
Description
본 발명은 반도체소자 제조방법에 관한 것으로, 특히 중첩정확도 측정용 마크 상에 형성되는 폴리실리콘 박막을 증착하는 방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for depositing a polysilicon thin film formed on a mark for measuring overlap accuracy.
잘 알려진 바와 같이, 메모리소자를 제조함에 있어, 전반부 마스크 공정과 후반부 마스크 공정 상의 중첩정확도를 측정하기 위해서는, 웨이퍼의 스크라이브영역에 중첩정확도를 측정하기 위한 마크를 형성하여야 한다.As is well known, in manufacturing a memory device, in order to measure the overlapping accuracy in the first half mask process and the second half mask process, a mark for measuring the overlap accuracy in the scribe area of the wafer should be formed.
도1a 및 도1b는 각각 통상의 중첩정확도 측정용 마크를 나타내는 사시도 및 평면도를 나타낸다. 도면에 도시된 바와 같이, 평면도 상에서 이 마크는 박스-인-박스(Box-In-Box)를 이루고 있어 통상 이를 박스-인-박스 마크라 부른다. 예컨대 일련의 메모리소자 제조 공정상에서 외부박스(11)는 소자분리 마스크 공정에서 형성되는 음각 패턴에 의해 만들어지고, 내부박스(12)는 게이트 마스크 공정에서 형성된 양각의 패턴에 의해 만들어진다. 이러한 구성을 갖는 마크에서 스캐닝에 의해 전기적 신호를 검출하므로써, 각 공정의 중첩정확도가 정확한지를 검출하게 된다.1A and 1B show a perspective view and a plan view, respectively, of a typical superposition accuracy measurement mark. As shown in the figure, on the top view this mark constitutes a Box-In-Box and is commonly referred to as a box-in-box mark. For example, in a series of memory device manufacturing processes, the outer box 11 is made of an intaglio pattern formed in the device isolation mask process, and the inner box 12 is made of an embossed pattern formed in the gate mask process. By detecting the electrical signal by scanning in the mark having such a configuration, it is detected whether the overlapping accuracy of each process is correct.
한편, 다이나믹 램(Dynamic RAM)은 소자가 점차 더 고집적화되어감에 따라, 비트라인 콘택 부위와 캐패시터의 스토리지노드 콘택부위에 각각 폴리실리콘 플러그(plug)를 미리 형성하여 콘택시의 공정 마진을 확보하고자 하는바, 이때 플러그용 폴리실리콘을 패터닝하기 위한 마스크 공정(이하, 플러그 마스크 공정이라 함)이 수행되며, 이 플러그 마스크 공정시에도 하부 게이트 또는 아이솔레이션 패턴들과 정확히 얼라인되어야 하기 때문에 중첩정확도를 측정하여야 한다.On the other hand, as the RAM becomes more integrated, the dynamic RAM tries to secure the process margin of contact by forming polysilicon plugs in advance in the bit line contact region and the storage node contact region of the capacitor. In this case, a mask process (hereinafter referred to as a plug mask process) for patterning the polysilicon for plugging is performed, and the overlapping accuracy is measured because the plug mask process must be exactly aligned with the lower gate or isolation patterns. shall.
도2a 및 도2b에는 플러그 마스크 공정시 그 중첩정확도를 측정하기 위한 마크의 사시도 및 평면도가 각각 도시되어 있다. 도2a 및 도2b를 참조하면, 이 마크는 3개의 박스로 이루어져 있음을 알 수 있는데, 제1박스(21)는 게이트 마스크 공정에서 형성된 음각의 패턴에 의해 생성되고, 제2박스(22)는 소자분리 마스크 공정에서 형성된 음각의 패턴에 의해 생성되며, 제3박스(23)는 플러그 마스크 공정시 양각의 포토레지스트패턴에 의해 생성된다. 이러한 플러그 마스크 공정의 중첩정확도를 측정하는 마크는 앞서 설명한 바와 같이 두 개의 박스로 구성될 수 도 있다.2A and 2B show a perspective view and a plan view of a mark for measuring the overlapping accuracy during the plug mask process, respectively. Referring to FIGS. 2A and 2B, it can be seen that the mark consists of three boxes. The first box 21 is generated by an intaglio pattern formed in the gate mask process, and the second box 22 is The third box 23 is formed by an embossed photoresist pattern during the plug mask process. The mark for measuring the overlap accuracy of the plug mask process may be composed of two boxes as described above.
그런데, 이러한 마크를 사용하여 중첩정확도를 측정함에 있어 다음과 같은 문제점이 발생된다.However, the following problem occurs in measuring the overlap accuracy using such a mark.
도3a 및 도3b는 플러그 마스크 공정의 중첩도를 측정하기 위하여 중첩마크를 두 개의 박스(3개의 박스도 동일한 문제점을 갖는다)로 형성하였을 경우로서, 먼저, 기판 상에 절연막(31)이 식각된 자리에 홈이 형성되고, 플러그용 폴리실리콘막(32)이 그 상부로 증착되었을 때 상기 홈의 단차를 따라 역시 홈을 형성되므로써 이 두 번째 홈에 의해 외부박스(A)가 생성된다. 이어서, 플러그 마스크 공정이 실시된다. 즉, 포토레지스트가 도포되고 노광 및 현상 공정으로 포토레지스트 패턴이 형성되는데, 외부박스(A) 내에 포토레지스트 패턴(33)이 형성되어 있고 이에 의해 내부박스(B)가 생성된다. 이어서, 측정장비에서 상기 마크를 스캐닝하여 전기적 신호를 읽는다.3A and 3B show an overlap mark formed of two boxes (three boxes have the same problem) in order to measure the degree of overlap of the plug mask process. First, the insulating film 31 is etched on the substrate. Grooves are formed in place, and when the plug-in polysilicon film 32 is deposited thereon, grooves are also formed along the steps of the grooves so that the outer box A is generated by this second groove. Subsequently, a plug mask process is performed. That is, a photoresist is applied and a photoresist pattern is formed by an exposure and development process. The photoresist pattern 33 is formed in the outer box A, thereby generating the inner box B. Subsequently, the mark is read by a measuring device to read an electrical signal.
그러나, 플러그용 폴리실리콘막을 높은 온도에서 증착하는 경우, 도3b에 도시된 바와 같이, 폴리실리콘의 결정립(grain)이 생성 및 성장하면서 중첩마크의 계면을 불량하게 만들기 때문에, 측정장비를 사용한 중첩도 측정시의 재현성(repeatability)을 떨어뜨려 층간 중첩정화도의 제어를 어렵게 만든다. 그리고 스텝퍼 및 스캐너에서 정렬에 사용되는 정렬키도 불량해져 장비에서의 정렬이 잘 이루어지지 않는다. 참고로 585℃에서 5000Å의 폴리실리콘막을 증착하고 3000Å까지 에치백(etch-back)해주는 경우, 앞서 언급한 문제점을 더욱 심각해지게 된다.However, when the plug polysilicon film is deposited at a high temperature, as shown in Fig. 3b, since the grains of the polysilicon are generated and grown, the interface of the overlap marks is poor, so that the degree of overlap using the measuring equipment It reduces the repeatability at the time of measurement, making it difficult to control the degree of overlap between layers. In addition, the alignment keys used for alignment in steppers and scanners are also poor, and the alignment in the equipment is difficult. For reference, when the polysilicon film is deposited at 585 ° C. and etched back to 3000 μs, the above-mentioned problem becomes more serious.
본 발명은 상기 문제점을 해결하기 위하여 안출된 것으로써, 증착된 폴리실리콘 박막에 의해 측정마크가 형성되었을 경우 이 마크를 정확히 검출할 수 있도록 하는 반도체소자의 폴리실리콘 박막 증착방법을 제공함을 그 목적으로 한다.An object of the present invention is to provide a method for depositing a polysilicon thin film of a semiconductor device which can accurately detect the mark when the measurement mark is formed by the deposited polysilicon thin film. do.
도1a 및 도1b는 각각 통상의 중첩정확도 측정용 마크를 나타내는 사시도 및 평면도.1A and 1B are a perspective view and a plan view, respectively, of a typical superposition accuracy measurement mark.
도2a 및 도2b는 플러그 마스크 공정시 그 중첩정확도를 측정하기 위한 멀티 박스 마크의 사시도 및 평면도.2A and 2B are a perspective view and a plan view of a multi-box mark for measuring the overlapping accuracy of the plug mask process.
도3a 및 도3b는 플러그 마스크 공정의 중첩도를 측정하기 위한 싱글 박스 마크의 단면도 및 평면도.3A and 3B are cross-sectional and plan views of a single box mark for measuring the degree of overlap of the plug mask process.
도4는 본 발명의 실시예를 나타내는 평면도.4 is a plan view showing an embodiment of the present invention.
도5는 종래기술과 본 발명 간의 중첩도 측정시의 재현성을 비교하기 위한 실험 결과치를 나타내는 도표.Fig. 5 is a table showing experimental results for comparing reproducibility in measuring the degree of overlap between the prior art and the present invention.
상기 목적을 달성하기 위한 본 발명은, 반도체소자 제조방법에 있어서, 증착된 폴리실리콘 박막에 의해 측정마크가 형성될 때 상기 측정마크의 재현성 확보를 위해 상기 폴리실리콘 박막을 550∼500℃의 온도 범위에서 증착하는 것을 특징으로 한다.The present invention for achieving the above object, in the method of manufacturing a semiconductor device, the polysilicon thin film temperature range of 550 ~ 500 ℃ to ensure the reproducibility of the measurement mark when the measurement mark is formed by the deposited polysilicon thin film It is characterized in that the deposition on.
그리고, 상기 폴리실리콘 박막을 증착한 후, 상기 폴리실리콘 박막에 대해 아르곤 스퍼터링 또는 에치백을 실시하는 것을 특징으로 한다.After the polysilicon thin film is deposited, argon sputtering or etch back may be performed on the polysilicon thin film.
본 발명은 다음과 같은 기술적 원리를 갖는다. 플러그용 폴리실리콘 박막을 585℃에서 5000Å으로 증착하고, 3000Å가지 에치백하는 경우에는 폴리실리콘 결정립의 형성으로 인해 중첩측정장비의 측정 재현성이 떨어져 층간 중첩도의 제어가 정확히 이루어지지 못한다. 또한 정렬키의 불량도 심각하다. 따라서, 본 발명은 증착속도는 작지만 550℃ 이하에서 폴리실리콘 박막을 증착하여 폴리실리콘의 결정화가 적게하고 패턴의 계면이 명확히 정의될 수 있도록 한다. 그에 따라 재현성 있는 중첩도 측정 데이터 얻을 수 있고, 양호한 정렬키를 만들 수 있다. 그리고, 폴리실리콘 박막의 증착속도를 고려하여 폴리실리콘 증착 및 에치백 타겟을 작게 가져간다면 공정지연을 방지할 수 있다.The present invention has the following technical principle. When the polysilicon thin film for plug is deposited at 5000 at 585 ° C. and etched back at 3000Å, the formation of polysilicon grains reduces the measurement reproducibility of the superposition measuring equipment, thereby preventing the precise control of the interlayer overlap. There is also a serious misalignment. Therefore, the present invention allows the polysilicon thin film to be deposited at a temperature of 550 ° C. or less, although the deposition rate is small, so that the crystallinity of the polysilicon is low and the interface of the pattern can be clearly defined. Thus, reproducible overlapping measurement data can be obtained and a good alignment key can be made. In addition, in consideration of the deposition rate of the polysilicon thin film, if the polysilicon deposition and the etch back target are reduced, process delay may be prevented.
이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부된 도면을 참조하여 설명하기로 한다.DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.
먼저, 도4에는 플러그용 폴리실리콘막이 증착되어 외부박스(A)가 생성되고, 마스크 공정시 포토레지스트패턴을 형성하여 내부박스(B)가 형성된 상태가 도시되어 있다. 이때 외부박스를 만드는 폴리실리콘막은 결정립(grain)이 생성되지 않도록 500∼550℃에서 증착을 실시하며 그 경우에 증착속도가 감소하여 공정속도가 떨어지므로 폴리실리콘의 증착두께는 1000∼2000Å으로 감소시킨다. 폴리실리콘의 증착 후에는 상기 폴리실리콘 박막에 대해 에치백 대신에 아르곤 스퍼터링(Ar sputtering)을 실시하여 중첩마크의 계면을 명확하게 정의하고 폴리실리콘 찌꺼기를 원활하게 제거한다.First, FIG. 4 illustrates a state in which a plug polysilicon layer is deposited to generate an outer box A, and a photoresist pattern is formed during a mask process to form an inner box B. Referring to FIG. In this case, the polysilicon film making the outer box is deposited at 500 to 550 ° C. so as not to produce grains. In this case, the deposition speed is reduced and the process speed is decreased. Therefore, the thickness of polysilicon is reduced to 1000 to 2000Å. . After deposition of polysilicon, ar sputtering is performed on the polysilicon thin film instead of etchback to clearly define the interface of the overlap marks and to smoothly remove polysilicon residues.
도5에는 585℃에서 5000Å증착하고 3000Å을 에치백하는 종래기술과, 530℃에서 2000Å증착하고 아르곤 스퍼터링 하는 본 발명의 재현성을 비교하기 위한 실험 결과치를 나타내었다.FIG. 5 shows experimental results for comparing the reproducibility of the prior art of 5000 Å evaporation at 585 ° C. and etch back 3000 Å and 2000 Å evaporation at 530 ° C. and argon sputtering.
본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.
본 발명은 측정마크 상에 다결정 실리콘의 증착 온도를 낮춤으로써 실리콘의 결정화를 억제해서 층간 중첩도(overlay) 측정시의 재현성을 확보할 수 있고, 정렬키의 모양을 정확히 정의할 수 있다. 이는 리소그라피(lithography) 공정의 안정화를 가져와 공정속도, 생산성 및 수율 향상에 기여할 수 있다.The present invention can reduce the crystallization of silicon by lowering the deposition temperature of polycrystalline silicon on the measurement mark to ensure reproducibility in overlay measurement, and to accurately define the shape of the alignment key. This can lead to stabilization of the lithography process and contribute to process speed, productivity and yield improvement.
Claims (4)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980024688A KR20000003446A (en) | 1998-06-29 | 1998-06-29 | Poly silicon film evaporation method of a semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980024688A KR20000003446A (en) | 1998-06-29 | 1998-06-29 | Poly silicon film evaporation method of a semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR20000003446A true KR20000003446A (en) | 2000-01-15 |
Family
ID=19541215
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019980024688A KR20000003446A (en) | 1998-06-29 | 1998-06-29 | Poly silicon film evaporation method of a semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR20000003446A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100582698B1 (en) * | 2003-08-29 | 2006-05-23 | 데루아키 이토 | Test tube cap removing apparatus |
-
1998
- 1998-06-29 KR KR1019980024688A patent/KR20000003446A/en not_active Application Discontinuation
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100582698B1 (en) * | 2003-08-29 | 2006-05-23 | 데루아키 이토 | Test tube cap removing apparatus |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US20080268381A1 (en) | Pattern forming method performing multiple exposure so that total amount of exposure exceeds threshold | |
| KR100383420B1 (en) | Method of manufacturing semiconductor device | |
| KR100368569B1 (en) | Semiconductor device and its manufacturing method | |
| US5972771A (en) | Enhancing semiconductor structure surface area using HSG and etching | |
| KR20000003446A (en) | Poly silicon film evaporation method of a semiconductor device | |
| JP3200455B2 (en) | Method for manufacturing semiconductor memory device | |
| KR920007446B1 (en) | Semiconductor integrated circuit device having contact hole | |
| KR100228352B1 (en) | Process for fabricating semiconductor device | |
| KR0172553B1 (en) | Method of manufacturing semiconductor device | |
| KR100253574B1 (en) | Semiconductor element manufacturing method | |
| KR100263669B1 (en) | Method of forming alignment mark for wafer alignment | |
| KR100424177B1 (en) | Method for forming alignment mark for scanner exposure apparatus | |
| KR100187661B1 (en) | Forming method of monitoring bar for semiconductor chip area | |
| KR100436773B1 (en) | Etching method of forming conductive pattern with large cd gain of semiconductor device | |
| KR100317581B1 (en) | How to Create Nested Marks Using a Frame-in-Frame Mesa Structure Mask | |
| KR100323722B1 (en) | align measurement using overlay pattern | |
| KR20000001945A (en) | D-ram cell capacitor manufacturing method | |
| KR100252887B1 (en) | Method for fabricating semiconductor device | |
| KR930012118B1 (en) | Method of fabricating a semicondcutor device | |
| KR100402935B1 (en) | Method for manufacturing semiconductor device | |
| KR100881813B1 (en) | A method for forming a overlay vernier of a semiconductor device | |
| KR20010004583A (en) | method of forming alignment key for semiconductor device | |
| KR100328696B1 (en) | Method for manufacturing semiconductor device | |
| KR100356474B1 (en) | Method of forming overlay vernier in semiconductor device | |
| KR100331285B1 (en) | Method for forming contact hole of a semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| WITN | Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid |