KR100253574B1 - Semiconductor element manufacturing method - Google Patents

Semiconductor element manufacturing method Download PDF

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KR100253574B1
KR100253574B1 KR1019970075703A KR19970075703A KR100253574B1 KR 100253574 B1 KR100253574 B1 KR 100253574B1 KR 1019970075703 A KR1019970075703 A KR 1019970075703A KR 19970075703 A KR19970075703 A KR 19970075703A KR 100253574 B1 KR100253574 B1 KR 100253574B1
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insulating
film
mask
pattern
insulating film
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KR1019970075703A
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KR19990055748A (en
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김대영
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김영환
현대전자산업주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823468—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/482—Bit lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/488—Word lines

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE: A method for manufacturing a semiconductor device is to prevent a contact between a word line and a neighboring conductive layer and a formation of polymer generated on exposure of an insulating spacer, thereby improving yields and reliability of the device. CONSTITUTION: An isolation insulating layer is formed on a semiconductor substrate(30). A mask insulating layer pattern overlapping the first conductive layer pattern is formed on the semiconductor substrate. An insulating spacer consisting of the first and second insulating layers is formed on a sidewall of the mask insulating layer pattern and the first conductive layer pattern. The second conductive layer and an anti-reflection coating are successively formed on the entire structure. A photoresist pattern is formed on a portion of a cell region which is in contact with the substrate and is predetermined to be a bit line. The bit line is formed by etching the substrate using the photoresist pattern as a mask. The second insulating layer is exposed by an etching using an etching mask.

Description

반도체 소자의 제조방법Manufacturing method of semiconductor device

본 발명은 반도체 소자의 제조방법에 관한 것으로, 특히 셀영역에서 워드라인과 인접 도전층과의 접촉을 방지하고, 주변회로영역에서 절연스페이서 노출시 발생하는 폴리머 생성을 방지함으로서 소자의 생산 수율 및 신뢰성을 향상시키는 기술에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and in particular, to prevent contact between a word line and an adjacent conductive layer in a cell region, and to prevent polymer formation occurring when an insulating spacer is exposed in a peripheral circuit region, thereby producing yield and reliability of the device. It is about a technique to improve.

고집적 반도체 메모리 소자에서 예를들어 256 MDRAM 급 이상에서 비트라인을 반도체기판의 확산영역으로 콘택하는데 사용되는 콘택홀의 크기는 0.1-0.2μm 정도이며, 콘택홀의 에스펙트비(종횡비)는 2-3으로 매우 미세하다.In the highly integrated semiconductor memory device, for example, the contact hole used for contacting the bit line to the diffusion region of the semiconductor substrate in the 256 MDRAM class or more is about 0.1-0.2 μm, and the aspect ratio (aspect ratio) of the contact hole is 2-3. Very fine

그런데, 미세한 콘택홀을 갖는 곳에서 비트라인을 형성하기 위한 방법으로 종래에는 화학기상증착법(chemical vapor deposition 이하, CVD)으로 텅스텐 실리사이드막을 증착하고, 패턴닝 공정으로 상기 텅스텐 실리사이드막의 일정부분을 식각하여 비트라인 패턴을 형성하였다.However, as a method for forming a bit line in a place having a fine contact hole, a conventional tungsten silicide film is deposited by chemical vapor deposition (CVD), and a portion of the tungsten silicide film is etched by a patterning process. A bit line pattern was formed.

상기와같이 비트라인을 형성하는 경우 상기 텅스텐 실리사이드막이 고온의 열공정시 실리콘 산화물층과 열 안정성이 나쁘다.When the bit line is formed as described above, the tungsten silicide film has poor thermal stability with the silicon oxide layer during the high temperature thermal process.

이러한 문제점을 다소 보완하기 위하여 콘택홀을 형성한다음, 일차적으로 얇은 두께의 폴리실리콘층을 증착하고, 그 상부에 텅스텐 실리사이드막을 증착하는 하는 방법이 대두 되었다.In order to partially compensate for this problem, a method of forming a contact hole, first depositing a polysilicon layer having a thin thickness, and then depositing a tungsten silicide layer on top thereof has emerged.

그러나, 상기와 같이 폴리실리콘층과 텅스텐 실리사이드막을 적층하기 위해서는 두개의 증착 장비를 이용해야 함으로 공정시간이 길어지고 생산성이 저하되는 문제가 야기된다.However, in order to stack the polysilicon layer and the tungsten silicide layer as described above, two deposition apparatuses must be used, thereby causing a problem of lengthening process time and lowering productivity.

도 1a 내지 도 1d 는 종래 기술에 따른 반도체 소자의 제조공정도이다.1A to 1D are manufacturing process diagrams of a semiconductor device according to the prior art.

먼저, 반도체 기판(10)에 소자분리를 위한 소자분리 절연막(12), 게이트산화막(도시 안됨), 폴리실리콘막패턴으로된 워드라인(또는 게이트전극 14), 마스크절연막(16)을 순차적으로 형성한 다음, 전표면에 산화막 재질의 스페이서용 절연막(18)을 형성한다.First, a device isolation insulating film 12, a gate oxide film (not shown), a word line (or gate electrode 14) made of a polysilicon film pattern, and a mask insulating film 16 are sequentially formed on the semiconductor substrate 10. Then, an insulating film for spacers 18 made of oxide film is formed on the entire surface.

이 때, 상기 반도체 기판(10)은 셀영역(A)과 주변회로영역(B)으로 나누어진다.(도 1a 참조)At this time, the semiconductor substrate 10 is divided into a cell region A and a peripheral circuit region B (see FIG. 1A).

다음, 셀영역(A)에서 상기 스페이서용 절연막(18)을 식각하여 워드라인(14) 측벽에 절연 스페이서(20)을 형성한다.Next, the spacer insulating layer 18 is etched in the cell region A to form an insulating spacer 20 on the sidewall of the word line 14.

그 다음, 상기 구조의 전표면에 폴리실리콘막(22)과 Ti/TiN막 구조로된 반사방지막(24)을 순차적으로 형성한다.Next, the polysilicon film 22 and the anti-reflection film 24 having a Ti / TiN film structure are sequentially formed on the entire surface of the structure.

다음, 셀영역(A)에서 상기 워드라인(14)간의 사이에 반도체 기판(10)과 접촉되어 콘택플러그를 형성하기 위해 감광막패턴(26)을 형성한다. (도 1b 참조)Next, the photoresist pattern 26 is formed in contact with the semiconductor substrate 10 between the word lines 14 in the cell region A to form a contact plug. (See FIG. 1B)

그 다음, 상기 감광막패턴(26)을 식각마스크로 상기 마스크절연막(16)이 노출될때 까지 식각하여 상기 반도체 기판(10)과 접촉되는 폴리실리콘막(22)패턴과 반사방지막(24)패턴을 구비하는 비트라인(28)을 형성한다.Next, the photoresist layer pattern 26 is etched using an etch mask until the mask insulating layer 16 is exposed, and the polysilicon layer 22 pattern and the anti-reflection layer 24 pattern are in contact with the semiconductor substrate 10. The bit line 28 is formed.

이 때, 주변회로영역(B)에서는 상기 스페이서용 절연막(18)이 노출되게 된다.(도 1c 참조)At this time, the spacer insulating film 18 is exposed in the peripheral circuit region B (see FIG. 1C).

다음, 셀영역(A)을 제외한 주변회로영역(B)에서 NMOS지역만 열리는 마스크를 적용하여 상기 스페이서용 절연막(18)을 식각하여 상기 워드라인(14) 측벽에 절연 스페이서(20)을 형성하고 후속공정의 소오스/드레인 확산영역 형성을 위한 임플란트공정을 실시한다.(도 1d 참조)Next, an insulating spacer 20 is formed on the sidewall of the word line 14 by etching the spacer insulating layer 18 by applying a mask in which only the NMOS region is opened in the peripheral circuit region B except the cell region A. An implant process is performed to form a source / drain diffusion region in a subsequent process (see FIG. 1D).

상기와 같은 종래 기술에 따르면, 셀영역에서 워드라인 귀퉁이 윗부분이 워드라인 스페이서가 얇기 때문에 인접 도전체인 폴리실리콘막과의 접촉되는 문제점이 발생하며, 주변회로영역에서 폴리실리콘막을 제거시 밑에 있는 스페이서용 산화막이 손상을 입어 남은 두께를 제어할 수 없으며, NMOS와 PMOS의 주변회로영역에서 마스크를 사용하여 식각함으로서 폴리머(polymer)가 발생하여 후속공정인 이온주입시 방지막으로 작용할 수 없는 문제점이 발생한다.According to the prior art as described above, since the word line spacer is thin at the top of the corner of the word line in the cell region, a problem arises in that the contact with the polysilicon layer, which is an adjacent conductor, occurs. The oxide film is damaged and the remaining thickness cannot be controlled, and a mask is used in the peripheral circuit areas of the NMOS and the PMOS to etch the polymer to generate a polymer, which may not act as a preventive film during ion implantation.

이에, 본 발명은 상기한 문제점을 해결하기 위한 것으로 셀영역의 워드라인과 중첩되어 있는 마스크절연막 측벽에 2중 구조의 절연 스페이서를 형성한 다음, 반도체 기판과 접촉되어 비트라인으로 예정된 부위에 폴리실리콘막패턴과 반사방지막패턴으로된 비트라인을 형성하며, 주변회로영역의 워드라인과 중첩되어 있는 마스크절연막 측벽에 형성된 절연 스페이서를 감싸는 절연막을 형성함으로서 셀영역에서 워드라인과 인접 도전층과의 접촉을 확실하게 방지할 수 있으며, 주변회로영역에서의 절연 스페이서 노출시 발생하는 폴리머 생성을 방지할 수 있어 공정을 단순화하며, 소자의 생산 수율 및 신뢰성을 향상시키는 반도체 소자의 제조방법을 제공하는데 그 목적이 있다.Accordingly, the present invention is to solve the above-described problem, and to form a double-layered insulating spacer on the sidewall of the mask insulating film overlapping the word line of the cell region, and then in contact with the semiconductor substrate polysilicon in a predetermined region as a bit line A bit line formed of a film pattern and an anti-reflection film pattern is formed, and an insulating film surrounding the insulating spacer formed on the sidewall of the mask insulating film overlapping the word line of the peripheral circuit region is formed to form contact between the word line and the adjacent conductive layer in the cell region. It is possible to reliably prevent and to prevent the formation of polymers generated when the insulating spacers are exposed in the peripheral circuit area, to simplify the process, and to provide a method for manufacturing a semiconductor device that improves the production yield and reliability of the device. have.

도 1a 내지 도 1d 는 종래 기술에 따른 반도체 소자의 제조공정도1a to 1d is a manufacturing process diagram of a semiconductor device according to the prior art

도 2a 내지 도 2d 는 본 발명에 따른 반도체 소자의 제조공정도2a to 2d is a manufacturing process diagram of a semiconductor device according to the present invention

＜도면의 주요 부분에 대한 부호의 설명＞<Description of the code | symbol about the principal part of drawing>

10, 30 : 반도체 기판 12, 32 : 소자분리 절연막10, 30: semiconductor substrate 12, 32: device isolation insulating film

14, 34 : 워드라인 16, 36 : 마스크절연막14, 34: word line 16, 36: mask insulating film

18, 38 : 스페이서용 제 1절연막 20, 40 : 제 1절연 스페이서18, 38: first insulating film for spacer 20, 40: first insulating spacer

22, 46 : 폴리실리콘막 24, 48 : 반사방지막22, 46 polysilicon film 24, 48: antireflection film

26, 50 : 감광막패턴 28, 52 : 비트라인26, 50: photoresist pattern 28, 52: bit line

42 : 스페이서용 제 2절연막 44 : 제 2절연 스페이서42: second insulating film for spacer 44: second insulating spacer

상기 목적을 달성하기 위해 본 발명에 따르면,According to the present invention to achieve the above object,

반도체 기판에 소자분리 절연막을 형성하는 공정과,Forming a device isolation insulating film on the semiconductor substrate;

상기 반도체 기판 상부에 제 1도전층패턴과 중첩되어 있는 마스크절연막패턴을 형성하는 공정과,Forming a mask insulating film pattern overlying the first conductive layer pattern on the semiconductor substrate;

상기 제 1도전층패턴 및 마스크절연막패턴 측벽에 제 1절연막과 제 2절연막의 2중구조된 절연 스페이서를 형성하는 공정과,Forming a double structured insulating spacer of a first insulating film and a second insulating film on sidewalls of the first conductive layer pattern and the mask insulating film pattern;

상기 구조의 전표면에 제 2도전층과 반사방지막을 순차적으로 형성하는 공정과,Sequentially forming a second conductive layer and an anti-reflection film on the entire surface of the structure;

셀영역에서 상기 반도체 기판과 접촉되어 비트라인으로 예정된 부위에 감광막패턴을 형성하는 공정과,Forming a photoresist pattern on a predetermined portion of the cell region by contacting the semiconductor substrate in a cell region;

셀영역에서 상기 감광막패턴을 마스크로 상기 마스크절연막이 노출될때 까지 식각하여 도전층패턴과 반사방지막패턴으로된 비트라인을 형성하고, 주변회로영역에서 식각마스크를 이용하여 상기 제 2절연막의 전표면이 노출될때 까지 식각하는 공정을 포함하는 것을 특징으로 한다.In the cell region, the photoresist pattern is etched using the mask until the mask insulating layer is exposed, thereby forming a bit line including a conductive layer pattern and an anti-reflection layer pattern, and the entire surface of the second insulating layer is formed by using an etching mask in the peripheral circuit region. And etching until exposed.

이하, 첨부된 도면을 참조하여 본 발명에 따른 반도체 소자의 제조방법에 대하여 상세히 설명을 하기로 한다.Hereinafter, a method of manufacturing a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.

도 2a 내지 도 2d 는 본 발명에 따른 반도체 소자의 제조공정도이다.2A to 2D are manufacturing process diagrams of a semiconductor device according to the present invention.

먼저, 반도체 기판(30)에 소자분리를 위한 소자분리 절연막(32)과, 게이트산화막(도시 안됨), 폴리실리콘막패턴으로된 워드라인(또는 게이트전극 34), 산화막으로 이루어진 마스크절연막(36)패턴을 순차적으로 형성한 다음, 전표면에 스페이서용 제 1절연막(38)을 형성한다.First, a device isolation insulating film 32 for device isolation on a semiconductor substrate 30, a gate oxide film (not shown), a word line (or gate electrode 34) made of a polysilicon film pattern, and a mask insulating film 36 made of an oxide film. After the patterns are sequentially formed, the first insulating layer 38 for spacers is formed on the entire surface.

여기서, 상기 제 1절연막(38)은 실리콘산화막 또는 실리콘질화막으로 형성되며, 상기 반도체 기판(30)은 셀영역(A)과 주변회로영역(B)으로 나누어진다.(도 2a 참조)Here, the first insulating film 38 is formed of a silicon oxide film or a silicon nitride film, and the semiconductor substrate 30 is divided into a cell region A and a peripheral circuit region B (see FIG. 2A).

다음, 상기 제 1절연막(38)을 전면식각하여 셀영역(A)과 주변회로영역(B)에 상기 워드라인(34) 및 마스크절연막(36)패턴 측벽에 제 1절연 스페이서(40)을 형성한다.Next, the first insulating layer 38 is etched entirely to form first insulating spacers 40 on sidewalls of the word line 34 and mask insulating layer 36 in the cell region A and the peripheral circuit region B. do.

그 다음, 소오스/드레인 확산영역용 마스크를 이용하여 NMOS와 PMOS의 이온주입 공정을 실시한 다음, 전표면에 스페이서용 제 2절연막(42)을 형성한다.Next, an ion implantation process of NMOS and PMOS is performed using a source / drain diffusion region mask, and then a second insulating film 42 for spacers is formed on the entire surface.

이 때, 상기 제 2절연막(42)은 실리콘질화막으로 형성한다.(도 2b 참조)In this case, the second insulating film 42 is formed of a silicon nitride film (see FIG. 2B).

다음, 셀영역(A)에서 상기 제 1절연 스페이서(40) 상부에 형성되어 있는 제 2절연막(42)을 식각하여 상기 워드라인(34) 및 마스크절연막(36)패턴 측벽에 형성된 제 1절연 스페이서(40)와 중첩되는 제 2절연 스페이서(44)을 형성하여 2중구조의 제 1,2절연 스페이서(40, 44)를 형성한다.Next, in the cell region A, the second insulating layer 42 formed on the first insulating spacer 40 is etched to form first insulating spacers formed on sidewalls of the word line 34 and the mask insulating layer 36. A second insulating spacer 44 overlapping the 40 is formed to form the first and second insulating spacers 40 and 44 having a double structure.

이 때, 상기 워드라인(34) 및 마스크절연막(36)패턴 측벽에 형성된 제 1절연 스페이서(40)와 중첩되는 제 2절연 스페이서(44)을 형성함으로서 상기 워드라인(34)과 인접 도전층과의 접촉을 방지할 수 있다.In this case, a second insulating spacer 44 overlapping the first insulating spacer 40 formed on the sidewalls of the word line 34 and the mask insulating layer 36 is formed to form the word line 34 and the adjacent conductive layer. Can prevent contact.

그 다음, 상기 구조의 전표면에 비트라인용 도전층으로 폴리실리콘막(46)과 Ti/TiN막 구조로 이루어진 반사방지막(48)을 하드마스크로 순차적으로 형성한다.Then, an antireflection film 48 made of a polysilicon film 46 and a Ti / TiN film structure is sequentially formed as a hard mask on the entire surface of the structure as a bit line conductive layer.

다음, 셀영역(A)에서 상기 반도체 기판(30)과 접촉되어 도전층 비트라인으로 예정된 부위에 감광막패턴(50)을 형성한다.(도 2c 참조)Next, in the cell region A, the photosensitive film pattern 50 is formed on a portion of the cell region A, which is in contact with the semiconductor substrate 30 as a conductive layer bit line (see FIG. 2C).

그 다음, 셀영역(A)에서 상기 감광막패턴(50)을 마스크로 상기 마스크절연막(36)이 노출될때 까지 식각하여 폴리실리콘막(46)패턴과 반사방지막(48)패턴으로된 비트라인(52)을 형성하고, 주변회로영역(B)에서는 식각마스크를 이용하여 상기 제 2절연막(42)의 전표면이 노출될때 까지 식각한다.Next, the bit line 52 including the polysilicon layer 46 pattern and the anti-reflection layer 48 pattern is etched by using the photoresist layer pattern 50 as a mask in the cell region A until the mask insulating layer 36 is exposed. ), And in the peripheral circuit region B, an etch mask is used until the entire surface of the second insulating layer 42 is exposed.

이 때, 종래 기술에서 제 1절연 스페이서(40) 노출시 발생하는 폴리머 생성을 방지할 수 있다.At this time, in the prior art, it is possible to prevent the generation of a polymer generated when the first insulating spacer 40 is exposed.

다음, 후속공정으로 상기 구조의 전표면에 이온주입 공정을 실시하여 소오스/드레인 확산영역(도시 안됨)을 형성한다.(도 2d 참조)Next, an ion implantation process is performed on the entire surface of the structure in a subsequent step to form a source / drain diffusion region (not shown) (see FIG. 2D).

상기한 바와같이 본 발명에 따르면, 셀영역의 워드라인 및 마스크절연막패턴 측벽에 2중 구조의 절연 스페이서를 형성하고, 주변회로영역의 워드라인 및 마스크절연막패턴 측벽에 형성된 절연 스페이서를 감싸는 절연막이 형성됨으로서 셀영역에서의 워드라인과 인접 도전층과의 접촉을 확실하게 방지할 수 있으며, 주변회로영역에서의 절연 스페이서 노출시 폴리머 생성을 방지할 수 있어 공정을 단순화하며, 소자의 생산 수율 및 신뢰성을 향상시키는 이점이 있다.As described above, according to the present invention, an insulating spacer having a double structure is formed on the sidewalls of the word line and the mask insulating film pattern of the cell region, and an insulating film is formed surrounding the insulating spacer formed on the sidewalls of the wordline and mask insulating film pattern of the peripheral circuit region. It can reliably prevent contact between the word line and the adjacent conductive layer in the cell region, and can prevent the formation of polymer when the insulating spacer is exposed in the peripheral circuit region, which simplifies the process and improves the production yield and reliability of the device. There is an advantage to improve.

Claims (6)

반도체 기판에 소자분리 절연막을 형성하는 공정과,Forming a device isolation insulating film on the semiconductor substrate; 상기 반도체 기판 상부에 제 1도전층패턴과 중첩되어 있는 마스크절연막패턴을 형성하는 공정과,Forming a mask insulating film pattern overlying the first conductive layer pattern on the semiconductor substrate; 상기 제 1도전층패턴 및 마스크절연막패턴 측벽에 제 1절연막과 제 2절연막의 2중구조된 절연 스페이서를 형성하는 공정과,Forming a double structured insulating spacer of a first insulating film and a second insulating film on sidewalls of the first conductive layer pattern and the mask insulating film pattern; 상기 구조의 전표면에 제 2도전층과 반사방지막을 순차적으로 형성하는 공정과,Sequentially forming a second conductive layer and an anti-reflection film on the entire surface of the structure; 셀영역에서 상기 반도체 기판과 접촉되어 비트라인으로 예정된 부위에 감광막패턴을 형성하는 공정과,Forming a photoresist pattern on a predetermined portion of the cell region by contacting the semiconductor substrate in a cell region; 셀영역에서 상기 감광막패턴을 마스크로 상기 마스크절연막이 노출될때 까지 식각하여 도전층패턴과 반사방지막패턴으로된 비트라인을 형성하고, 주변회로영역에서 식각마스크를 이용하여 상기 제 2절연막의 전표면이 노출될때 까지 식각하는 공정을 포함하는 것을 특징으로 하는 반도체 소자의 제조방법.In the cell region, the photoresist pattern is etched using the mask until the mask insulating layer is exposed, thereby forming a bit line including a conductive layer pattern and an anti-reflection layer pattern, and the entire surface of the second insulating layer is formed by using an etching mask in the peripheral circuit region. A method of manufacturing a semiconductor device comprising the step of etching until exposure. 제 1 항에 있어서, 상기 제 1도전층은 워드라인용으로 폴리실리콘막으로 형성되며, 제 2도전층은 비트라인용으로 폴리실리콘막으로 형성된 것을 특징으로 하는 반도체 소자의 제조방법.The method of claim 1, wherein the first conductive layer is formed of a polysilicon film for a word line, and the second conductive layer is formed of a polysilicon film for a bit line. 제 1 항에 있어서, 상기 제 1절연막은 실리콘산화막 또는 실리콘질화막으로 이루어진 것을 특징으로 하는 반도체 소자의 제조방법.The method of claim 1, wherein the first insulating layer is formed of a silicon oxide film or a silicon nitride film. 제 1 항에 있어서, 상기 제 2절연막은 실리콘질화막으로 이루어지는 것을 특징으로 하는 반도체 소자의 제조방법.The method of manufacturing a semiconductor device according to claim 1, wherein the second insulating film is made of a silicon nitride film. 제 1 항에 있어서, 상기 제 2절연막 형성전에 이온주입 공정을 추가로 실시하는 것을 특징으로 하는 반도체 소자의 제조방법.The method of manufacturing a semiconductor device according to claim 1, further comprising an ion implantation step before forming the second insulating film. 제 1 항에 있어서, 상기 제 1절연막과 제 2절연막의 2중구조된 절연 스페이서는 셀영역에 형성되는 것을 특징으로 하는 반도체 소자의 제조방법.2. The method of claim 1, wherein the double structured insulating spacers of the first insulating film and the second insulating film are formed in a cell region.
KR1019970075703A 1997-12-27 1997-12-27 Semiconductor element manufacturing method KR100253574B1 (en)

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