KR20000001619A - Capacitor having a lower electrode of a winding container shape and method of forming the same - Google Patents

Abstract

PURPOSE: A capacitor of a semiconductor device and a method of forming the capacitor are provided to maximize a surface area of a lower electrode. CONSTITUTION: The method of forming a capacitor comprises the steps of: forming a contact plug(20) for connecting a semiconductor substrate and a lower electrode in an interlayer insulating layer(18) on the semiconductor substrate(10); depositing at least tow material layers(30, 33, 36) of different etch characteristic from each other above the semiconductor substrate(10) to pattern the deposited material layers; etching the result by use of etch solutions or gases having different etch rate to form the prominence and depression at a profile of the deposited material layers; forming a lower electrode layer(40) on the result; removing the lower electrode layer(40) formed on the top of an uppermost one of the material layers; forming a dielectric layer(50) on the result; and forming an upper electrode(60) on the entire surface of the result, whereby the prominence and depression has a 'da shape.

Description

Capacitor of semiconductor device having bent container shape lower electrode and manufacturing method thereof

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a capacitor of a semiconductor device and a method of manufacturing the same, and more particularly, to a capacitor having a new structure having a wider surface area of a lower electrode thereof, and a method of manufacturing the same.

In semiconductor devices, in particular memory devices, capacitors are used as means for storing data. The stored data should be kept unaltered and should be able to prevent the stored data from being corrupted by external influences (e.g. soft errors caused by alpha (α) particles). On the other hand, with the higher integration of semiconductor devices, the area in which semiconductor devices such as transistors and capacitors can be formed is getting narrower.

Therefore, various methods have been sought to have a capacitance such that data storage and maintenance functions can be normally performed even under external influences in a narrow area. One of the methods has been researched to expand the surface area as much as possible by making the shape of the lower electrode three-dimensional, such as a stack, cylinder, or fin. However, the method of stereoscopic lower electrode has a problem that the manufacturing process is relatively difficult as the semiconductor device is more integrated.

On the other hand, a method of using a ferroelectric having a high dielectric constant is being studied as another method of increasing capacitance. Such ferroelectrics include BST ((Ba, Sr) TiO ₃ ) and PZT (PbZrTiO ₃ ). These dielectrics may be silicon oxide (SiO ₂ ), silicon nitride (Si ₃ N ₄ ), or a combination of NO (Si ₃ N ₄ / SiO ₂ ) or ONO (SiO ₂ / Si ₃ N). _The dielectric constant is more than several hundred times that of the ₄ / SiO ₂ ) film. In order to use the ferroelectric as a dielectric film of a capacitor, a heat-resistant metal that can be well matched with the ferroelectric is used as an electrode of the capacitor. Representative heat-resistant metals that can be best matched with a ferroelectric are platinum (Pt) and ruthenium (Ru). Platinum group metals and their oxides are widely used. Platinum group metals and oxides thereof are not only excellent in oxidation resistance in a high temperature oxygen atmosphere, but also advantageous for growth of ferroelectric films.

However, since a heat resistant metal such as a platinum group metal is difficult to etch, a method of forming a lower electrode without etching is being studied. In such a method of forming a lower electrode of the platinum group metal without etching, a method of forming an insulating layer pattern on which a portion of the lower electrode is to be formed is formed, and then a platinum group metal, which is a lower electrode material, is deposited, and a portion of the lower electrode is to be formed. The lower electrode is formed by removing the platinum group metal formed at the other portion by a method such as chemical mechanical polishing.

However, according to the method of forming the lower electrode without etching, it was not possible to form a lower electrode of a complicated structure such as a pin shape that can maximize the surface area, and to form a simple stacked lower electrode. However, as semiconductor devices become more integrated, as the area where capacitors are formed becomes smaller, the height of the lower electrode needs to be increased to obtain the desired capacitance, which increases the level difference between the memory cell region and the peripheral circuit region, thereby increasing the difficulty of subsequent processes. Increases. Therefore, the lower electrode of the ferroelectric capacitor is also required to increase its surface area as much as possible without increasing the height.

An object of the present invention is to provide a capacitor of a semiconductor device having a lower electrode having a new structure in which the surface area of the lower electrode is maximized.

Another object of the present invention is to provide a method of manufacturing a capacitor of a semiconductor device having the lower electrode of the new structure.

1A to 1F are cross-sectional views illustrating a method of manufacturing a capacitor according to a first embodiment of the present invention.

2 shows a cross section of a capacitor according to a second embodiment of the present invention.

3A and 3B show a cross section of a capacitor according to a third embodiment of the present invention.

4A and 4B show a cross section of a capacitor according to a fourth embodiment of the present invention.

The capacitor of the semiconductor device according to the present invention for achieving the above technical problem, in the capacitor of the semiconductor device comprising a lower electrode, a dielectric film and the upper electrode, the profile of the lower electrode is at least one 'c' shaped on both side walls thereof. It has an uneven part, It is characterized by the hollow cylindrical shape (Hereinafter, this is called a folded container shape.).

A dielectric film is deposited on the inner surface and the inner bottom surface of the curved container-shaped lower electrode. In addition, the outer surface of the lower electrode may be in contact with the insulating film, or the entire surface of the outer surface or a portion of a predetermined height or more may be exposed to deposit a dielectric film to further increase the surface area of the lower electrode.

Here, the dielectric layer may be formed of Ta ₂ O ₅ , SrTiO ₃ , (Ba, Sr) TiO ₃ , PbZrTiO ₃ , SrBi ₂ Ta ₂ O ₉ , (Pb, La) (Zr, Ti) O ₃ or Bi ₄ Ti ₃ O ₁₂ The upper and lower electrodes may be formed of a platinum group metal, an oxide of a platinum group metal, or a metal nitride.

According to another aspect of the present invention, there is provided a method of manufacturing a capacitor of a semiconductor device, including forming a contact plug for connecting a semiconductor substrate and a lower electrode to an interlayer insulating layer, and then forming material layers having different etching characteristics thereon. Laminate at least two layers and pattern the stacked material layers to expose the contact plug. Subsequently, the material layers are etched with an etching solution or an etching gas having different etching rates of the material layers, thereby forming irregularities in the profile of the stacked material layers. The lower electrode film is formed on the surface of the resultant material so far, and adjacent lower electrodes are separated by removing the lower electrode film formed on the uppermost layer of the material layers. Subsequently, a dielectric film is formed on the resultant surface and an upper electrode is formed thereon, thereby completing a capacitor having the lower electrode of the curved container shape.

Here, the process of forming the lower electrode film is preferably performed by chemical vapor deposition, and the removal of the lower electrode film formed on the uppermost layer of the material layers is preferably performed by chemical mechanical polishing. .

As described above, the present invention can be applied to a ferroelectric capacitor having a lower electrode made of a platinum group metal or an oxide thereof, which is difficult to etch, by making the lower electrode into a curved container shape without an etching process, thereby further increasing capacitance.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

Figure 1f is a cross-sectional view showing a capacitor having a lower electrode of the curved container shape according to the first embodiment of the present invention. As shown, the capacitor according to the first embodiment of the present invention is formed on the semiconductor substrate 10 on which the transistors are formed, the contact plugs 20 for lower electrodes, and the material layers 30 and 34 having a 'c'-shaped unevenness. 36) the lower electrode 42 separated from other adjacent lower electrodes and having a 'c' shaped cylindrical shape, and the dielectric film 50 and the dielectric film deposited to have the 'c' shaped unevenness on the lower electrode 42 surface, respectively. And an upper electrode 60 deposited on 50.

Here, the dielectric film 50 may include Ta ₂ O ₅ , SrTiO ₃ , (Ba, Sr) TiO ₃ , PbZrTiO ₃ , SrBi ₂ Ta ₂ O ₉ , (Pb, La) (Zr, Ti) O ₃ or Bi ₄ Ti ₃ The ferroelectric capacitor can be formed by forming a high dielectric material such as O ₁₂ .

In addition, the material of the lower electrode 42 or the upper electrode 60 may be a platinum group metal such as platinum (Pt), ruthenium (Ru), or iridium (Ir) or RuO ₂ , IrO, which is well matched with a high dielectric material such as BST or PZT. A metal nitride such as an oxide of a platinum group metal such as ₂ or the like or TiN which is well suited to a dielectric film of Ta ₂ O ₅ may be used.

In addition, although the lower electrode 42 having one 'c' shaped uneven portion is shown in FIG. 1f, the 'c' shaped uneven portion may be two or more. That is, instead of stacking the material layers 30, 34, and 36 in three layers as shown in FIG. 1F, the layers having the same structure as the first and second layers 30 and 34 are repeated on the third layer 36. Multiple uneven parts can be formed by laminating | stacking.

2 is a cross-sectional view showing a capacitor having a lower electrode of a curved container shape according to a second embodiment of the present invention. The lower electrode 44 of the second embodiment has a cylindrical shape having a 'c'-shaped uneven portion, like the lower electrode 42 of the first embodiment, but as shown in FIG. The difference is that the electrode area is wider than that of the lower electrode of the first embodiment by using it as an effective surface of the lower electrode.

In the second embodiment, like the first embodiment, the dielectric film 52 can be formed of a high dielectric material, and the upper and lower electrodes can be formed of a platinum group metal, an oxide thereof, or a metal nitride. In addition, the lower electrode 44 may have two or more 'c' shaped uneven parts.

In addition, in FIG. 2, the dielectric layer is formed on the lower electrode of the portion of the material layers that contact the second and third layers 34 and 36 in FIG. 1F, leaving the first layer 30. ) May be removed to form a dielectric film only at a portion in contact with the third layer 36, or conversely, by removing the first layer 30 to form a dielectric film on the entire outer surface of the lower electrode 44, the electrode area is further increased. It can also be widened.

3A and 3B are cross-sectional views illustrating a capacitor having a lower electrode having a curved container shape according to a third embodiment of the present invention. 3A and 3B show a barrier layer 22 between the bottom electrode contact plugs 20 and the bottom electrodes 42 and 44 of the capacitors of the first and second embodiments of the present invention shown in FIGS. 1F and 2, respectively. It shows a representative of the structure further formed. The barrier layer 22 generally serves to prevent the contact plug 20 made of polycrystalline silicon, high melting point metal or metal silicide and the lower electrodes 42 and 44 from diffusing or reacting with each other during the formation process. As the material of the barrier layer 22, Ti, TiN, TiSi _x , TiSiN, TaSiN, TaAlN, Ir, Ru, W, WSi or WN may be used.

4A and 4B are cross-sectional views illustrating a capacitor having a lower electrode having a curved container shape according to a fourth embodiment of the present invention. 4A and 4B illustrate a material layer 30 for separating the lower electrode of the capacitor and the interlayer insulating layer 18 forming the under structure of the capacitor, according to the first and second embodiments of the present invention shown in FIGS. 1F and 2, respectively. In order to improve adhesion properties between the material layer 30 and the interlayer insulating film 18, the adhesive layer 24 is further formed. As the material for forming the adhesive layer 24, metal oxides such as TiO ₂ and Al ₂ O ₃ may be used.

Next, a method of manufacturing a capacitor having a lower electrode of a curved container shape according to an embodiment of the present invention will be described.

First, as shown in Figure 1a to complete the substructure of the capacitor. As shown in the figure below, the device isolation film 12 is formed on the semiconductor substrate 10, the transistor including the gate electrode 14, the bit line 16, and the like is formed, and then the interlayer insulating film 18 is formed. Is completed. Then, the contact plug for the lower electrode is formed by drilling a contact hole for electrically connecting the lower electrode and the semiconductor substrate 10 to the interlayer insulating film 18, filling the conductive material therein, and removing the conductive material remaining in the portion other than the contact portion. 20 is formed. As the conductive material, a high melting point metal such as polycrystalline silicon, a platinum group metal, a metal silicide, or the like can be used.

Subsequently, at least two or more layers of material having different etching characteristics and capable of selectively etching may be stacked. Although FIG. 1B shows a structure in which three layers of the first layer 30, the second layer 33, and the third layer 36 are stacked, the fourth layer, the fifth layer, and the like are laminated thereon again. In the shape of the lower electrode, two or more 'c' shaped irregularities may be made.

In this case, the materials of the first layer 30 to the third layer 36 may be selected by using different materials from the silicon oxide film, silicon nitride film or aluminum oxide film. In addition, two different materials may be selected and stacked alternately. Of course, the same effect can be obtained with the same material if a method capable of selective etching in the etching process is used. Although the thickness to laminate | stack depends on a desired capacitance, about 1000-3000 micrometers is suitable.

After stacking the first to third layers as described above, the stacked material layers are etched to expose a portion where the lower electrode is to be formed by performing a photolithography process, as shown in FIG. 1B.

Subsequently, any one material layer is selectively etched using the difference in etching characteristics of the stacked materials. For example, when the first layer 30 and the third layer 36 are silicon nitride films and the second layer 33 is a silicon oxide film, the second layer 33 is etched using BOE (Buffered Oxide Echant) as an etching solution. Only the oxide film is selectively etched to make it as shown in FIG. 1C. In addition, FIG. 1C illustrates a state in which the second layer 34 is selectively etched. However, if only the silicon nitride film is selectively etched using phosphoric acid (H ₃ PO ₄ ), the first layer 30 and The third layer 36 will be etched. In this case, the depth removed by selective etching may vary depending on the size of the lower electrode or the distance between other adjacent lower electrodes, but it is appropriate that the depth is about 10 to 50% of the length of the material layer that is not etched.

Next, as shown in FIG. 1D, when the lower electrode film 40 is formed on the entire surface of the resulting product, a curved container shape having a desired 'c'-shaped uneven portion is obtained. The material of the lower electrode layer 40 may be a platinum group metal such as platinum (Pt), ruthenium (Ru), iridium (Ir), or an oxide or metal nitride of a platinum group metal such as RuO ₂ or IrO ₂ . At this time, since the lower electrode film 40 should also be formed on the 'c'-shaped concave-convex portions of the first to third layers 30, 34, and 36, a chemical vapor deposition method having good step coverage is used. It is preferable to deposit. For example, when platinum (Pt) is used as a material of the lower electrode film, argon (Ar) and oxygen (O ₂ ) atmospheres using a hexafluoro acetyle acetonate (Pt-HFA), a chamber pressure of 1 to 10 Torr, and 200 to It can be deposited using chemical vapor deposition at a substrate temperature of 500 ℃.

Subsequently, adjacent lower electrodes 42 are separated by removing the lower electrode layer 40 deposited on the upper surface of the third layer 36 as illustrated in FIG. 1E. This process is preferably performed by chemical mechanical polishing or etch back to remove all the lower electrode film 40 deposited on the upper surface of the third layer 36 and to overetch the 10% of the third layer 36. Do.

Further, instead of immediately removing the lower electrode film 40 deposited on the upper surface of the third layer 36, the filling material may be filled on the entire structure of FIG. 1D, and then the filling material and the lower electrode film may be removed together. In this case, the residue of the lower electrode layer which is uniformly removed and is removed does not remain more than when the lower electrode layer is immediately removed without using the filling material. Suitable materials for filling include SOG (Spin On Glass), BPSG (Boron Phosphorus Silicate Glass) or USG (Undoped Silicate Glass).

When the dielectric film 50 is deposited on the surface of the lower electrode 42 and the exposed third layer 36, and the upper electrode 60 is deposited thereon, the first embodiment of the present invention as shown in FIG. 1F. A capacitor having a curved container-shaped lower electrode is completed.

Here, as a material of the dielectric film 50, Ta ₂ O ₅ , SrTiO ₃ , (Ba, Sr) TiO ₃ , PbZrTiO ₃ , SrBi ₂ Ta ₂ O ₉ , (Pb, La) (Zr, Ti) O ₃ or Bi ₄ A high dielectric material such as Ti ₃ O ₁₂ may be used, and like the lower electrode 42, in order to form a 'c'-shaped uneven portion, it is preferable to deposit using a chemical vapor deposition method having good step coverage. For example, when BST is used as a dielectric, an organic source based on Ba (tetra methyl heptane dionhe) ₂ , Sr (TMHD) ₂ , Ti (TMHD) ₂ , and O ₂ and N ₂ O are oxidized gases. It is used as, and the BST of 100 to 500Åm thickness is deposited by chemical vapor deposition under the conditions of substrate temperature 400 to 600 ℃, chamber pressure 1 to 10 Torr.

Like the lower electrode 42, the upper electrode 60 may be formed by using a platinum group metal such as platinum (Pt), ruthenium (Ru), or iridium (Ir), or an oxide or metal nitride of a platinum group metal such as RuO ₂ or IrO ₂ . It can be formed by a vapor deposition method, and the deposition thickness is about 100 to 3000 Pa. After the upper electrode is formed, a heat treatment may be added for 30 minutes at a temperature of 500 to 800 ° C. in a nitrogen atmosphere containing 1 to 10% of oxygen to improve the interfacial properties between the high dielectric film and the upper and lower electrodes. .

Next, a method of manufacturing a capacitor having a lower electrode having a curved container shape according to the second embodiment of the present invention shown in FIG. 2 will be described.

First, in the method of manufacturing the capacitor according to the first embodiment of the present invention described above, that is, the process illustrated in FIGS. 1A to 1E, that is, the lower structure, the contact plug 20, and the material layers 30 and 34 for separating the lower electrode. , And the lower electrode film 40 are sequentially formed, and the lower electrode film formed on the upper surface of the third layer 36 is removed to form the lower electrode 42 or 44 having a curved container shape in the same manner. .

Subsequently, some or all of the material layers 30, 34, and 36 are removed from the third layer 36 without immediately forming a dielectric film. For example, if the third layer 36 is a silicon nitride film and the second layer 34 below is a silicon oxide film, the third layer 36 is first removed using phosphoric acid (H ₂ PO ₄ ), and then The silicon oxide film serving as the second layer 34 is etched using BOE (Buffered Oxide Echant) as an etching solution to expose the outer surface of the lower electrode 44. When the dielectric film 52 and the upper electrode 62 are deposited on the exposed lower electrode 44 surface and the remaining first layer 30 in the same manner as in the manufacturing of the capacitor according to the first embodiment, the second electrode as shown in FIG. The capacitor of the embodiment is completed.

Although FIG. 2 illustrates a case in which only one material layer 30 of the three material layers 30, 34, and 36 is left, only the third layer 36 may be removed, and conversely, the first layer 30 may be removed. It is also possible to obtain a larger electrode area. Of course, the material layer may be laminated more without limiting to three layers from the beginning.

Next, a method of manufacturing a capacitor having a lower electrode having a curved container shape according to a third embodiment of the present invention shown in FIGS. 3A and 3B will be described.

First, a substructure of the capacitor as shown in FIG. 1A is formed. Subsequently, the space formed by etching the formed lower electrode contact plug 20 to a predetermined depth and the front surface of the interlayer insulating film 18, for preventing mutual diffusion and reaction between the contact plug 20 and the lower electrode to be formed later. The barrier layer material is laminated. The barrier layer material is removed by chemical mechanical polishing or etch back so that the barrier layer material remains only on the contact plug 20. Subsequently, when the capacitor manufacturing process according to the first and second embodiments described above is performed, the capacitor according to the third embodiment in which the barrier layer 22 is inserted as shown in FIGS. 3A and 3B is completed.

Here, the barrier layer material may be Ti, TiN, TiSi _x , TiSiN, TaSiN, TaAlN, Ir, Ru, W, WSi or WN.

Next, a method of manufacturing a capacitor having a lower electrode having a curved container shape according to a fourth embodiment of the present invention shown in FIGS. 4A and 4B will be described.

First, before forming the lower structure of the capacitor as shown in FIG. 1A and stacking the material layer 30 for separating the lower electrode, the material layer 30 and the interlayer insulating film 18 forming the lower structure of the capacitor are formed. An adhesive layer 24 is formed to improve the adhesion characteristics of the interlayer insulating film 18. As the material for forming the adhesive layer 24, metal oxides such as TiO ₂ and Al ₂ O ₃ may be used. Subsequently, when the capacitor manufacturing process according to the first and second embodiments described above is performed, the capacitor according to the fourth embodiment in which the adhesive layer 24 is inserted as shown in FIGS. 4A and 4B is completed.

In addition, if both the method of manufacturing the capacitors according to the third and fourth embodiments are performed, a capacitor having both the barrier layer 22 and the adhesive layer 24 may be obtained.

As described above, according to the capacitor according to the present invention, by having a hollow cylindrical lower electrode having a 'c'-shaped concave-convex portion, an increased effective electrode area can be obtained in the same area, thereby ensuring sufficient capacitance. High integration of the memory device can be achieved.

In addition, the capacitor manufacturing method according to the present invention is applicable to a ferroelectric capacitor using a platinum electrode which is difficult to etch since it does not involve an etching process of the electrode.

Claims (21)

A capacitor of a semiconductor device comprising a lower electrode, a contact plug connecting the lower electrode and a semiconductor substrate, a dielectric film deposited on a surface of the lower electrode, and an upper electrode deposited on the dielectric film. The lower electrode profile has at least one 'c' shaped concave-convex portion on both side walls, and a hollow cylindrical capacitor. The capacitor of claim 1, wherein an outer surface of both sidewalls of the lower electrode is in contact with an insulating layer, and the dielectric layer is deposited on the inner surface of both sidewalls and the inner bottom surface of the lower electrode. The semiconductor device of claim 1, wherein the dielectric film is deposited on all of the outer surfaces of both sidewalls of the lower electrode or a portion of a predetermined height or more, an inner surface of both sidewalls, and an inner bottom surface of the lower electrode. Capacitors. The capacitor of claim 1, further comprising a barrier layer between the lower electrode and the contact plug to prevent mutual diffusion and reaction between the lower electrode and the contact plug. The capacitor of claim 4, wherein the barrier layer is formed of one selected from the group consisting of Ti, TiN, TiSi _x , TiSiN, TaSiN, TaAlN, Ir, Ru, W, WSi, and WN. The dielectric layer of claim 1, wherein the dielectric layer is formed of Ta ₂ O ₅ , SrTiO ₃ , (Ba, Sr) TiO ₃ , PbZrTiO ₃ , SrBi ₂ Ta ₂ O ₉ , (Pb, La) (Zr, Ti) O _3, and Bi _4. Capacitor of a semiconductor device, characterized in that formed of any one selected from the group consisting of Ti ₃ O ₁₂ . The capacitor of claim 1, wherein the lower electrode or the upper electrode is formed of at least one selected from the group consisting of a platinum group metal, an oxide of a platinum group metal, and a metal nitride. (a) forming a contact plug on the interlayer insulating film on the semiconductor substrate for connecting the semiconductor substrate and the lower electrode; (b) stacking at least two or more layers of material having different etching characteristics on the resultant, and patterning the stacked material layers to expose a portion where the lower electrode is to be formed; (c) etching the resultant into an etchant or an etching gas having a different etching rate of the material layers to form an uneven portion in the profile of the stacked material layers; (d) forming a lower electrode film on the resultant surface; (e) removing the lower electrode layer formed on the uppermost layer of the material layers; (f) forming a dielectric film on the resultant surface; And (g) forming an upper electrode on the entire surface of the resultant. 10. The method of claim 8, further comprising removing some or all of the material layers between steps (e) and (f). 10. The method of claim 8 or 9, wherein the material layers are formed of any one selected from the group consisting of a silicon nitride film, a silicon oxide film, and an aluminum oxide film. The method of claim 10, wherein the material layers are formed by alternately stacking different first and second materials. 10. The method of claim 8 or 9, wherein the thicknesses of the material layers are 300 Å or more, respectively. The method of claim 8 or 9, wherein the step (d) is to form the lower electrode film by chemical vapor deposition, and the step (e) is formed on the top of the uppermost layer of the material layer by chemical mechanical polishing A method of manufacturing a capacitor of a semiconductor device, characterized in that the lower electrode film is removed. 15. The method of claim 13, further comprising the step of filling the filling material on the entire surface of the resultant of step (d) between step (d) and (e), wherein step (e) And removing the lower electrode layer formed on the uppermost layer of the material layers. 15. The method of claim 14, wherein the filling material is formed of one selected from a group consisting of a silicon oxide film, SOG, BPSG, and USG. The method of claim 8 or 9, wherein the dielectric film is Ta ₂ O ₅ , SrTiO ₃ , (Ba, Sr) TiO ₃ , PbZrTiO ₃ , SrBi ₂ Ta ₂ O ₉ , (Pb, La) (Zr, Ti) O ₃ and Bi ₄ Ti ₃ O _{12 A} method for manufacturing a capacitor of a semiconductor device, characterized in that formed of one selected from the crowd. 10. The method of claim 8 or 9, wherein the lower electrode or the upper electrode is formed of at least one selected from the group consisting of a platinum group metal, an oxide of a platinum group metal, and a metal nitride. 10. The method of claim 8 or 9, Between the step (a) and (b), a barrier layer for preventing the mutual diffusion and reaction between the lower electrode and the contact plug, the lower electrode and the contact plug Capacitor manufacturing method of a semiconductor device, characterized in that it further comprises forming between. 19. The method of claim 18, wherein the barrier layer is formed of any one selected from the group consisting of Ti, TiN, TiSi _x , TiSiN, TaSiN, TaAlN, Ir, Ru, W, WSi, and WN. 10. The method according to claim 8 or 9, wherein an adhesive layer is formed on the interlayer insulating film between the steps (a) and (b) to improve adhesion between the interlayer insulating film and the lowermost layer of the material layers. Capacitor manufacturing method of a semiconductor device characterized in that it further comprises. 21. The method of claim 20, wherein the adhesive layer is made of a metal oxide.