KR20000000991A - Mask frame - Google Patents
Mask frame Download PDFInfo
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- KR20000000991A KR20000000991A KR1019980020981A KR19980020981A KR20000000991A KR 20000000991 A KR20000000991 A KR 20000000991A KR 1019980020981 A KR1019980020981 A KR 1019980020981A KR 19980020981 A KR19980020981 A KR 19980020981A KR 20000000991 A KR20000000991 A KR 20000000991A
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- KR
- South Korea
- Prior art keywords
- mask frame
- alignment mark
- semiconductor device
- pattern
- alignment
- Prior art date
Links
- 238000000034 method Methods 0.000 claims abstract description 28
- 239000004065 semiconductor Substances 0.000 claims abstract description 20
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 230000000903 blocking effect Effects 0.000 claims abstract description 7
- 230000002093 peripheral effect Effects 0.000 claims description 2
- 238000004519 manufacturing process Methods 0.000 abstract description 4
- 229920002120 photoresistant polymer Polymers 0.000 abstract 1
- 238000002955 isolation Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
- G03F1/38—Masks having auxiliary features, e.g. special coatings or marks for alignment or testing; Preparation thereof
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- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
- Preparing Plates And Mask In Photomechanical Process (AREA)
Abstract
본 발명은 마스크 프레임 ( mask frame ) 에 관한 것으로, 반도체기판의 정렬마크와 정렬시켜 반도체기판 상부의 감광막을 노광 및 현상하여 패턴을 형성할 수 있도록 하는 반도체소자의 마스크 프레임에 있어서, 후속 CMP 공정시 과도한 CMP 공정으로부터 정렬마크를 보호할 수 있는 더미패턴을 형성할 수 있도록 마스크 프레임의 오픈 영역에 다수의 차광영역이 구비되는 마스크 프레임을 형성하고 이를 이용하여 반도체소자를 형성함으로써 후속 CMP 공정시 정렬마크가 손상되는 현상을 방지할 수 있어 정렬도를 향상시킬 수 있어 반도체소자의 제조공정을 용이하게 실시할 수 있는 기술이다.BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a mask frame, wherein a mask frame of a semiconductor device is formed so that a pattern is formed by exposing and developing a photoresist film on an upper surface of a semiconductor substrate in alignment with an alignment mark of a semiconductor substrate. In order to form a dummy pattern to protect the alignment mark from excessive CMP process, a mask frame including a plurality of light blocking regions is formed in the open area of the mask frame, and a semiconductor device is formed using the alignment mark during the subsequent CMP process. It is possible to prevent the phenomenon of damaging, improve the degree of alignment, it is a technology that can easily perform the manufacturing process of the semiconductor device.
Description
본 발명은 마스크 프레임에 관한 것으로, 특히 반도체소자의 소자분리공정과 같이 후속공정으로 화학기계연마 ( chemical mechanical polishing, 이하에서 CMP라 함 ) 공정을 적용하는 마스크 프레임의 오픈영역에 별도의 패턴을 형성하여 후속공정인 CMP 공정시 정렬마크 또는 패턴이 손상되는 현상을 방지하는 기술에 관한 것이다.The present invention relates to a mask frame, and in particular, to form a separate pattern in the open area of the mask frame to apply a chemical mechanical polishing (CMP) process in a subsequent process, such as the device isolation process of a semiconductor device The present invention relates to a technique for preventing a phenomenon that an alignment mark or a pattern is damaged during a subsequent CMP process.
일반적으로, 정렬마크나 중첩마크는 셀의 여유면적이나 셀과 셀 사이의 공간, 예를들면 스크라이브 라인이나 프레임 ( frame ) 등의 여유면적에 형성한다.In general, alignment marks and overlap marks are formed in the free area of a cell or the space between the cell and the free area such as a scribe line or a frame.
그리고, 상기 여유면적 상부에 정렬마크가 형성된 마스크 프레임을 이용하여 마스크를 정렬하고 노광 및 현상공정을 실시한다.Then, the mask is aligned using a mask frame having an alignment mark formed on the clearance area, and an exposure and development process is performed.
이때, 상기 프레임은 정렬마크의 정렬부분 외의 부분은 오픈시켜 형성된 것으로 이를 이용한 노광 및 현상공정시 셀부의 바깥부분을 정렬마크만이 형성된 상태로 형성한다.In this case, the frame is formed by opening the portion other than the alignment portion of the alignment mark, and forms the outer portion of the cell portion in the state where only the alignment mark is formed during the exposure and development processes using the same.
그리고, 셀의 바깥부분에 위치한 정렬마크는 주변에 별도의 패턴이 형성되어 있지 않아 후속공정인 CMP 공정시 손상되기 용이하다.In addition, the alignment mark located at the outer part of the cell is not easily formed at the periphery, and thus is easily damaged during the subsequent CMP process.
그로인하여, 후속공정 진행시 정렬이 어려워지게되어 반도체소자의 제조공정을 어렵게 하는 문제점이 있다.Therefore, there is a problem that the alignment becomes difficult during the subsequent process, making the manufacturing process of the semiconductor device difficult.
도 1 은 종래기술에 따른 마스크 프레임을 도시한 평면도이다.1 is a plan view showing a mask frame according to the prior art.
먼저, 정렬마크(103)가 구비되고, 후속 마스크 공정에서 형성될 정렬마크가 위치하는 지역(107)을 도시한다.First, an alignment mark 103 is provided and shows the area 107 where the alignment mark to be formed in a subsequent mask process is located.
그리고, "105"는 마스크 프레임의 오픈된 공간을 도시한다. (도 1)And "105" shows the open space of the mask frame. (Figure 1)
상기한 바와같이 종래기술에 따른 반도체소자의 제조방법은, 오픈된 영역에 형성된 정렬마크가 CMP 공정시 손상되어 후속공정시 정렬에 어려움을 가지며 그에 따른 중첩정확도를 저하시켜 반도체소자의 제조를 어렵게 하는 문제점이 있다.As described above, the manufacturing method of the semiconductor device according to the prior art has difficulty in the alignment mark formed in the open area is damaged during the CMP process and difficult to align in the subsequent process, thereby reducing the overlapping accuracy, making the manufacturing of the semiconductor device difficult There is a problem.
본 발명은 상기한 문제점을 해결하기위하여, 정렬마크가 구비되는 반도체소자의 여유면적에 규칙적으로 정렬마크와 같은 높이의 절연패턴을 형성할 수 있도록 형성된 마스크 프레임을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION In order to solve the above problems, an object of the present invention is to provide a mask frame formed so that an insulating pattern having the same height as an alignment mark is regularly formed in a free area of a semiconductor device having an alignment mark.
도 1 는 종래기술에 따른 마스크 프레임을 도시한 평면을 도시한 계략도.1 is a schematic view showing a plane showing a mask frame according to the prior art;
도 2 는 본 발명의 실시예에 따른 마스크 프레임을 도시한 평면을 도시한 계략도.2 is a schematic view showing a plane illustrating a mask frame according to an embodiment of the present invention;
※ 도면의 주요 부분에 대한 부호의 설명※ Explanation of codes for main parts of drawing
103,203 : 정렬마크 105 : 오픈된 공간103,203: alignment mark 105: open space
107 : 오픈되어 후속 마스크 공정에 정렬마크가 형성될 영역107: area to be opened to form an alignment mark in a subsequent mask process
205 : 오픈된 공간205: open space
207 : 차광영역207: shading area
이상의 목적을 달성하기위해 본 발명에 마스크 프레임은,In order to achieve the above object, the mask frame of the present invention,
반도체기판의 정렬마크와 정렬시켜 반도체기판 상부의 감광막을 노광 및 현상하여 패턴을 형성할 수 있도록 하는 반도체소자의 마스크 프레임에 있어서,In the mask frame of the semiconductor device to align the alignment mark of the semiconductor substrate to form a pattern by exposing and developing the photosensitive film on the semiconductor substrate,
후속 CMP 공정시 과도한 CMP 공정으로부터 정렬마크를 보호할 수 있는 더미패턴을 형성할 수 있도록 마스크 프레임의 오픈 영역에 다수의 차광영역이 구비되는 것을 특징으로한다.In the subsequent CMP process, a plurality of light shielding areas are provided in the open area of the mask frame to form a dummy pattern to protect the alignment mark from excessive CMP process.
이상의 목적을 달성하기 위한 본 발명의 원리는, 정렬마크를 이용하여 마스크를 정렬시킬 수 있는 마스크 프레임에 정렬마크가 형성되는 부분과 후속공정으로 정렬마크가 형성될 오픈 영역에 일정한 간격, 예를들면 가로, 세로 각각 100 ㎛ 정도의 크기로 오픈된 영역과 차광영역을 형성함으로써 반도체기판 상부의 정렬마크 주변에 별도의 패턴이 형성되어 후속공정인 CMP 공정시 정렬마크가 손상되는 것을 방지할 수 있도록 하는 것이다.The principle of the present invention for achieving the above object, the alignment mark is formed in the mask frame capable of aligning the mask using the alignment mark and a predetermined interval, for example in the open area where the alignment mark is to be formed in a subsequent process, for example By forming an open area and a light shielding area of about 100 μm in width and length, respectively, a separate pattern is formed around the alignment mark on the upper portion of the semiconductor substrate to prevent the alignment mark from being damaged during the subsequent CMP process. will be.
이하, 첨부된 도면을 참고로 하여 본 발명을 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 2 는 본 발명의 실시예에 따른 반도체소자의 마스크 프레임을 도시한 평면도이다.2 is a plan view illustrating a mask frame of a semiconductor device according to an embodiment of the present invention.
도 2a 를 참조하면, 마스크 프레임의 정렬마크(203) 부분을 제외한 모든 부분의 오픈 영역에 일정간격으로 차광영역을 형성하되, 이를 가로, 세로 각각 100 ㎛ 정도의 크기로 오픈영역(205)과 차광영역(207)을 형성한다.Referring to FIG. 2A, light blocking areas are formed at predetermined intervals in the open areas of all parts except the alignment mark 203 of the mask frame, and the light blocking areas are formed with the open area 205 and the light blocking with a size of about 100 μm horizontally and vertically. Area 207 is formed.
이로인하여, 상기 마스크 프레임을 이용한 노광 및 현상공정으로 반도체기판 상부에 패턴을 형성하는 경우, 정렬마크가 형성되는 부분에 별도의 패턴, 즉 더미패턴이 구비되어 후속 CMP 공정시 상기 정렬마크가 과도하게 CMP 되어 손상되지않도록 한다.Thus, when the pattern is formed on the semiconductor substrate by the exposure and development process using the mask frame, a separate pattern, that is, a dummy pattern, is provided at a portion where the alignment mark is formed, so that the alignment mark is excessively used during the subsequent CMP process. Do not damage the CMP.
이때, 상기 더미패턴은, 정렬마크 하나의 크기인 가로 세로 각각 100 ㎛ 의 크기로 형성할 수도 있으며, 가로 세로의 크기를 다르게 하여 형성할 수도 있다.In this case, the dummy pattern may be formed to have a size of 100 μm each of the length and width of one alignment mark, or may be formed by varying the size of the width and length.
그리고, 상기 차광영역, 즉 더미패턴은 사각형, 원형 또는 삼각형과 같은 도형으로 형성할 수 있으며, 셀부, 주변회로부 또는 마스크 프레임 등에 형성할 수 있다.The light blocking area, that is, the dummy pattern may be formed in a shape such as a rectangle, a circle, or a triangle, and may be formed in a cell part, a peripheral circuit part, or a mask frame.
이상에서 설명한 바와같이 본 발명에 따른 마스크 프레임은, 마스크 프레임의 여유공간에 일정간격으로 오픈영역과 차광영역을 형성하고 이를 이용한 후속공정시 정렬마크의 주변에 패턴을 형성함으로써 후속 CMP 공정시 정렬마크가 손상되는 현상을 방지할 수 있어 후속공정을 용이하게 실시할 수 있도록 하여 반도체소자의 특성 및 신뢰성을 향상시킬 수 있는 효과가 있다.As described above, the mask frame according to the present invention forms an open area and a light shielding area at a predetermined interval in the free space of the mask frame, and forms a pattern around the alignment mark in a subsequent process using the same. Can be prevented from being damaged so that subsequent processes can be easily performed, thereby improving the characteristics and reliability of the semiconductor device.
Claims (4)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980020981A KR100307222B1 (en) | 1998-06-05 | 1998-06-05 | Mask frame |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980020981A KR100307222B1 (en) | 1998-06-05 | 1998-06-05 | Mask frame |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20000000991A true KR20000000991A (en) | 2000-01-15 |
| KR100307222B1 KR100307222B1 (en) | 2001-10-19 |
Family
ID=19538533
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019980020981A KR100307222B1 (en) | 1998-06-05 | 1998-06-05 | Mask frame |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR100307222B1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100500934B1 (en) * | 2000-05-31 | 2005-07-14 | 주식회사 하이닉스반도체 | Method for forming semiconductor device capable of preventing over polishing at wafer edge |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2783973B2 (en) * | 1994-03-22 | 1998-08-06 | 沖電気工業株式会社 | Method of manufacturing mask for X-ray lithography |
| JP2977471B2 (en) * | 1995-08-25 | 1999-11-15 | 東光株式会社 | Alignment method of wafer alignment mark |
| JPH09232223A (en) * | 1996-02-19 | 1997-09-05 | Canon Inc | Method for alignment |
| US5705320A (en) * | 1996-11-12 | 1998-01-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Recovery of alignment marks and laser marks after chemical-mechanical-polishing |
-
1998
- 1998-06-05 KR KR1019980020981A patent/KR100307222B1/en not_active IP Right Cessation
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100500934B1 (en) * | 2000-05-31 | 2005-07-14 | 주식회사 하이닉스반도체 | Method for forming semiconductor device capable of preventing over polishing at wafer edge |
Also Published As
| Publication number | Publication date |
|---|---|
| KR100307222B1 (en) | 2001-10-19 |
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