KR20000000813A - Multi chip module - Google Patents

Abstract

PURPOSE: A multi chip module is for making the control of a loop easy and for having good electrical characteristics and low cost by shortening the length of a bonding wire. CONSTITUTION: A multi chip module comprises: a substrate(210) where many penetration slits(212) are formed and which has more than one conduction layer; more than one first integrated circuit chip(220) attached on a first surface of the substrate; more than one second integrated circuit chip(230) attached on a second surface of the substrate; many first bonding wires(240) connecting the second surface of the substrate with the bonding pad of a first integrated circuit chip; and many second bonding wires(250) connecting the first surface of the substrate with the bonding pad of a second integrated circuit chip.

Description

Multi chip module

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory module. More specifically, a plurality of integrated circuit chips are mounted on a substrate by a direct chip attachment (DCA) method and are electrically connected to the substrate by wire bonding. It relates to a chip module.

In general, an integrated circuit chip on which a circuit pattern is formed is packaged into various types such as a ball grid array (BGA) type, a lead on chip (LOC) type, a chip size package (CSP) type, and the like, followed by a printed circuit board (PCB). Alternatively, the module is constructed by mounting on a printed wiring board (PWB). The conventional structure of such a module is shown in plan and cross section respectively in FIGS. 1A and 1B. 1A and 1B, reference numeral 1 denotes a packaged integrated circuit chip, 2 a PCB or PWB substrate, and 3 a lead.

Recently, in order to increase the density of integrated circuit chips in a module, a direct chip attachment (DCA) method of directly mounting an unpackaged integrated circuit chip on a PCB or PWB substrate has been proposed. As such, wire bonding and flip chip bonding are widely used to electrically connect an integrated circuit chip to a substrate in a DCA scheme for constructing a high density module. Among them, the flip chip bonding method has a high cost, and therefore many applications are limited. In addition, the wire bonding method can provide a successful module when there are bonding pads around the integrated circuit chip, whereas when there is a bonding pad in the center of the integrated circuit chip such as DRAM, the loop of the wire becomes long. Problems are pointed out that it is difficult to control the loop and the electrical characteristics of the manufactured module are not good.

The present invention has been made to solve the above problems, and an object thereof is to provide a multi-chip module having a low manufacturing cost.

Another object of the present invention is to provide a multi-chip module that is easy to control the loop and has good electrical characteristics by shortening the length of the bonding wire.

1A and 1B are a plan view and a front view showing an example of a conventional memory module.

2 is a cross-sectional view showing a multi-chip module according to a first embodiment of the present invention.

3A and 3B are plan views showing a combination of a ground voltage region and an internal ground voltage region in the substrate according to FIG. 2;

4 is a cross-sectional view showing that a step is formed in a substrate in the module according to FIG. 2.

5 is a cross-sectional view showing that the module according to FIG. 2 is mounted on a PWC.

6 is a cross-sectional view showing a multi-chip module according to a second embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

100: module 110: substrate

112: through-slit 120: integrated circuit chip

130: adhesive 140: bonding wire

150: encapsulant 200: module

210: substrate 212: through slits

220: first integrated circuit chip 230: second integrated circuit chip

240: first bonding wire 250: second bonding wire

260: encapsulant

In order to achieve the above object of the present invention, a substrate having a first surface and a second surface facing each other, and having at least one conductive layer and a plurality of through slits are formed; At least one first integrated circuit chip having a surface on which a plurality of bonding pads are formed, the surface being attached to a first surface of the substrate; At least one second integrated circuit chip having a plurality of bonding pads formed thereon and attached to a second surface of the substrate; A plurality of first bonding wires electrically connecting the second surface of the substrate and the bonding pads of the first integrated circuit chip while passing through the through slits of the substrate; And a plurality of second bonding wires electrically connecting the first surface of the substrate and the bonding pads of the second integrated circuit chip while passing through other through slits of the substrate. Is provided.

Such a module according to the present invention has a low cost since the electrical connection between the substrate and the integrated circuit chip is made by wire bonding. In addition, the module of the present invention has a shorter wire length by connecting the substrate and the integrated circuit chip by bonding wires passing through the through slits formed in the substrate. Due to this shorted wire length, the module is easy to control the loop and has good electrical properties.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a cross-sectional view illustrating a multi-chip module according to a first embodiment of the present invention, and FIGS. 3A and 3B are plan views illustrating layers in which a ground voltage region and an internal ground voltage region are combined in a substrate according to FIG. 2. 4 is a cross-sectional view showing a step formed on a substrate in the module according to FIG. 2, FIG. 5 is a cross-sectional view showing a module mounted on the PWC according to FIG. 2, and FIG. 6 is a second embodiment of the present invention. Cross-sectional view showing a multi-chip module according to.

Referring to FIG. 2, the module 100 according to the first embodiment of the present invention includes a substrate 110 having a first surface 110a and a second surface 110b opposite the first surface. The substrate 110 has one or more through slits 112, which preferably have a rectangular planar shape or a rounded square planar shape. Also preferably used as the substrate 110 is a module PCB, a PGA for BGA, or a flexible film. Substrate 110 has at least one conductive layer. In addition, the substrate 110 may be formed of a plurality of conductive layers having an insulating film interposed between the conductive layers.

When the substrate 110 has two conductive layers, the upper layer corresponding to the first surface 110a is a power layer, and the lower layer corresponding to the second surface 110b is a signal layer. . On the other hand, if the substrate 110 consists of four conductive layers, the three layers on top corresponding to the first surface 110a are the power layer, and the one at the bottom corresponding to the second surface 110b. Layers are signal layers.

In addition, the substrate 110 may be applied to an integrated circuit chip using different internal power. When the chip uses internal power differently, when the applied substrate 110 is composed of two conductive layers, the upper layer corresponding to the first surface 110a has a ground voltage (V _ss ) region and an internal ground voltage (V _ssq ). The regions are combined power layers, and the lower layer corresponding to the second surface 110b is a signal layer. On the other hand, when the substrate 110 is applied to an integrated circuit chip consisting of four conductive layers and having different internal powers, each of the upper and third layers corresponding to the first surface 110a may be a power supply voltage power layer (V). _dd ), the internal power supply voltage power layer (V _ddq ), and the combined power layer (V _ss / V _ssq ) of the ground voltage region and the internal ground voltage region, and the lowest one layer corresponding to the second surface 110b is Signal layer. Here, the substrate 110 is a ground voltage region and in the case including a combination power layer (V _ss / V _ssq) of the internal ground voltage domain, combining a power layer of the ground voltage region and the internal ground voltage domain (V _ss / V _ssq ) May be composed of a double ring planar shaped region, as shown in FIG. 3A, or may be composed of four rectangular rod planar shaped regions, as shown in FIG. 3B.

Referring to FIG. 3A, the combination layer V _ss / V _{ssq of} the ground voltage region and the internal ground voltage region included in the substrate 110 may have a shape of a continuous inner ring plane formed around the through-slit 112. the internal supply voltage domain (V _ssq) (114) and the internal supply voltage domain (V _ssq) (114) ground potential area in the outer periphery of the outer ring plane at a predetermined distance from the internal power supply voltage regions formed continuously shape of ( V _ss ) 116. Conversely, in FIG. 3A, the inner ring planar region 114 may be the ground voltage power region V _ss , and the outer ring planar region 116 may be the internal ground voltage power region V _ssq . In addition, referring to FIG. 3B, a combination power layer V _ss / V _{ssq of} the ground voltage and the internal ground voltage included in the substrate 110 may have two inner rectangular bar plane shapes formed on both sides of the through-slit 112. Ground voltage power region (V _ss ) 116a of two outer rectangular bar plane shapes formed at the outer periphery of the internal power supply voltage power region (V _ssq ) 114a and the internal power supply voltage power region (V _ssq ) 114a Is done. Conversely, in FIG. 3B, the inner rectangular bar planar region 114a may be the ground voltage power region V _ss , and the outer rectangular bar planar region 116a may be the internal ground voltage power region V _ssq . As described above, the reference signal of the ground voltage power region V _{ss ref} and the reference ground voltage power region V _ss and the internal ground voltage power region V _ssq illustrated in FIGS. 3A and 3B are located at the positions of the lower signal layers. The internal ground voltage power region V _{ssq ref} is preferably placed.

Referring again to FIG. 2, a plurality of integrated circuit chips 120 are mounted on the first surface 110a of the substrate 110 by a chip attach method by an adhesive 130. In FIG. 2, a plurality of integrated integrated circuit chips are mounted on the substrate 110, but only one integrated circuit chip is mounted and included in the first embodiment of the present invention and belong to the scope of the present invention. Each integrated circuit chip 120 shown in FIG. 2 has a surface 120a on which a plurality of bonding pads 122 are formed. In addition, each integrated circuit chip has a substrate 110 in such a manner that the bonding pad 122 is positioned in the through-slit 112 of the substrate 110 while the surface 120a faces the first surface of the substrate 110. ) Is attached. On the other hand, the adhesive 130 used to attach each integrated circuit chip 120 to the substrate 110 is a liquid paste or a layer of epoxy film commonly used in LOC type packages, epoxy Preference is given to the elastomers used in the three layers of the film / base film / epoxy film or μ-BGA.

Each integrated circuit chip 120 is electrically connected to a substrate 110. For this electrical connection, the module 100 includes a plurality of bonding wires 140. The bonding wire 140 penetrates the through-slit 112 formed on the substrate 110, and one end thereof is bonded to the bonding pad 122 of the integrated circuit chip 120, and the other end thereof is formed of the substrate 110. 2 is bonded to surface 110b. After such electrical connection between the integrated circuit chip 120 and the substrate 110 by the bonding wire 140, the module 100 is encapsulated to protect the active area of the bonding wire 140 and the integrated circuit chip 120. It is encapsulated by the agent 150.

For this encapsulation, a glob top coating or a conventional molding method can be used. In the glow top coating, a guide ring is provided on the upper and / or lower surface of the module 100 to control the height of the encapsulant 150 while preventing bleed-out of the resin used as the encapsulant. ) Can be used. In the molding, the molding cavity may be configured by grouping the entire module 100 or by grouping one or more integrated circuit chips 120 suitable for productivity.

In the module 100 shown in FIG. 2, the integrated circuit chip 120 at the first surface 110a of the substrate 110 is mounted as shown in FIG. 4 to reduce the thickness of the module 100. Steps 110c and 110d may be formed at the portion to be bonded and / or the portion to which the bonding wire 140 is bonded at the second surface 110b.

In addition, the module 100 illustrated in FIG. 2 may use a tag attached to the substrate 110 as a terminal as a memory module.

In addition, the module 100 illustrated in FIG. 2 may be attached to the PWC as a component, such as a typical multi-chip module (MCM), when the substrate 110 is formed of a PCB to form a package. As shown in FIG. 5, the module 100 is attached to the PWC to form a package.

Referring to FIG. 5, the module 100 is attached to the PWC 50 by a conductive epoxy 70.

In the above, the module in which the integrated circuit chip is attached to one surface of the substrate has been described. However, in the second embodiment of the present invention, the integrated circuit chip may be attached to both sides of the substrate. Thus, a module in which an integrated circuit chip is attached on both sides of a substrate is shown in FIG. 6.

Referring to FIG. 6, the module 200 is directly chipped by the adhesive 130 on the first surface 210a and the second surface 210b of the substrate 210, unlike the module 100 shown in FIG. 2. A plurality of first integrated circuit chips 220 and a plurality of second integrated circuit chips 230 mounted in an attached manner. In FIG. 6, a plurality of integrated circuit chips are shown mounted on each of the first surface 210a and the second surface 210b of the substrate 210, but the first surface 210a and the second surface 210b are shown. In this case, only one integrated circuit chip is attached thereto, and is included in the second embodiment of the present invention and falls within the scope of the present invention. As in FIG. 2, the first and second integrated circuit chips 220 and 230 have surfaces 220a and 230a on which a plurality of bonding pads 222 and 232 are formed, respectively. However, the first integrated circuit chip 220 attached to the first surface 210a of the substrate 210 alternates with the second integrated circuit chip 230 attached to the second surface 210b of the substrate 210. It is arranged in the form. In other words, adjacent to one of the through slits 212 of the substrate 210 where the bonding pad 222 of the first integrated circuit chip 220 attached to the first surface 210a of the substrate 210 is located. Bonding pads 232 of the second integrated circuit chip 230, which are attached to the second surface 210b of the substrate 210, are located at the other side of the through slits 212. As such, the first integrated circuit chip 220 attached to the first surface 210a of the substrate 210 is electrically connected to the second surface 210b of the substrate 210 by the first bonding wire 240. The second integrated circuit chip 230 attached to the second surface 210b is electrically connected to the first surface 210a of the substrate 210 by the second bonding wire 250. For this electrical connection, the first bonding wire 240 penetrates through the through-slit 212, and one end is bonded to the bonding pad 222 of the first integrated circuit chip 220, and the other end is connected to the substrate ( Bonded to a second surface 210b of 210. In addition, the second bonding wire 250 penetrates the through-slit 212, and one end thereof is bonded to the bonding pad 232 of the second integrated circuit chip 230, and the other end thereof is the second of the substrate 210. Bonded to surface 210b.

As such, the substrate 210 in the module 200 in which the integrated circuit chips are mounted on the first surface 210a and the second surface 210b of the substrate 210 has two insulating films interposed between the respective conductive layers. It may be composed of the above conductive layer. When the substrate 210 consists of two conductive layers, both the upper layer and the lower layer are signal layers. In addition, when the substrate 210 is composed of four conductive layers, the uppermost layer and the lowermost layer are signal layers, and the two middle layers are power layers. When the substrate 210 consists of six conductive layers, the uppermost layer and the lowermost layer are the signal layers, and the four middle layers are the power layers. Thus, in the case of six conductive layers, the two power layers adjacent to the signal layer are ground voltage layers (V _ss ) or a combined power layer (V _ss / V _ssq ) of the ground voltage and the internal ground voltage, _respectively . The two power layers are power supply voltage power layer V _dd and internal power supply voltage power layer V _ddq , respectively. Here, when the substrate 210 includes a combined power layer (V _ss / V _ssq ) of the ground voltage and the internal ground voltage, the combined power layer (V _ss / V _ssq ) of the ground voltage and the internal ground voltage is already shown in FIG. 3A. And a power region in the shape of a double ring plane or a power region in the shape of a square bar plane, as described with reference to FIG. 3B. The reference ground voltage power region V _{ss ref} and the reference internal ground voltage power region V may be located at positions of the upper and lower signal layers corresponding to the ground voltage power region V _ss and the internal ground voltage power region V _ssq . _{ssq ref} ) is preferred.

The module 200 shown in FIG. 6 is encapsulated in accordance with the encapsulation method as described with respect to the module 100 shown in FIG. 2 after wire bonding by the first and second bonding wires 240, 250. It is sealed as 260.

In addition, the module 200 shown in FIG. 6 has a first integrated circuit chip 220 at the first surface 210a of the substrate 210 to reduce the thickness of the module as in the case of the module shown in FIG. The mounting portion and the portion where the first bonding wire 240 is bonded and / or the portion on which the second integrated circuit chip 230 is mounted on the second surface 210b of the substrate 210 and the second bonding wire ( Steps may be formed in a portion to which 250 is bonded.

In addition, the module 200 illustrated in FIG. 6 may use a tag attached to the substrate 210 as a terminal, such as a memory module.

In addition, the module 200 shown in FIG. 6 is a PWC as one component, like a conventional multi-chip module (MCM), as in the case of the module 100 shown in FIG. It can also be attached to make up a package.

In addition, although the module illustrated in FIGS. 2 and 6 has been described on the basis of having an integrated circuit chip having a center pad formed thereon, the module may be applied to an integrated circuit chip having a peripheral pad.

As described above, the module of the present invention has a low cost since the electrical connection between the substrate and the integrated circuit chip is made by wire bonding. The module of the present invention has a shorter wire length by electrically connecting the substrate and the integrated circuit chip by bonding wires passing through the through slits formed in the substrate. Due to this shorted wire length, the module is easy to control the loop and has good electrical properties.

Although the present invention has been described and illustrated with reference to preferred embodiments thereof, those skilled in the art can clearly see that various changes and modifications to the embodiments can be made without departing from the gist of the present invention.

Claims (13)

A substrate having a first surface and a second surface facing each other, and having at least one conductive layer and having a plurality of through slits formed thereon; At least one first integrated circuit chip having a surface on which a plurality of bonding pads are formed, the surface being attached to a first surface of the substrate; At least one second integrated circuit chip having a plurality of bonding pads formed thereon and attached to a second surface of the substrate; A plurality of first bonding wires electrically connecting the second surface of the substrate and the bonding pads of the first integrated circuit chip while passing through the through slits of the substrate; And And a plurality of second bonding wires electrically connecting the first surface of the substrate and the bonding pads of the second integrated circuit chip while passing through the other through slits of the substrate. The multichip module of claim 1, wherein the attachment of the first and second integrated circuit chips to the substrate is made by adhesive. The multi-chip module according to claim 2, wherein the adhesive is one selected from the group consisting of a liquid paste, one layer of an epoxy film, three layers of an epoxy film / base film / epoxy film, and an elastomer for μ-BGA. . The multichip module of claim 1, wherein the substrate is one selected from the group consisting of a PCB, a PWB, and a flexible film. The multichip module of claim 1, wherein the through-slit has a substantially rectangular planar shape. The multichip module of claim 1, wherein the substrate has conductive layers made up of two signal layers respectively corresponding to the first surface and the second surface. 2. The multi-layer of claim 1, wherein the substrate has four conductive layers, each consisting of two signal layers corresponding to a first surface and a second surface, and two power layers positioned between the signal layers. Chip module. 2. The multi-layer of claim 1, wherein the substrate has six conductive layers comprising two signal layers corresponding to a first surface and a second surface, respectively, and four power layers positioned between the signal layers. Chip module. 9. The power supply device of claim 8, wherein the power layer comprises two layers each adjacent to the signal layer, wherein a ground voltage region and an internal ground voltage region are combined, and an internal power supply voltage layer adjacent to one of the combined layers; And a power supply voltage layer adjacent to the internal power supply voltage layer and adjacent to the other one of the combined layers. 9. The power supply circuit of claim 8, wherein the power layer includes two ground voltage layers each adjacent to the signal layer, an internal power voltage layer adjacent to one of the ground voltage layers, and adjacent to the internal power voltage layer. And a power supply voltage layer adjacent to the other one of the ground voltage layers. 10. The method according to claim 9, wherein the combination of the ground voltage region and the inner ground voltage region is a predetermined inner ring planar inner region continuously formed at the periphery of the through-slit and the inner region at the periphery of the inner region. The multi-chip module, characterized in that formed by two ring planar region consisting of an outer region of the outer ring plane shape continuously formed at intervals. 10. The method of claim 9, wherein the combination of the ground voltage region and the internal ground voltage region comprises an inner region of two rectangular bar plane shapes formed discontinuously around the through-slit and the inner region outside of the inner region. Multi-chip module, characterized in that the outer region formed of two rectangular bar plane shape formed discontinuously at a predetermined interval from the. The substrate of claim 1, wherein the substrate is formed at a portion at which the first and second integrated circuit chips are mounted at the first and second surfaces and / or at a portion at which the bonding wires at the first and second surfaces are bonded. Multi-chip module characterized in that it has a step.