KR20000000625A - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor device Download PDFInfo
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- KR20000000625A KR20000000625A KR1019980020347A KR19980020347A KR20000000625A KR 20000000625 A KR20000000625 A KR 20000000625A KR 1019980020347 A KR1019980020347 A KR 1019980020347A KR 19980020347 A KR19980020347 A KR 19980020347A KR 20000000625 A KR20000000625 A KR 20000000625A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823892—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
Abstract
본 발명은 반도체장치의 제조방법에 관한 것으로서 특히, 반도체소자중 저전압소자에 고내압이 공존하는 소자의 제조에 있어서 NMOS 혹은 PMOS 소자의 문턱전압을 조절하기 위하여 사진공정을 사용하는 이온주입공정의 단순화를 성취하므로서 공정비용의 절감을 가져오고 또한 고전압 p 채널 소자에서는 펀치-스루를 방지하는 효과를 가져와서 소자내압특성을 개선하는 반도체장치의 문턱전압 조절방법에 관한 것이다. 이를 위하여 본 발명은 필드영역과 제 1 활성영역 내지 제 4 활성영역이 순서대로 형성되고 제 3 활성영역과 제 4 활성영역은 제 2 도전형 웰에 형성된 제 1 도전형 반도체기판 위에 제 1 도전형 불순물로 제 1 이온주입을 실시하는 단계와, 제 1 활성영역과 제 4 활성영역만을 노출시키는 제 1 마스크를 기판 위에 형성하는 단계와, 기판 전면에 제 1 도전형 불순물로 제 2 이온주입을 실시하는 단계와, 제 1 마스크를 제거하는 단계와, 제 3 활성영역만을 노출시키는 제 2 마스크를 기판 위에 형성하는 단계와, 기판 전면에 제 2 도전형 불순물로 제 3 이온주입을 실시하는 단계와, 제 2 마스크를 제거하는 단계를 포함하여 이루어진다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and in particular, to simplify the ion implantation process using a photo process to control the threshold voltage of an NMOS or PMOS device in the manufacture of a device having high breakdown voltage in a low voltage device among semiconductor devices. The present invention relates to a method for adjusting the threshold voltage of a semiconductor device, which achieves a reduction in process cost and also has an effect of preventing punch-through in high voltage p-channel devices, thereby improving device breakdown voltage characteristics. To this end, in the present invention, the field region and the first active region to the fourth active region are sequentially formed, and the third active region and the fourth active region are formed on the first conductive semiconductor substrate formed in the second conductive type well. Performing a first ion implantation with impurities, forming a first mask exposing only the first active region and the fourth active region on the substrate, and performing a second ion implantation with the first conductivity type impurities on the entire surface of the substrate Removing the first mask, forming a second mask exposing only the third active region on the substrate, performing a third ion implantation with a second conductivity type impurity on the entire surface of the substrate, Removing the second mask.
Description
본 발명은 반도체장치의 제조방법에 관한 것으로서 특히, 반도체소자중 저전압소자에 고내압이 공존하는 소자의 제조에 있어서 NMOS 혹은 PMOS 소자의 문턱전압을 조절하기 위하여 사진공정을 사용하는 이온주입공정의 단순화를 성취하므로서 공정비용의 절감을 가져오고 또한 고전압 p 채널 소자에서는 펀치-스루를 방지하는 효과를 가져와서 소자내압특성을 개선하는 반도체장치의 문턱전압 조절방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and in particular, to simplify the ion implantation process using a photo process to adjust the threshold voltage of an NMOS or PMOS device in the manufacture of a device having high breakdown voltage in a low voltage device among semiconductor devices. The present invention relates to a method for adjusting the threshold voltage of a semiconductor device, which achieves a reduction in process cost and also has an effect of preventing punch-through in high voltage p-channel devices, thereby improving device breakdown voltage characteristics.
반도체장치가 고집적화 됨에 따라 각각의 셀은 미세해져 내부의 전계 강도가 증가된다. 이러한 전계 강도의 증가는 소자 동작시 드레인 부근의 공핍층에서 채널영역의 캐리어를 가속시켜 게이트산화막으로 주입시키는 핫-캐리어 효과(hot-carrier effect)를 일으킨다. 상기 게이트산화막에 주입된 캐리어는 반도체기판과 게이트산화막의 계면에 준위를 생성시켜 문턱전압(threshold voltage : VTH)을 변화시키거나 상호 컨덕턴스를 저하시켜 소자 특성을 저하시킨다. 그러므로, 핫-캐리어 효과에 의한 소자 특성의 저하를 감소시키기 위해 채널영역에 이온주입 등의 방법으로 불순물을 매몰시켜 문턱전압을 조절하거나 LDD(Lightly Doped Drain) 등과 같이 드레인 구조를 변화시킨 구조를 사용하여야 한다. 종래 기술에 의한 반도체소자중 모스 제품들은 소자의 채널영역의 문턱전압을 조절하기 위한 이온주입공정이 필수적이다.As the semiconductor device is highly integrated, each cell becomes finer and the internal electric field strength is increased. This increase in electric field strength causes a hot-carrier effect in which the carrier of the channel region is accelerated and injected into the gate oxide layer in the depletion layer near the drain during operation of the device. The carrier injected into the gate oxide film creates a level at an interface between the semiconductor substrate and the gate oxide film, thereby changing the threshold voltage (V TH ) or lowering the mutual conductance, thereby degrading device characteristics. Therefore, in order to reduce the deterioration of device characteristics due to the hot-carrier effect, an impurity is buried in the channel region by a method such as ion implantation to adjust the threshold voltage or change the drain structure such as LDD (Lightly Doped Drain). shall. Morse products of the semiconductor device according to the prior art require an ion implantation process to adjust the threshold voltage of the channel region of the device.
일반적으로 고전압 제품의 경우에 제품의 입출력회로는 고전압소자로 하고 내부의 논리회로는 저전압소자로 하게 된다. 대부분의 경우 고전압과 저전압소자는 중요한 자체소자의 특성으로서 내압(breakdown voltage)뿐만 아니라 소자의 문턱전압(threshold voltage)을 설정하여야 한다. 문턱전압을 조절하기 위한 이온주입을 각각의 소자가 형성될 부위에 별도로 실시하여야 하므로 독립적인 포토 마스크가 반드시 필요하게 된다. 일반적인 회로의 경우 소자는 CMOS 구조로 되어 있으므로 n 채널과 p 채널이 필요로 하게 되고 각각의 문턱전압을 위해서는 총 네개의 사진공정과 포토 마스크가 필요로 하게 된다.In general, in the case of a high voltage product, the input / output circuit of the product is a high voltage device and the internal logic circuit is a low voltage device. In most cases, high voltage and low voltage devices are important characteristics of their own devices, and must set the threshold voltage of the device as well as the breakdown voltage. Since ion implantation for adjusting the threshold voltage must be performed separately at the site where each device is to be formed, an independent photo mask is necessary. In the general circuit, since the device has a CMOS structure, n-channel and p-channel are required, and a total of four photo processes and a photo mask are required for each threshold voltage.
도 1a 내지 도 1d는 종래 기술에 따른 반도체장치의 문턱전압 조절방법 공정단면도이다.1A to 1D are cross-sectional views illustrating a method for adjusting a threshold voltage of a semiconductor device according to the related art.
도 1a를 참조하면, n 웰(3)이 형성된 p형의 반도체기판(1) 표면의 소정 부분에 LOCOS(Local Oxidation of Silicon) 등의 통상적인 선택산화방법에 의해 필드산화막(2)을 형성하여 소자의 활성영역 및 필드영역을 한정한다.Referring to FIG. 1A, a field oxide film 2 is formed on a predetermined portion of a surface of a p-type semiconductor substrate 1 on which n wells 3 are formed by a conventional selective oxidation method such as LOCOS (Local Oxidation of Silicon). The active area and the field area of the device are defined.
그리고 고전압 n 채널을 갖는 영역을 형성하기 위하여 제 1 영역(R1)을 노출시키는 제 1 포토레지스트패턴(4)을 형성한다.In order to form a region having a high voltage n channel, a first photoresist pattern 4 exposing the first region R1 is formed.
제 1 포토레지스트패턴(4)으로 보호되지 아니하는 기판(1)의 노출 부위에 붕소이온 주입을 35 KeV의 에너지와 4.0E12의 농도로 실시하여 불순물 매몰층을 기판에 형성한다.Boron ion implantation is performed in the exposed portion of the substrate 1 not protected by the first photoresist pattern 4 at an energy of 35 KeV and a concentration of 4.0E12 to form an impurity buried layer on the substrate.
도 1b를 참조하면, 제 1 포토레지스트패턴(4)을 제거한 다음 저전압 n 채널영역을 형성하기 위하여 제 2 영역(R2)의 기판(1) 표면을 노출시키는 제 2 포토레지스트패턴(5)을 형성한다.Referring to FIG. 1B, the second photoresist pattern 5 exposing the surface of the substrate 1 of the second region R2 is formed to remove the first photoresist pattern 4 and then form a low voltage n channel region. do.
제 2 포토레지스트패턴(5)으로 보호되지 아니하는 기판(1)의 노출부위에 붕소이온주입을 35 KeV의 에너지와 1.0E12의 농도로 실시하여 불순물 매몰층을 기판(1)에 형성한다.Boron ion implantation is performed on the exposed portion of the substrate 1 not protected by the second photoresist pattern 5 at an energy of 35 KeV and a concentration of 1.0E12 to form an impurity buried layer on the substrate 1.
도 1c를 참조하면, 제 2 포토레지스트패턴(5)을 제거한 다음 고전압 p 채널영역을 형성하기 위하여 제 3 영역(R3)의 기판(1) 표면을 노출시키는 제 3 포토레지스트패턴(6)을 형성한다.Referring to FIG. 1C, after removing the second photoresist pattern 5, a third photoresist pattern 6 is formed to expose the surface of the substrate 1 of the third region R3 to form a high voltage p-channel region. do.
제 3 포토레지스트패턴(6)으로 보호되지 아니하는 기판(1)의 노출부위에 BF2이온주입을 80 KeV의 에너지와 5.0E11의 농도로 실시하여 불순물 매몰층을 기판(1)에 형성한다.An impurity buried layer is formed on the substrate 1 by implanting BF 2 ions into an exposed portion of the substrate 1 that is not protected by the third photoresist pattern 6 at an energy of 80 KeV and a concentration of 5.0E11.
도 1d를 참조하면, 제 3 포토레지스트패턴(6)을 제거한 다음 저전압 p 채널영역을 형성하기 위하여 제 4 영역(R4)의 기판(1) 표면을 노출시키는 제 4 포토레지스트패턴(7)을 형성한다.Referring to FIG. 1D, a fourth photoresist pattern 7 is formed to expose the surface of the substrate 1 of the fourth region R4 to remove the third photoresist pattern 6 and then form a low voltage p-channel region. do.
제 4 포토레지스트패턴(7)으로 보호되지 아니하는 기판(1)의 노출부위에 BF2이온주입을 35 KeV의 에너지와 4.0E12의 농도로 실시하여 불순물 매몰층을 기판(1)에 형성한다.An impurity buried layer is formed on the substrate 1 by implanting BF 2 ions into an exposed portion of the substrate 1 that is not protected by the fourth photoresist pattern 7 at an energy of 35 KeV and a concentration of 4.0E12.
이후 제 4 포토레지스트패턴을 제거한 다음 게이트 산화막, 게이트 등을 형성하여 트랜지스터 소자를 제조한다.Thereafter, the fourth photoresist pattern is removed, and then a gate oxide film, a gate, or the like is formed to manufacture a transistor device.
그러나, 상술한 바와 같이 종래 기술에서는 NMOS 소자와 PMOS 소자의 문턱전압을 제어하기 위하여 각각의 소자수 만큼 별도의 이온주입공정을 수행하여야 하는바 이는 공정의 단순화에 장애가 되어 생산비용을 상승시키는 문제점이 있다.However, as described above, in order to control the threshold voltages of the NMOS device and the PMOS device, a separate ion implantation process must be performed as many as the number of devices, which hinders the process simplification and increases the production cost. have.
따라서, 본 발명의 목적은 반도체소자의 트렌지스터인 NMOS 혹은 PMOS 의 문턱전압을 조절하기 위한 이온주입공정을 동시에 실시하여 불필요한 공정 수를 단축시키며, 고전압 p채널 소자에 있어서는 카운터 도핑에 의한 웰의 농도를 상승시키므로 펀치-스루 형상을 개선하는 반도체장치의 문턱전압 조절방법을 제공하는데 있다.Accordingly, an object of the present invention is to simultaneously perform the ion implantation process for adjusting the threshold voltage of the NMOS or PMOS transistor of the semiconductor device to reduce the number of unnecessary steps, and in the high-voltage p-channel device to reduce the well concentration by counter doping. The present invention provides a method for adjusting the threshold voltage of a semiconductor device by increasing the punch-through shape.
상기 목적을 달성하기 위한 본 발명에 따른 반도체장치의 제조방법은 필드영역과 제 1 활성영역 내지 제 4 활성영역이 순서대로 형성되고 제 3 활성영역과 제 4 활성영역은 제 2 도전형 웰에 형성된 제 1 도전형 반도체기판 위에 제 1 도전형 불순물로 제 1 이온주입을 실시하는 단계와, 제 1 활성영역과 제 4 활성영역만을 노출시키는 제 1 마스크를 기판 위에 형성하는 단계와, 기판 전면에 제 1 도전형 불순물로 제 2 이온주입을 실시하는 단계와, 제 1 마스크를 제거하는 단계와, 제 3 활성영역만을 노출시키는 제 2 마스크를 기판 위에 형성하는 단계와, 기판 전면에 제 2 도전형 불순물로 제 3 이온주입을 실시하는 단계와, 제 2 마스크를 제거하는 단계를 포함하여 이루어진다.In the semiconductor device manufacturing method according to the present invention for achieving the above object, the field region and the first active region to the fourth active region are formed in order and the third active region and the fourth active region are formed in the second conductivity type well. Performing a first ion implantation with a first conductivity type impurity on the first conductivity type semiconductor substrate, forming a first mask on the substrate exposing only the first active region and the fourth active region, Performing a second ion implantation with a first conductivity type impurity, removing the first mask, forming a second mask exposing only the third active region on the substrate, and forming a second conductivity type impurity on the entire surface of the substrate And performing a third ion implantation, and removing the second mask.
도 1a 내지 도 1d는 종래 기술에 따른 반도체장치의 문턱전압 조절방법 공정단면도1A to 1D are cross-sectional views of a threshold voltage adjusting method of a semiconductor device according to the related art.
도 2a 내지 도 2c는 본 발명에 따른 반도체장치의 문턱전압 조절방법 공정단면도2A to 2C are cross-sectional views illustrating a method for adjusting a threshold voltage of a semiconductor device according to the present invention.
본 발명에서는 종래의 복잡한 문턱전압조절을 위한 이온주입공정을 효과적으로 최적화하여In the present invention, by effectively optimizing the ion implantation process for the conventional complex threshold voltage control
이하, 첨부한 도면을 참조하여 본 발명을 상세히 설명한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2c는 본 발명에 따른 반도체장치의 문턱전압 조절방법 공정단면도이다.2A to 2C are cross-sectional views illustrating a method for adjusting a threshold voltage of a semiconductor device according to the present invention.
도 2a를 참조하면, P형의 반도체기판(21)에 능동소자의 구현을 위한 N웰영역(23)을 형성하고 기판(21)표면의 소정 부분에 LOCOS(Local Oxidation of Silicon) 등의 통상적인 선택산화방법에 의해 필드산화막(22)을 형성하여 소자의 활성영역 및 필드영역을 한정한다. 이때 웰영역은 모스소자의 종류에 따라 P형기판인 경우 N형 웰이되고 N형 기판인 경우 P형웰이 된다.Referring to FIG. 2A, an N well region 23 is formed on a P-type semiconductor substrate 21 for implementing active devices, and a local portion of silicon (LOCOS) or the like is formed on a predetermined portion of the surface of the substrate 21. The field oxide film 22 is formed by the selective oxidation method to define the active region and the field region of the device. In this case, the well region may be an N type well in the case of a P type substrate and a P type well in the case of an N type substrate according to the type of MOS device.
그다음 종래기술과는 다르게 포토마스크를 형성하지 아니하고 기판(21)의 전면에 저전압 n채널영역으로 제 2 영역(A2)을 형성하기 위한 이온주입을 붕소이온을 사용하여 35 KeV의 에너지와 1.0E12의 농도로 실시한다. 이때 포토마스크를 사용하지 아니한 이온주입을 실시하였으므로 고전압 n채널영역으로 제 1 영역(A1), 저전압 p채널영역으로 제 4 영역(A4) 그리고 고전압 p채널영역으로 제 3 영역(A3)에 모두 붕소이온이 1.0E12 농도로 이온주입된다.Then, unlike in the prior art, ion implantation for forming the second region A2 into the low voltage n-channel region on the front surface of the substrate 21 without forming a photomask is performed using boron ions to achieve energy of 35 KeV and 1.0E12. Conduct at concentration. At this time, since ion implantation was performed without using a photomask, all of the boron in the first region A1 as the high voltage n-channel region, the fourth region A4 as the low voltage p-channel region, and the third region A3 as the high voltage p-channel region. Ions are implanted at a concentration of 1.0E12.
도 2b를 참조하면, 기판(21)의 전면에 포토레지스트를 도포한 다음 사진공정을 실시하여 고전압 n채널영역으로 제 1 영역(A1)과 저전압 p채널영역으로 제 4 영역(A4)의 기판(21) 표면만을 노출시키는 제 1 포토레지스트패턴(24)을 형성한다.Referring to FIG. 2B, a photoresist is coated on the entire surface of the substrate 21, and then a photolithography process is performed so that the substrate of the first region A1 as the high voltage n-channel region and the fourth region A4 as the low voltage p-channel region ( 21) The first photoresist pattern 24 exposing only the surface is formed.
기판(21)의 전면에 붕소이온을 사용하여 35 KeV의 에너지와 3.0E12의 농도로 이온주입을 실시하여 제 1 포토레지스트패턴(24)으로 보호되지 아니하는 제 1 영역(A1)과 제 4 영역(A4)의 기판(21)에 불순물 매몰층을 각각형성한다.The first region A1 and the fourth region which are not protected by the first photoresist pattern 24 by performing ion implantation using a boron ion on the front surface of the substrate 21 at an energy of 35 KeV and a concentration of 3.0E12. Impurity embedding layers are formed in the substrate 21 of (A4), respectively.
따라서, 제 1 영역(A1)의 기판에는 붕소이온이 35 KeV의 에너지로 4.0E12의 농도로 불순물매몰층이 형성되고, 제 2 영역(A2)의 기판에는 붕소이온이 35 KeV의 에너지로 1.0E12의 농도로 불순물매몰층이 형성되며, 제 3 영역(A3)의 기판에는 붕소이온이 35 KeV의 에너지로 1.0E12의 농도로 불순물매몰층이 형성되고 또한 제 4 영역(A4)의 기판에는 붕소이온이 35 KeV의 에너지로 4.0E12의 농도로 불순물매몰층이 형성된다.Accordingly, an impurity buried layer is formed in the substrate of the first region A1 at a concentration of 4.0E12 at an energy of 35 KeV and boron ions at an energy of 35 KeV at a substrate of the second region A2 at 1.0E12. The impurity buried layer is formed at a concentration of, and an impurity buried layer is formed at a concentration of 1.0E12 at 35 KeV energy in the substrate of the third region A3, and a boron ion is formed at the substrate of the fourth region A4. An impurity embedding layer is formed at a concentration of 4.0E12 with an energy of 35 KeV.
즉, 이때의 이온주입량은 고전압 n채널영역(A1)과 저전압 p 채널영역(A4)을 형성하기 위한 총 이온주입량에서 이미 이온주입된 양을 감한 만큼의 이온주입을 실시한다.In other words, the ion implantation amount is ion implanted by subtracting the ion implantation amount from the total ion implantation amount for forming the high voltage n channel region A1 and the low voltage p channel region A4.
도 2c를 참조하면, 제 1 포토레지스트패턴을 제거한 다음 다시 기판(21)의 전면에 포토레지스트를 도포한 다음 고전압 p채널영역으로 제 3 영역(A3)을 형성하기 위하여 제 3 영역(A3)만을 노출시키는 사진공정을 실시하여 제 2 포토레지스트패턴(25)을 형성한다.Referring to FIG. 2C, after removing the first photoresist pattern, the photoresist is applied to the entire surface of the substrate 21, and only the third region A3 is formed to form the third region A3 as the high voltage p-channel region. The photolithography process is performed to expose the second photoresist pattern 25.
기판(21)의 전면에 인이온을 사용하여 150 KeV의 에너지와 3.0E11의 농도로 이온주입을 실시하여 제 2 포토레지스트패턴(25)으로 보호되지 아니하는 제 3 영역(A3)의 기판(21)에 불순물 매몰층을 형성한다.The substrate 21 of the third region A3 which is not protected by the second photoresist pattern 25 by implanting ions at an energy of 150 KeV and a concentration of 3.0E11 using phosphorus ions on the entire surface of the substrate 21. ) An impurity embedding layer is formed.
따라서 제 3 영역(A3)의 기판(21)에는, 붕소이온이 35 KeV의 에너지로 1.0E12의 농도로 불순물매몰층이 형성되어 있는데 여기에 새로 인이 150 KeV의 에너지와 3.0E11의 농도로 이온주입 된다. 즉, 제 3 영역에는 인이온으로 카운터 도핑되어 적정 문턱전압을 형성한다.Accordingly, an impurity buried layer is formed in the substrate 21 of the third region A3 at a concentration of 1.0E12 with boron ions at an energy of 35 KeV. Is injected. That is, the third region is counter-doped with in ions to form an appropriate threshold voltage.
결과적으로, 종래기술과 비교하여 동일한 도핑결과를 얻으면서 4 개의 사진 마스크공정이 2 개의 공정으로 단순화되며 모든 영역의 문턱전압을 모두 만족시킨다.As a result, four photo mask processes are simplified to two processes while satisfying the same doping result compared with the prior art, and satisfy all threshold voltages of all regions.
이후, 제 2 포토레지스트패턴을 제거하고 게이트산화막, 게이트, 소스/드레인 등을 형성하여 CMOS 소자를 완성한다.Thereafter, the second photoresist pattern is removed to form a gate oxide film, a gate, a source / drain, and the like to complete the CMOS device.
따라서, 본 발명은 일반적인 반도체 모스소자 제조공정에서 고전압 소자와 저전압소자가 공존하는 경우 감소된 마스크공정수로 각각 트랜지스터의 문턱전압을 만족시키크로 제품의 생산단가를 낮추며, 또한 고전압 p채널의 경우 인이온에 의한 카운터 도핑으로 문턱전압 뿐만 아니라 채널내이 형성된 웰의 농도를 높이므로 펀치-스루 현상을 방지하여 소자의 내압특성을 개선하는 장점이 있다.Accordingly, the present invention lowers the production cost of the product by satisfying the threshold voltages of the transistors with the reduced number of mask processes when the high voltage device and the low voltage device coexist in a general semiconductor MOS device manufacturing process. The counter doping by ions increases the concentration of the wells formed in the channel as well as the threshold voltage, thereby preventing the punch-through phenomenon and improving the breakdown voltage characteristics of the device.
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