KR19990086049A - Manufacturing method of pressure sensor - Google Patents
Manufacturing method of pressure sensor Download PDFInfo
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- KR19990086049A KR19990086049A KR1019980018834A KR19980018834A KR19990086049A KR 19990086049 A KR19990086049 A KR 19990086049A KR 1019980018834 A KR1019980018834 A KR 1019980018834A KR 19980018834 A KR19980018834 A KR 19980018834A KR 19990086049 A KR19990086049 A KR 19990086049A
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- semiconductor substrate
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 33
- 239000004065 semiconductor Substances 0.000 claims abstract description 32
- 229910052751 metal Inorganic materials 0.000 claims abstract description 28
- 239000002184 metal Substances 0.000 claims abstract description 28
- 238000000034 method Methods 0.000 claims abstract description 19
- 238000005530 etching Methods 0.000 claims abstract description 14
- 230000001681 protective effect Effects 0.000 claims abstract description 11
- 238000002955 isolation Methods 0.000 claims description 8
- 230000015572 biosynthetic process Effects 0.000 claims description 6
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 7
- 229910052710 silicon Inorganic materials 0.000 abstract description 7
- 239000010703 silicon Substances 0.000 abstract description 7
- 239000010410 layer Substances 0.000 description 19
- 238000005229 chemical vapour deposition Methods 0.000 description 7
- 238000000206 photolithography Methods 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 239000011810 insulating material Substances 0.000 description 3
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 239000011241 protective layer Substances 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- -1 Phospho Chemical class 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/84—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by variation of applied mechanical force, e.g. of pressure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0804—Emitter regions of bipolar transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1004—Base region of bipolar transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Pressure Sensors (AREA)
- Measuring Fluid Pressure (AREA)
Abstract
본 발명은 바이폴라 트랜지스터를 구비하는 압력센서의 제조방법에 관한 것으로서, 상기 반도체 기판의 이면 식각에 앞서 접촉부와 금속전극을 먼저 형성함으로써 웨이퍼의 파손을 막아 수율을 향상시킬 수 있으며, 또한 상기 보호막이 상기 반도체 기판의 이면 식각시 상기 금속전극을 포함한 상부구조물들 실리콘 식각액으로부터 보호할뿐 아니라 소자의 최종 보호막으로도 사용함으로써 종래와 같은 별도의 전극보호막을 형성할 필요가 없으므로 공정이 용이하며 공정시간을 단축할 수 있는 효과가 있다.The present invention relates to a method of manufacturing a pressure sensor having a bipolar transistor, wherein the contact portion and the metal electrode are first formed before etching the back surface of the semiconductor substrate to prevent breakage of the wafer to improve the yield. When etching the back surface of the semiconductor substrate, the upper structures including the metal electrode are not only protected from the silicon etchant but also used as the final protective film of the device, thus eliminating the need to form a separate electrode protective film as in the prior art, and thus, the process is easy and the process time is shortened. It can work.
Description
본 발명은 압력센서의 제조방법에 관한 것으로서, 특히 공정시간을 단축하고 수율을 증가시킬 수 있는 압력센서의 제조방법에 관한 것이다.The present invention relates to a method of manufacturing a pressure sensor, and more particularly to a method of manufacturing a pressure sensor that can shorten the process time and increase the yield.
압력센서소자의 제조공정 중 실리콘 식각공정은 매우 중요한데, 종래의 경우 바이폴라( bipolar)의 에미터(emitter) 영역 형성하고, 이 에미터 영역을 포함한 바이폴라가 형성되어 있는 반도체 기판의 상부 전면을 마스크(mask)로 보호한 후 반도체 기판의 반대면을 식각하는 방법을 사용하였다.In the manufacturing process of the pressure sensor element, the silicon etching process is very important. In the conventional case, the bipolar emitter region is formed, and the upper surface of the semiconductor substrate on which the bipolar including the emitter region is formed is masked ( After protecting with a mask, a method of etching the opposite side of the semiconductor substrate was used.
도 1a 내지 도 1c를 참조하여 이를 개략적으로 설명하면, 먼저 도 1a 에서는 도시한 바와 같이 반도체기판(1) 내에 통상적인 바이폴라 트랜지스터의 제조방법을 이용하여 매립층(2)과, 에피텍셜층(3), 소자분리영역(4), 베이스 영역(5) 및 에미터 영역(6)을 형성하고, 결과물의 전면에 절연물질로서 예를들어 PSG(Phospho Silicated Glass) 또는 CVD(Chemical Vapor deposition) 실리콘산화막으로 제 2 절연막(10)을 형성한 후 다시 상기 제 2 절연막(10) 위에 LPCVD(Low Pressure Chemical Vapor deposition) Si3N4을 침전시켜 반도체 기판의 이면 식각공정시 상부 구조물들을 보호하기 위한 보호막(11)을 형성한다.1A to 1C, the buried layer 2 and the epitaxial layer 3 will be described with reference to FIG. 1A by using a conventional method of manufacturing a bipolar transistor in the semiconductor substrate 1 as shown in FIG. 1A. A device isolation region 4, a base region 5 and an emitter region 6 are formed, and as an insulating material on the front surface of the resultant, for example, PSG (Phospho Silicated Glass) or CVD (Chemical Vapor Deposition) silicon oxide film. After forming the second insulating film 10, a protective film 11 for protecting upper structures during the back surface etching process of the semiconductor substrate by depositing Low Pressure Chemical Vapor Deposition (LPCVD) Si 3 N 4 on the second insulating film 10. ).
이때 상기 반도체 기판(1)의 이면에는 실리콘 나이트라이드(Si3N4)로 이루어진 제 3 절연막(12)이 형성되어 있으며, 미설명부호 7,8은 적층순서대로 실리콘을 열산화시킨 제 1 및 제 2 산화막이고, 9는 CVD 실리콘 산화막을 침전(deposition )시켜 형성한 제 1 절연막이다.At this time, a third insulating film 12 made of silicon nitride (Si 3 N 4 ) is formed on the back surface of the semiconductor substrate 1, and reference numeral 7, 8 denotes first and second thermal oxidation of silicon in the stacking order. 9 is a first insulating film formed by depositing a CVD silicon oxide film.
이어서 도 1b 에서는 상기 반도체 기판 이면의 제 3 절연막(12)을 사진식각방법을 이용하여 선택적으로 식각하고 이를 마스크로 하여 상기 반도체 기판 이면을 식각액을 이용하여 소정 깊이까지 식각한다.Subsequently, in FIG. 1B, the third insulating layer 12 on the back surface of the semiconductor substrate is selectively etched using a photolithography method, and the back surface of the semiconductor substrate is etched to a predetermined depth by using an etching solution as a mask.
이어서 도 1c 에서는 상기 반도체 기판 이면의 제 3 절연막과 상기 반도체 기판 표면의 보호막을 동시에 제거하고, 반도체 기판의 표면 상부에 순차적층된 제 1, 제 2 산화막(7,8)과 제 1, 제 2 절연막(9,10)을 선택적으로 식각하여 접촉부(contact hole)를 형성한 후 금속전극(13)을 형성하며, 다시 상기 금속전극(13) 위에 금속전극을 보호하기 위한 전극보호막(14)을 형성한다.Subsequently, in FIG. 1C, the third insulating film on the back surface of the semiconductor substrate and the protective film on the surface of the semiconductor substrate are simultaneously removed, and the first and second oxide films 7 and 8 and the first and second layers sequentially layered on the surface of the semiconductor substrate. Selectively etching the insulating films 9 and 10 to form a contact hole, and then forming a metal electrode 13, and then forming an electrode protective layer 14 to protect the metal electrode on the metal electrode 13. do.
그러나 상기와 같은 종래의 압력센서는, 상기 반도체 기판의 이면 식각시 상기 반도체 기판 표면의 상부구조물들을 보호하기 위해 일반적으로 LPCVD에 의한 실리콘 나이트라이드 형성공정이 추가되어 공정이 복잡하고 그에 따른 공정시간이 증가할뿐만 아니라, 도 1b 에 도시한 바와 같이 반도체 기판의 식각된 부분이 가공되는 웨이퍼의 대부분의 면적을 차지하므로 반도체 기판 이면 식각 후의 접촉부 및 금속전극 형성시 웨이퍼가 파손됨으로써 수율이 저하되는 등 많은 문제점들이 있다.However, in the conventional pressure sensor as described above, in order to protect the upper structures of the surface of the semiconductor substrate when the backside of the semiconductor substrate is etched, a silicon nitride forming process by LPCVD is generally added, which makes the process complicated and the processing time accordingly. In addition, as shown in FIG. 1B, since the etched portion of the semiconductor substrate occupies most of the area of the wafer to be processed, the yield is lowered due to breakage of the wafer during the formation of the contact portion and the metal electrode after etching the back surface of the semiconductor substrate. There are problems.
따라서 본 발명의 목적은 상기와 같은 종래 기술의 문제점을 해결하기 위하여 접촉부 및 금속전극을 형성한 후 반도체 기판의 이면을 식각함으로써 공정시간을 단축하고 수율을 향상시킬 수 있는 압력센서의 제조방법을 제공하는 것이다.Accordingly, an object of the present invention is to provide a manufacturing method of a pressure sensor that can shorten the process time and improve the yield by etching the back surface of the semiconductor substrate after forming the contact portion and the metal electrode to solve the problems of the prior art as described above. It is.
상기 목적을 달성하기 위한 본 발명의 압력센서 제조방법은, 바이폴라 트랜지스터를 구비하는 압력센서의 제조방법에 있어서, 반도체 기판에 소자분리영역을 형성하여 소자분리영역과 소자형성영역을 정의하는 단계와, 상기 소자형성영역에 상기 바이폴라 트랜지스터의 베이스 영역 및 에미터 영역을 형성하는 단계와, 상기 구조물들과 상부에 형성될 금속전극을 절연시키기 위한 제 1 절연막을 형성하는 단계와, 상기 베이스 영역 및 에미터 영역과 상기 금속전극을 연결하기 위한 접촉부를 형성하는 단계와, 상기 접촉부와 연결되는 금속전극을 형성하는 단계와, 상기 금속전극 형성 후 결과물 전면에 상기 금속전극을 포함한 반도체 기판의 상부 구조물들을 보호하기 위한 보호막을 형성하는 단계와, 상기 바이폴라 트랜지스터가 형성되지 않은 반도체 기판의 이면 중 상기 바이폴라 트랜지스터에 대응되는 면을 제외한 일부영역을 소정깊이로 식각하는 단계를 포함하여 이루어지는 것을 특징으로 한다.The pressure sensor manufacturing method of the present invention for achieving the above object, in the method of manufacturing a pressure sensor having a bipolar transistor, forming a device isolation region on the semiconductor substrate to define the device isolation region and the device formation region, Forming a base region and an emitter region of the bipolar transistor in the device formation region, forming a first insulating layer for insulating the structures and a metal electrode to be formed on the upper portion, and forming the base region and the emitter Forming a contact portion for connecting a region to the metal electrode, forming a metal electrode connected to the contact portion, and protecting the upper structures of the semiconductor substrate including the metal electrode on the entire surface of the resultant after forming the metal electrode; Forming a passivation layer for the passivation and the peninsula on which the bipolar transistor is not formed And etching a portion of the back surface of the body substrate except for the surface corresponding to the bipolar transistor to a predetermined depth.
도 1a 내지 도 1c는 종래의 기술에 의한 압력센서의 제조방법을 도시한 순서도들이고,1A to 1C are flowcharts illustrating a method of manufacturing a pressure sensor according to the related art.
도 2a 및 도 2c 는 본 발명에 의한 압력센서의 제조방법을 도시한 순서도들이다.2A and 2C are flowcharts illustrating a method of manufacturing a pressure sensor according to the present invention.
*도면의 주요 부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *
51 : 반도체 기판 52 : 매립층51 semiconductor substrate 52 buried layer
53 : 에피텍셜층 54 : 소자분리영역53 epitaxial layer 54 device isolation region
55 : 베이스 영역 56 : 에미터 영역55: base area 56: emitter area
57 : 제 1 산화막 58 : 제 2 산화막57: first oxide film 58: second oxide film
59 : 제 1 절연막 60 : 제 2 절연막59: first insulating film 60: second insulating film
61 : 금속층 62 : 보호막61 metal layer 62 protective film
63 : 제 3 절연막63: third insulating film
이하, 첨부한 도면을 참조하여 본 발명을 상세하게 설명하고자 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
도 2a 는 통상적인 방법으로 바이폴라의 에미터 영역을 형성한 상태를 도시한 것으로, 먼저 반도체기판(51)의 도전형(제 1 도전형)과 다른 도전형(제 2 도전형)의 물질로 매립층(52)을 형성한 후 상기 매립층(52)과 동일한 제 2 도전형 에피텍셜층(53)을 형성하며, 다시 상기 제 1 도전형의 물질을 상기 에피텍셜층(53)에 선택적으로 확산시켜 소자분리영역(54)을 형성함으로써 소자형성영역과 소자분리영역을 정의한다.FIG. 2A illustrates a state in which an emitter region of a bipolar is formed by a conventional method. First, a buried layer is formed of a material of a conductive type (first conductive type) different from that of the semiconductor substrate 51. After forming 52, a second conductive epitaxial layer 53 identical to the buried layer 52 is formed, and the first conductive material is selectively diffused into the epitaxial layer 53. The isolation region 54 is formed to define the device formation region and the isolation region.
이어서 상기 결과물 전면에 실리콘 열산화공정을 이용하여 제 1 산화막(57)을 형성한 후 선택적으로 사진식각하고 이를 마스크로 하여 상기 에피텍셜층(53) 내에 제 1 도전형 물질을 확산시켜 베이스 영역(55)를 형성하며, 다시 상기 결과물 전면에 실리콘 열산화 공정을 이용한 제 2 산화막(58)과 실리콘 CVD 공정을 이용한 제 1 절연막(59)을 순차적층시킨 후 선택적으로 이 두 층을 사진식각하고 이를 마스크로 하여 상기 베이스 영역(55) 내에 제 2 도전형의 물질을 확산시켜 에미터 영역(56)을 형성한다.Subsequently, after the first oxide film 57 is formed on the entire surface of the resultant by using a silicon thermal oxidation process, the first oxide film 57 is selectively etched, and the first conductive material is diffused into the epitaxial layer 53 using the mask as a base region. 55), the second oxide film 58 using the silicon thermal oxidation process and the first insulating film 59 using the silicon CVD process are sequentially formed on the entire surface of the resultant, and then the two layers are selectively etched and The emitter region 56 is formed by diffusing a second conductivity type material into the base region 55 using a mask.
이어서, 상기 에미터 영역(56)이 형성된 결과물 전면에 절연물질로서 예를들면 PSG(Phospho Silicated Glass) 또는 CVD(Chemical Vapor deposition) 실리콘산화물을 침전(deposition)시켜 제 2 절연막(60)을 형성한다.Subsequently, a second insulating film 60 is formed by depositing, for example, PSG (Phospho Silicated Glass) or CVD (Chemical Vapor Deposition) silicon oxide as an insulating material on the entire surface of the resultant product in which the emitter region 56 is formed. .
도 2b 에서는, 금속전극 마스크 패턴을 이용한 사진식각방법으로 상기 제 1, 제 2 산화막(57,58), 제 1, 제 2 절연막(59,60)을 반응성 이온식각하여 접촉부를 형성하고, 상기 접촉부가 형성된 결과물 전면에 금속물질로서 예를들면 알루미늄을 소정의 두께로 침전시켜 금속층(61)을 형성하며 이를 사진식각법으로 식각하여 금속전극을 형성한다.In FIG. 2B, the first and second oxide layers 57 and 58 and the first and second insulating layers 59 and 60 are reactively ion-etched to form a contact portion by a photolithography method using a metal electrode mask pattern. As a metal material on the entire surface of the resultant formed, for example, aluminum is precipitated to a predetermined thickness to form a metal layer 61, which is etched by photolithography to form a metal electrode.
이어서 후속공정시 반도체 기판의 모든 구조물들을 보호하기 위해 상기 금속전극이 형성된 결과물의 전,후면에 상기 금속층(61)보다 낮은 온도에서 형성할 수 있는 절연물질로서 예를들면 PECVD(Plasma Etched CVD) 실리콘 나이트라이드를 소정의 두께로 침전시켜 상기 반도체 기판 상부구조물의 전면에는 보호막(62)을 형성하고 상기 반도체 기판 이면에는 제 3 절연막(63)을 형성한다. 이때 상기 보호막(62)은 다른 구조물들뿐만 아니라 상기 금속전극도 함께 보호하게 되므로 종래와 같이 상기 금속전극을 보호하기 위한 별도의 전극보호막이 필요없다.Subsequently, in order to protect all the structures of the semiconductor substrate in a subsequent process, an insulating material that can be formed at a lower temperature than the metal layer 61 on the front and rear surfaces of the resultant metal electrode, for example, PECVD (Plasma Etched CVD) silicon. Nitride is deposited to a predetermined thickness to form a protective film 62 on the front surface of the upper structure of the semiconductor substrate, and to form a third insulating film 63 on the back surface of the semiconductor substrate. In this case, since the protective layer 62 protects the metal electrode as well as other structures, a separate electrode protective layer for protecting the metal electrode is not required as in the related art.
도 2c 에서는, 반도체 기판 이면의 상기 제 3 절연막을 사진식각공정을 이용하여 선택적으로 식각하고, 이를 마스크로 적용하여 다시 상기 반도체 기판(51)을 식각한 후 상기 제 3 절연막을 제거한다.In FIG. 2C, the third insulating film on the back surface of the semiconductor substrate is selectively etched using a photolithography process, and the third insulating film is removed by etching the semiconductor substrate 51 by applying it as a mask.
더 상세하게는, 상기 바이폴라 트랜지스터에 대응되는 면을 제외한 반도체 기판의 이면을 남은 부분이 약 20 마이크로미터(
이상에서와 같이 본 발명에 의하면, 상기 반도체 기판의 이면 식각에 앞서 접촉부와 금속전극을 먼저 형성함으로써 웨이퍼의 파손을 막아 수율을 향상시킬 수 있으며, 또한 상기 보호막이 상기 반도체 기판의 이면 식각시 상기 금속전극을 포함한 상부구조물들 보호함으로써 종래와 같은 별도의 전극보호막을 형성할 필요가 없기 때문에 공정시간을 단축할 수 있는 효과가 있다.As described above, according to the present invention, by forming the contact portion and the metal electrode first before the back surface etching of the semiconductor substrate, it is possible to improve the yield by preventing the breakage of the wafer, and the protective film is the metal during the back surface etching of the semiconductor substrate. By protecting the upper structures including the electrode there is no need to form a separate electrode protective film as in the prior art has the effect of reducing the process time.
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