CA1271270A - Method of manufacturing a semiconductor device, in which a metallization with a thick connection electrode is provided on a semiconductor body - Google Patents

Method of manufacturing a semiconductor device, in which a metallization with a thick connection electrode is provided on a semiconductor body

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Publication number
CA1271270A
CA1271270A CA000526962A CA526962A CA1271270A CA 1271270 A CA1271270 A CA 1271270A CA 000526962 A CA000526962 A CA 000526962A CA 526962 A CA526962 A CA 526962A CA 1271270 A CA1271270 A CA 1271270A
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Prior art keywords
connection electrode
layer
metallization
metal layer
metal
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Expired - Lifetime
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CA000526962A
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French (fr)
Inventor
Johannes S. Peters
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Koninklijke Philips NV
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Philips Gloeilampenfabrieken NV
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00013—Fully indexed content
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01022—Titanium [Ti]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01024—Chromium [Cr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01057—Lanthanum [La]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
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    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1203—Rectifying Diode
    • H01L2924/12035—Zener diode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Abstract

ABSTRACT:
Method of manufacturing a semiconductor device, in which a metallization with a thick connection electrode is provided on a semiconductor body.

A method of manufacturing a semiconductor device comprising a semiconductor body (1), of which a surface (13) is provided with a metallization (15,16,17,18) with a thick connection electrode (19). The metallization is formed in a first metal layer (49) and the connection electrode is formed in a second metal layer (51). Between these metal layers is provided a third metal layer (50), which serves as an etching stopper during the formation of the connection electrode. During a single deposition step, the three metal layers (49,50,51) are provided, after which first the connection electrode and then the metallization are formed by etching. By providing the three metal layers in a single deposition step, the number of processing steps for manufacturing the semiconductor device is limited and it is moreover achieved that the adhesion between connection electrode (19) and metallization (15,16,17,18) is an optimum.

Description

~71~7() 1 20104-8~0 "Method of manufacturlng a semiconductor device, in which a metallization with a thick connection electrode is provided on a semiconductor body."
The invention relate to a method of manufacturing a semiconductor device comprising a semiconductor body, one surface æO ~o ~C,c~
of which is provided with a metallization with a~thick connection electrode and an insula~ing layer coveriny the metalliza~ion except at the area of the connection electrode, thè metallization being formed in a first me~al layer and the connection electrode being formed in a second me~al layer by etchiny, while a third metal layer is provided between these metal layers, which can serve as an e~ching stopper during the formation of the connection electrode.
Such a method is particularly suitable for the manufacture of semiconductor devices, the semiconductor body of which is clamped within a fused glass envelope between two electrodes. One of these two electrodes is in contact with the connection electrode present on ~he surface, whlle the other electrode ls in contact with the side o~ the semiconductor body 2Q remote from thl~ surface.
The German Offenlegungsschrift No. 2428373, lald open January 2, 1976, discloses a method of the kind mentioned in the openiny parayraph, in which, after the first metal layer has been provided on the surface of the semiconductor body and khe metallization has been formed therein, a layer of insulatlng material is deposited over the whole surface. At the area at which the metallization has to be provided with the thick connection electrode, a window is etched into the insulating ` ~

'7~

la 20104-8210 layer, after whieh the third and the second metal layer are successively provided over the whole surface. The connection electrode is formed in this double metal layer.
The known method described has the disadvantage tha~ it can be carried out only with the aid of a comparatively large number of processing steps. Moreover, ~ ~ ~t7~

P~N 11 602 -2- 2-10-~986 it has been found that the adhesion between metallization and connection electrode sometimes leaves much to be desired.
The invention has inter alia for its object to provide a method in which it is possible to manufacture a semiconductor device comprising a semiconductor body which is provided with a metallization with a thick connection electrode with the aid of a comparatively small number of processing steps, the adhesion between metallization and con-nection electrode being an optimum.
For this purpose, according to the invention, the method mentioned in the opening paragraph is character-ized in that during a single deposition step the first, the third and the second metal layers are successively pro-vided on the surface of the semiconductor body, after which first the connection electrode and then the metallization are formed, whereupon the insulating layer is provided, into which a window is etched at the area of the connection electrode. Since the third and second metal layers are pro-vided in the same deposition step as the first metal layer, it is avoided that oxides or residues of etchants are pre-sent between the metal layers. The adhesion between the layers is an optimum.
The number of processing steps is essentially limited by the use of the invention because all metal layers - i.e. in order of sucession the first, third and second metal layers - are provided in a single deposition step.
Subsequently, a first etching mask is provided on these layers, whereupon uncovered layers are etched away from the second layer down to the third metal layer. The third layer serves as an etching stopper when etching the second layer. Subsequently, a second etching mask is provided, after which uncovered parts of the third and first metal layers are etched away. Finally, the insulating layer is provided, into which a window is etched at the area of the connection electrode.
During the formation of the metallization and the connection electrode, first the connection electrode is formed, after which the remaining part of the metallization 71~

PHN 11 602 -3- 2-10-19~6 is formed. This has the advantage that this remaining part of the metallization is etched in a comparatively thin metal layer (in practice 3 to 6 /um). As a result, fine details can be realized in this part of the metallization. If the patterns of the whole metallization should be formed first in all layers, the realization of thin details would be extremely diEficult because the second layer is comparatively thick (in practice 30 to 60 /um).
The invention will now be described more fully, by way of example, with reference to a drawing.
Inthe drawing:
Fig. 1 shows diagrammatically in plan view a semiconductor device manufactured by means of the method according to the invention, Fig. 2 is a diagrammatic sectional view of the device shown in Fig. 1 taken on the line II-II, Fig. 3 shows diagrammatically a glass envelope accommodating a semiconductor device of the type shown in Figures 1 and 2, and Figures 4, 5 and 6 show d-iagrammatically successi-ve stages in the manufacture of the semiconductor device shown in Figures 1 and 2 by means of the method according to the invention.
The Figures are schematic and not drawn to scale, while for the sake of clarity more particularly the dimen-sions in the direction of thickness in the cross-sections are greatly exaggerated. In the Figures, corresponding parts are denoted by the same reference numerals.
The method according to the invention is particular-ly suitable for the manufacture of a semiconductor deviceof a kind as shown in Figures 1 and 2. This semiconductor device comprises a semiconductor body 1 comprising three bipolar transistors having a common n-type collector zone 2 having a dopingcorcentration of about 1014 atoms/cm3 and a thickness of about 90 /um. The collector zone 2 is connect-ed by means of an n-type zone having a comparatively high doping concentration of about 102 atoms/cm3 and a thickness of about 7 /um to a metal electrode layer 4. The . .

~7~ 7~

semiconductor body 1 further has three ~-type base zones 5, 6 and 7 and a ~-type separation zone 8 having a thickness of about 30 /um and a doping concentration of about 1018 atoms/cm3. Finally, the semiconductor body 1 has three n-type emitter -zones 9, 10 and 11 and a connection zone 12 having a thickness of about 7 /um and a doping concentration of about 102 atoms/cm3. The base zone 5 and the emitter zone 9 constitute with the common collector zone 2 a first transistor (5, 9), while the base zone 6 and the emitter zone 10 constitute with this collector zone a second transistor (6,10) and the base æone 7 and the emitter zone 11 constitute with this collector zone a third transistor (7,11)~
The surface 13 of the semiconductor body 1 is provided with an insulating layer 14 of silicon oxide and a metallization consisting in this case of four parts. All parts consist of a substrate layer of titanium and a top layer of silver; for the sake of clarity, however, the parts are designated only by a single reference numeral. A first part 15 connects the contact zone 12 (and hence the common collector zone 2) to the base 5 of the first transistor (5,9), while a second part 16 connects the emitter 9 of the first transistor (5,9) to the base 6 of the second transis-tor (6,10) and a third part 17 connects the emitter 10 of the second transistor (6,10) to the base 7 of the third transistor (7,11) and the fourth part 18 connects the emitter of the fourth transistor (7, 11) to a thick con-nection electrode 19. This connection electrode 19 also comprises a substrate layer of titanium and a top layer of silver. The whole surface 13 of the semiconductor body is finally covered with an insulating layer 20 of silicon nitride, which covers the metallization 15,16,17 and 18 except at the area of the connection electrode 19.
Fig. 3 shows diagrammatically how the device shown in Figures 1 and 2 can be mounted in a glass envelope ',0.
The semiconductor body 1 is arranged for this purpose with its metal electrode layer 4 and the thick connection elec-trode 19 between two electrodes 31 and 32, after which a soft glass tube is slipped over the whole. The whole is then heated to a temperature of about 700C, whereupon after cooling the glass envelope 30 is formed, which adheres satisfactorily to the electrodes 31 and 32. Due to shrinkage stresses producedin the glass upon cooling, the semiconductor body is clamped between the electrodes. Thus, in this embodiment, an integrated circuit is present between the elec(trodes 31 and 32, which integrated circuit comprises three series-connected diodes, which are constituted by three series-connected base-emitter junc~ons . Such a circuit can be used as a voltage stabilizer.
Figures 4, 5 and 6 show successive stages of the manufacture of the semiconductor device shown in Figures 1 and 2. The metallization with the parts 15, 16, 17 and 18 is then formed in a first metal layer and the con-nection electrode 19 is formed in a second metal layer by etching, while a third metal layer is provided between these metal layers and can serve as an etching stopper during the formation of the connection electrode 19.
The starting material is a semiconductor body 1/
in which the various semiconductor zones 5, 6, 7, 8, 9, 10, 11 and 12 are provided in a usual manner and whose surface 13 is provided with the insulating layer 14 with windows 41, 42 and 43 for contacting the base zones 5, 6 and 7, 25 with windows 44, 45 and 46 for contacting the emitter zones 9, 10 and 11 and with a window 47 for contacting the connectan zone 12. The separation zone 8 is not connected to the metallization in this embodiment.
A titanium layer 48 having a thickness of about 30 0,1 /um, a silver layer 49 having a thickness of about 4 um, a titanium layer 50 having a thickness of about 0.2 /um and a thick silver layer 51 having a thickness of about 50 /um are now deposited in a single deposition step on the whole surface 13 of the semiconductor body 1. The ti-tanium layer 48 serves as an adhesive layer between the silver layer 49 and the semiconductor zones 5,6,7,8,9,10, 11 and 12 and the insulating layer 14. Although the ti-tanium layer 48 is of great advantage for the operation of ~7~

PHN 11 602 -6~ 2-10-1986 the semiconductor device, it is essential for the formation of the metallizations 15,16,17 and 18 with the connection electrode 19 by means of the method according to the in-vention that during the single deposition step the layers 49, 50 and 51 are formed. The metallizations 15, 16, 17 and 18 are formed in the silver layer 49, referred to herein-.before as the first metal layer, while the connection electrode 19 is formed in the silver layer 51, referred to hereinbefore as the second metal layer. During the formation of the connection electrode 19, the titanium layer 50, re-ferred to hereinbefore as the third metal layer, serves as an etching stopper.
According to the invention, after a photolacquer mask 52 has been provided in a usual manner, first the con-nection electrode 19 is formed by etching away the partsof the silver layer 51 not covered by the photolacquer mask 52. The silver may be etched, for example, in a solution (1 : 1) of nitric acid and ferronitrate. The titanium layer 50, which is practically not attacked by the said etching baths, then serves as an etching stopper. After a next photolacquer mask 53 has been provided in a usual manner, parts of the titanium layer 50 not covered by this mask are etched away in a mixture of nitric acid and hydro-fluoride. Subsequently, the non-covered parts of the silver layer 49 and the titanium layer 48 are successively etched away. Thus, the parts of the metallizations 15,16,17 and 18 are formed. Finally, the whole is covered in a usual manner by a silicon nitride layer 54, of which, after a photo-lacquer mask 55 has been provided in a usual manner, parts not covered by this mask are etched away. Thus, the semi-conductor device shown in Figures 1 and 2 is manufactured.
Since the metal layers essential to the metalli-zations 15,16,17 and 18 and the connection electrode 19 ~
i.e. in order of succession the first layer 49, the third layer 50 and the second layer 51 - are provided in a single deposition step, the number of processing steps for the manufacture of the semiconductor device shown in Figures 1 and 2 is limited. During the formation of the .7~

metallization parts 15,16,17 and 18, the etching treatment is carried out in a comparatively thin layer so that com-paratively fine details can be formed. This would not be the case if during the first etching treatment a pattern corresponding to the metallization parts 15,16,17 and 18 were etched in all the layers 49, 50 and 51 and only then the thick layer 51 were removed from the parts 15,16,17 and 18.
Since the metal layers 48,49,50 and 51 are provided in a single deposition step, It is avoided that oxides or l~ residues of etchants are present between the metal layers.
The adhesion between the layers is therefore an optimum.
During the single deposition step, preferably a first metal layer 49 of silver, a third metal layer 50 of titanium and a second metal layer 51 of silver are pro-vided. Such a choice is particularly practical if thesemiconductor device has to be accommodated in an envelope as shown in Fig. 3. In such a case, the whole semiconductor device is heated to a temperature of about 700C, the semiconductor device being capable of withstanding this heating step without any problem, Although the said metals are to be preferred, other choices are possible. For example, the first metal layer may alternatively consist of tungsten, platinum or a silicide, such as platinum silicide, while the third metal layer may alternatively consist oE chromium and the second metal layer of copper.
As described already ahove, it is also of great advantage if during the deposition step before providing the first metal layer 49, the third metal layer 50 and the second metal layer 51 a metal adhesive layer 48 is providedO
Preferably, the latter layer consists of titanium for the same reasons as described hereinbefore for the other metal layers 49, 50 and 51. A very suitable thickness for the adhesive layer is 0,05 to 0,15 /um.
Preferably, the first metal layer of silver is provided in a thickness of 3 to 6 /um, the third metal layer of titanium 50 is provided in a thickness of 0,1 to 0,3 /um and the second metal layer of silver 51 is pro-vided in a thickness of 20 to 50 /um.

P~N 11 602 -~- 2-10-1986 It will be appreciated that the invention is not limited to the embodiment described, but that many modi-fications are possible for a person skilled in the art without departing from the scope of the invention. For example, instead of three transistors/ the device may also comprise a single diode or Zener diode, the first metal layer then forming an ohmic contact with the semiconductor body. Furthermore, the metallization may be provided with more than one connection electrode.

. ,.,,, , . ~

Claims (6)

THE EMBODIMENTS OF THE INVENTION IN WHICH AN EXCLUSIVE
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
1. A method of manufacturing a semiconductor device comprising a semiconductor body, of which a surface is provided with a metallization with a 20 to 50 µm connection electrode, and an insulating layer covering the metallization except at the area of the connection electrode, the metallization being formed in a first metal layer and the connection electrode being formed in a second metal layer by etching, while a third metal layer is provided between these metal layers, which can serve as an etching stopper during the formation of the connection electrode, characterized in that during a single deposition step the first, the third and the second metal layers are successively provided on the surface of the semiconductor body, after which the first connection electrode and then the metallization are formed, whereupon the insulating layer is provided, into which a window is etched at the area of the connection electrode.
2. A method as claimed in Claim 1, characterized in that during the deposition step a first metal layer of silver, a third metal layer of titanium and a second metal layer of silver are provided.
3. A method as claimed in Claim 1 characterized in that during the deposition step, before the first, the third and the second metal layers are provided, a metal adhesive layer is provided.
4. A method as claimed in Claim 3, characterized in that an adhesive layer having a thickness of 50 to 150 µm is provided.
5. A method as claimed in Claim 2, characterized in that the first metal layer of silver is provided in a thickness of 3 to
6 µm, the third metal layer of titanium is provided in a thickness of 0.1 to 0.3 µm and the second metal layer of silver is provided in a thickness of 20 to 50 µm.
CA000526962A 1986-01-08 1987-01-08 Method of manufacturing a semiconductor device, in which a metallization with a thick connection electrode is provided on a semiconductor body Expired - Lifetime CA1271270A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
NL8600021 1986-01-08
NL8600021A NL8600021A (en) 1986-01-08 1986-01-08 METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE APPLYING METALIZATION TO A SEMICONDUCTOR BODY

Publications (1)

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CA1271270A true CA1271270A (en) 1990-07-03

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US (1) US4789647A (en)
EP (1) EP0229426B1 (en)
JP (1) JPS62160763A (en)
CA (1) CA1271270A (en)
DE (1) DE3678135D1 (en)
NL (1) NL8600021A (en)

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US4789647A (en) 1988-12-06
JPS62160763A (en) 1987-07-16
EP0229426A1 (en) 1987-07-22
EP0229426B1 (en) 1991-03-13
NL8600021A (en) 1987-08-03
DE3678135D1 (en) 1991-04-18

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