KR19990084847A - Manufacturing Method of Semiconductor Device - Google Patents
Manufacturing Method of Semiconductor Device Download PDFInfo
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- KR19990084847A KR19990084847A KR1019980016907A KR19980016907A KR19990084847A KR 19990084847 A KR19990084847 A KR 19990084847A KR 1019980016907 A KR1019980016907 A KR 1019980016907A KR 19980016907 A KR19980016907 A KR 19980016907A KR 19990084847 A KR19990084847 A KR 19990084847A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 18
- 239000004065 semiconductor Substances 0.000 title claims abstract description 15
- 238000002955 isolation Methods 0.000 claims abstract description 11
- 238000005530 etching Methods 0.000 claims abstract description 9
- 150000002500 ions Chemical class 0.000 claims abstract description 8
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 238000000034 method Methods 0.000 claims description 24
- 229920002120 photoresistant polymer Polymers 0.000 description 20
- 238000000206 photolithography Methods 0.000 description 7
- 230000003647 oxidation Effects 0.000 description 5
- 238000007254 oxidation reaction Methods 0.000 description 5
- 230000015556 catabolic process Effects 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823857—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
본 발명은 LDNMOS영역의 LDPMOS 게이트 산화막을 잔존층이 남도록 선택 식각하여 필드 산화막의 티닝 현상을 방지하므로 소자의 전기적 특성 및 신뢰성을 향상시키기 위한 반도체 소자의 제조 방법에 관한 것이다.The present invention relates to a method of fabricating a semiconductor device for improving the electrical characteristics and reliability of the device since the etching of the LDPMOS gate oxide film in the LDNMOS region so as to leave the remaining layer to prevent the tinning of the field oxide film.
본 발명의 반도체 소자의 제조 방법은 고전압MOS영역과 저전압MOS영역이 정의된 제 1 도전형 기판을 준비하는 단계, 상기 기판상에 제 2 도전형 웰과 고농도 제 1, 제 2 도전형 웰 및 제 1, 제 2 도전형 표류층 그리고 다수개의 격리막을 포함한 제 1 도전형 에피택셜층을 형성하는 단계, 상기 격리막들을 포함한 전면에 상기 고전압MOS의 제 1 게이트 절연막을 성장시키는 단계, 상기 격리막들이 식각되지 않도록 상기 저전압MOS영역의 제 1 게이트 절연막의 상부부위를 식각하는 단계, 상기 저전압MOS의 채널영역에 채널이온을 주입하는 단계, 상기 저전압MOS영역의 제 1 게이트 절연막을 제거하는 단계와, 상기 노출된 에피택셜층상에 상기 제 1 게이트 절연막보다 두께가 낮은 저전압MOS의 제 2 게이트 절연막을 성장시키는 단계를 포함하여 이루어짐을 특징으로 한다.The method of manufacturing a semiconductor device of the present invention comprises the steps of preparing a first conductivity type substrate having a high voltage MOS region and a low voltage MOS region, a second conductivity type well and high concentration first, second conductivity type well and Forming a first conductivity type epitaxial layer including a first conductivity type drift layer and a plurality of isolation layers, growing a first gate insulating layer of the high voltage MOS on the entire surface including the isolation layers, wherein the isolation layers are not etched. Etching an upper portion of the first gate insulating layer of the low voltage MOS region, implanting channel ions into the channel region of the low voltage MOS region, removing the first gate insulating layer of the low voltage MOS region, And growing a second gate insulating film of a low voltage MOS having a thickness lower than that of the first gate insulating film on the epitaxial layer. All.
Description
본 발명은 반도체 소자의 제조 방법에 관한 것으로, 특히 소자의 전기적 특성 및 신뢰성을 향상시키는 반도체 소자의 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device for improving electrical characteristics and reliability of the device.
일반적으로 LDMOS(Lateral double diffusion MOS)에서 고전압MOS인 LDPMOS의 게이트에는 약100V의 고전압이 인가되고 저전압MOS인 LDNMOS의 게이트에는 약5V의 저전압이 인가되므로, 상기 LDPMOS는 약2000Å두께의 게이트 산화막이 필요하고 상기 LDNMOS는 약200Å두께의 게이트 산화막이 필요하다.In general, a high voltage of about 100 V is applied to a gate of an LDPMOS, which is a high voltage MOS, and a low voltage of about 5 V is applied to a gate of an LDNMOS, which is a low voltage MOS in an LDMOS. In addition, the LDNMOS requires a gate oxide film having a thickness of about 200 kHz.
도 1a 내지 도 1g는 종래 기술에 따른 LDMOS의 제조 방법을 나타낸 공정 단면도이다.1A to 1G are cross-sectional views illustrating a method of manufacturing an LDMOS according to the prior art.
종래 기술에 따른 LDMOS의 제조 방법은 도 1a에서와 같이, LDPMOS영역과 LDNMOS영역이 정의되며 p형인 반도체 기판(11)상에 n형 웰(13), p형 표류층(14), n형 표류층(15), 고농도 n형 웰(16)과, 고농도 p형 웰(17) 그리고 격리영역에 다수개의 필드 산화막(18)이 형성된 p형 에피택셜(Epitaxial)층(12)을 형성한다.In the conventional LDMOS manufacturing method, as shown in FIG. 1A, an n-type well 13, a p-type drifting layer 14, and an n-type drifting are defined on a p-type semiconductor substrate 11 in which an LDPMOS region and an LDNMOS region are defined. A p-type epitaxial layer 12 in which a layer 15, a high concentration n-type well 16, a high concentration p-type well 17, and a plurality of field oxide films 18 are formed in an isolation region is formed.
여기서, 상기 필드 산화막(18)들을 일반적인 로코스(LOCOS) 공정으로 형성하며, 일반적인 감광막의 선택 사진 식각공정들과 이온 주입공정들 그리고 드라이브-인(Drive-in) 확산 공정들에 의해 상기 n형 웰(13)은 상기 p형 에피택셜층(12) 표면내의 일정영역에 형성된다.Here, the field oxide layers 18 are formed by a general LOCOS process, and the n-type is formed by selective photolithography processes, ion implantation processes, and drive-in diffusion processes of the general photoresist layer. The well 13 is formed in a predetermined region within the surface of the p-type epitaxial layer 12.
그리고, 상기 p형 표류층(14)은 상기 n형 웰(13) 표면내의 일정영역에 형성되고, 상기 n형 표류층(15)은 상기 n형 웰(13) 일측의 에피택셜층(12) 표면내의 일정영역에 형성되며 그리고 상기 고농도 n형 웰(16)은 상기 p형 표류층(14) 일측의 n형 웰(13) 표면내에 형성되고, 상기 고농도 p형 웰(17)은 상기 n형 표류층(15) 일측의 에피택셜층(12) 표면내에 형성된다.The p-type drifting layer 14 is formed in a predetermined region within the surface of the n-type well 13, and the n-type drifting layer 15 is an epitaxial layer 12 on one side of the n-type well 13. The high concentration n-type well 16 is formed in the surface of the n-type well 13 on one side of the p-type drift layer 14, and the high concentration p-type well 17 is formed in the n-type well. It is formed in the surface of the epitaxial layer 12 on one side of the drift layer 15.
또한, 상기 p형 표류층(14)과 고농도 n형 웰(16)의 LDPMOS 채널영역에 채널이온이 주입된 상태이다.In addition, channel ions are implanted into the LDPMOS channel region of the p-type drifting layer 14 and the highly concentrated n-type well 16.
도 1b에서와 같이, 전면의 열산화 공정으로 상기 노출된 에피택셜층(12)상에 1900 ~ 2100Å두께의 제 1 산화막(19)을 성장시킨다.As shown in FIG. 1B, a first oxide film 19 having a thickness of 1900 to 2100 μs is grown on the exposed epitaxial layer 12 by a thermal oxidation process on the entire surface.
도 1c에서와 같이, 상기 제 1 산화막(19)을 포함한 전면에 제 1 감광막(20)을 도포하고, 상기 제 1 감광막(20)을 선택 사진 식각 공정으로 상기 n형 웰(13) 상측에만 남도록 선택적으로 노광 및 현상한다.As shown in FIG. 1C, the first photoresist film 20 is coated on the entire surface including the first oxide film 19, and the first photoresist film 20 is left only above the n-type well 13 by a selective photolithography process. And optionally exposure and development.
그리고, 상기 선택적으로 노광 및 현상된 제 1 감광막(20)을 마스크로 상기 제 1 산화막(19)을 선택적으로 식각하여 상기 LDPMOS의 게이트 산화막을 형성한다.The first oxide film 19 is selectively etched using the selectively exposed and developed first photoresist film 20 to form a gate oxide film of the LDPMOS.
여기서, 상기 1900 ~ 2100Å두께의 제 1 산화막(19)을 식각하기 위하여 3000Å정도 두께의 산화막이 식각될 수 있는 식각량을 사용하므로 즉 오버 에치(Over Etch)하므로 상기 제 1 산화막(19)의 식각에 의해 상기 LDNMOS영역의 필드 산화막(18)도 영향을 받아 약간 식각된다. 특히 상기 필드 산화막(18)의 가장자리부위가 많이 식각된다.In order to etch the first oxide film 19 having a thickness of 1900 to 2100 μs, an etching amount capable of etching an oxide film having a thickness of about 3000 μs is used, that is, over etched, so that the first oxide film 19 is etched. As a result, the field oxide film 18 in the LDNMOS region is also affected and slightly etched. In particular, the edge portion of the field oxide film 18 is etched a lot.
도 1d에서와 같이, 상기 제 1 감광막(20)을 제거한 후, 전면의 열산화 공정으로 상기 노출된 에피택셜층(12)상에 190 ~ 210Å두께의 제 2 산화막(21)을 성장시킨다.As shown in FIG. 1D, after the first photosensitive film 20 is removed, a second oxide film 21 having a thickness of 190 to 210 μm is grown on the exposed epitaxial layer 12 by thermal oxidation of the entire surface.
도 1e에서와 같이, 상기 제 2 산화막(21)을 포함한 전면에 제 2 감광막(22)을 도포하고, 상기 제 2 감광막(22)을 상기 LDNMOS의 채널영역 상측에만 제거되도록 선택 사진 식각한다.As shown in FIG. 1E, the second photoresist layer 22 is coated on the entire surface including the second oxide layer 21, and the second photoresist layer 22 is selectively etched to remove only the channel region of the LDNMOS.
그리고, 상기 선택 사진 식각된 제 2 감광막(22)을 마스크로 전면에 BF2 +이온(23)을 80KeV의 에너지와 6.0E12㎝-2의 농도로 주입한다.Then, the BF 2 + ions 23 are implanted at a concentration of 6.0 Ke12cm −2 and an energy of 80 KeV on the entire surface of the selective photo-etched second photosensitive film 22.
도 1f에서와 같이, 상기 제 2 감광막(22)을 제거한 다음, 전면에 제 3 감광막(24)을 도포하고, 상기 제 3 감광막(24)을 상기 n형 웰(13) 상측에만 남도록 선택 사진 식각 공정 한다.As shown in FIG. 1F, after the second photoresist layer 22 is removed, a third photoresist layer 24 is applied to the entire surface, and the selected photolithography is performed such that the third photoresist layer 24 remains only above the n-type well 13. Fair.
그리고, 상기 선택 사진 식각 공정된 제 3 감광막(24)을 마스크로 상기 제 2 산화막(21)을 제거한다.Then, the second oxide film 21 is removed using the third photosensitive film 24 subjected to the selective photolithography process.
도 1g에서와 같이, 상기 제 3 감광막(24)을 제거하고, 전면의 열산화 공정으로 상기 노출된 에피택셜층(12)상에 190 ~ 210Å두께의 제 3 산화막(25)을 성장시킨다.As shown in FIG. 1G, the third photoresist layer 24 is removed, and a third oxide layer 25 having a thickness of 190 to 210 μm is grown on the exposed epitaxial layer 12 by thermal oxidation of the entire surface.
여기서, 상기 제 3 산화막(25)의 성장으로 상기 LDNMOS의 게이트 산화막을 형성한다.Here, the gate oxide film of the LDNMOS is formed by growing the third oxide film 25.
상기와 같은 공정들을 포함하여 후공정들에 의해 LDPMOS와 LDNMOS를 형성한다.Including the above processes, LDPMOS and LDNMOS are formed by post-processes.
그러나 종래의 반도체 소자의 제조 방법은 LDPMOS 게이트 산화막을 형성하기 위한 산화막의 선택 오버 에치시 LDNMOS영역의 필드 산화막도 영향을 받아 식각되므로 특히 필드 산화막의 가장자리부위가 많이 식각되므로 필드 산화막의 티닝(Thinning)현상에 의해 소자의 항복전압이 감소하여 소자의 전기적 특성 및 신뢰성을 저하시키는 문제점이 있었다.However, in the conventional method of manufacturing a semiconductor device, the field oxide film of the LDNMOS region is also etched during the selective over-etching of the oxide film for forming the LDPMOS gate oxide film. Due to the phenomenon, the breakdown voltage of the device is reduced, thereby degrading the electrical characteristics and reliability of the device.
본 발명은 상기의 문제점을 해결하기 위해 안출한 것으로 LDNMOS영역의 LDPMOS 게이트 산화막을 잔존층이 남도록 선택 식각하여 필드 산화막의 티닝 현상을 방지하므로 소자의 전기적 특성 및 신뢰성을 향상시키는 반도체 소자의 제조 방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and the method of manufacturing a semiconductor device improves the electrical characteristics and reliability of the device by selectively etching the LDPMOS gate oxide film of the LDNMOS region so that the remaining layer remains, thereby preventing the tinning of the field oxide film. The purpose is to provide.
도 1a 내지 도 1g는 종래 기술에 따른 LDMOS의 제조 방법을 나타낸 공정 단면도1A to 1G are cross-sectional views illustrating a method of manufacturing an LDMOS according to the prior art.
도 2a 내지 도 2f는 본 발명의 실시예에 따른 LDMOS의 제조 방법을 나타낸 공정 단면도2A to 2F are cross-sectional views illustrating a method of manufacturing an LDMOS according to an embodiment of the present invention.
도면의 주요부분에 대한 부호의 설명Explanation of symbols for main parts of the drawings
31: 반도체 기판 32: p형 에피택셜층31: semiconductor substrate 32: p-type epitaxial layer
33: n형 웰 34: p형 표류층33: n-type well 34: p-type drift layer
35: n형 표류층 36: 고농도 n형 웰35: n-type drift layer 36: High concentration n-type well
37: 고농도 p형 웰 38: 필드 산화막37: high concentration p-type well 38: field oxide film
39: 제 1 산화막 40: 제 1 감광막39: first oxide film 40: first photosensitive film
41: 제 2 감광막 42: BF2 +이온41: a second photosensitive film 42: BF 2 + ions
43: 제 3 감광막 44: 제 2 산화막43: third photosensitive film 44: second oxide film
본 발명의 반도체 소자의 제조 방법은 고전압MOS영역과 저전압MOS영역이 정의된 제 1 도전형 기판을 준비하는 단계, 상기 기판상에 제 2 도전형 웰과 고농도 제 1, 제 2 도전형 웰 및 제 1, 제 2 도전형 표류층 그리고 다수개의 격리막을 포함한 제 1 도전형 에피택셜층을 형성하는 단계, 상기 격리막들을 포함한 전면에 상기 고전압MOS의 제 1 게이트 절연막을 성장시키는 단계, 상기 격리막들이 식각되지 않도록 상기 저전압MOS영역의 제 1 게이트 절연막의 상부부위를 식각하는 단계, 상기 저전압MOS의 채널영역에 채널이온을 주입하는 단계, 상기 저전압MOS영역의 제 1 게이트 절연막을 제거하는 단계와, 상기 노출된 에피택셜층상에 상기 제 1 게이트 절연막보다 두께가 낮은 저전압MOS의 제 2 게이트 절연막을 성장시키는 단계를 포함하여 이루어짐을 특징으로 한다.The method of manufacturing a semiconductor device of the present invention comprises the steps of preparing a first conductivity type substrate having a high voltage MOS region and a low voltage MOS region, a second conductivity type well and high concentration first, second conductivity type well and Forming a first conductivity type epitaxial layer including a first conductivity type drift layer and a plurality of isolation layers, growing a first gate insulating layer of the high voltage MOS on the entire surface including the isolation layers, wherein the isolation layers are not etched. Etching an upper portion of the first gate insulating layer of the low voltage MOS region, implanting channel ions into the channel region of the low voltage MOS region, removing the first gate insulating layer of the low voltage MOS region, And growing a second gate insulating film of a low voltage MOS having a thickness lower than that of the first gate insulating film on the epitaxial layer. All.
상기와 같은 본 발명에 따른 반도체 소자의 제조 방법의 바람직한 실시예를 첨부된 도면을 참조하여 상세히 설명하면 다음과 같다.When described in detail with reference to the accompanying drawings a preferred embodiment of the method for manufacturing a semiconductor device according to the present invention as follows.
도 2a 내지 도 2f는 본 발명의 실시예에 따른 LDMOS의 제조 방법을 나타낸 공정 단면도이다.2A to 2F are cross-sectional views illustrating a method of manufacturing an LDMOS according to an exemplary embodiment of the present invention.
본 발명의 실시예에 따른 LDMOS의 제조 방법은 도 2a에서와 같이, LDPMOS영역과 LDNMOS영역이 정의되며 p형인 반도체 기판(31)상에 n형 웰(33), p형 표류층(34), n형 표류층(35), 고농도 n형 웰(36)과, 고농도 p형 웰(37) 그리고 격리영역에 다수개의 필드 산화막(38)이 형성된 p형 에피택셜층(32)을 형성한다.In the method of manufacturing an LDMOS according to an exemplary embodiment of the present invention, as shown in FIG. 2A, an n-type well 33, a p-type drifting layer 34, and a p-type semiconductor substrate 31 having an LDPMOS region and an LDNMOS region are defined. The n-type drifting layer 35, the high-concentration n-type well 36, the high-concentration p-type well 37, and the p-type epitaxial layer 32 having a plurality of field oxide films 38 formed in the isolation region are formed.
여기서, 상기 필드 산화막(38)들을 일반적인 로코스 공정으로 형성하며, 일반적인 감광막의 선택 사진 식각공정들과 이온 주입공정들 그리고 드라이브-인 확산 공정들에 의해 상기 n형 웰(33)은 상기 p형 에피택셜층(32) 표면내의 일정영역에 형성된다.Here, the field oxide layers 38 are formed by a general LOCOS process, and the n-type well 33 is formed by the p-type by selective photolithography processes, ion implantation processes, and drive-in diffusion processes. It is formed in a predetermined region within the epitaxial layer 32 surface.
그리고, 상기 p형 표류층(34)은 상기 n형 웰(33) 표면내의 일정영역에 형성되고, 상기 n형 표류층(35)은 상기 n형 웰(33) 일측의 에피택셜층(32) 표면내의 일정영역에 형성되며 그리고 상기 고농도 n형 웰(36)은 상기 p형 표류층(34) 일측의 n형 웰(33) 표면내에 형성되고, 상기 고농도 p형 웰(37)은 상기 n형 표류층(35) 일측의 에피택셜층(32) 표면내에 형성된다.The p-type drifting layer 34 is formed in a predetermined region within the surface of the n-type well 33, and the n-type drifting layer 35 is an epitaxial layer 32 on one side of the n-type well 33. The high concentration n-type well 36 is formed in the surface of the n-type well 33 on one side of the p-type drifting layer 34, and the high concentration p-type well 37 is formed in the n-type. It is formed in the surface of the epitaxial layer 32 on one side of the drift layer 35.
또한, 상기 p형 표류층(34)과 고농도 n형 웰(36)의 LDPMOS 채널영역에 채널이온이 주입된 상태이다.In addition, channel ions are implanted into the LDPMOS channel region of the p-type drifting layer 34 and the highly concentrated n-type well 36.
도 2b에서와 같이, 전면의 열산화 공정으로 상기 노출된 에피택셜층(32)상에 1900 ~ 2100Å두께의 제 1 산화막(39)을 성장시킨다.As shown in FIG. 2B, a first oxide film 39 having a thickness of 1900 to 2100 μs is grown on the exposed epitaxial layer 32 by a thermal oxidation process on the entire surface.
도 2c에서와 같이, 상기 제 1 산화막(39)을 포함한 전면에 제 1 감광막(40)을 도포하고, 상기 제 1 감광막(40)을 선택 사진 식각 공정으로 상기 n형 웰(33) 상측에만 남도록 선택적으로 노광 및 현상한다.As shown in FIG. 2C, the first photoresist film 40 is coated on the entire surface including the first oxide film 39, and the first photoresist film 40 is left only above the n-type well 33 by a selective photolithography process. And optionally exposure and development.
그리고, 상기 선택적으로 노광 및 현상된 제 1 감광막(40)을 마스크로 상기 190 ~ 210Å두께의 제 1 산화막(39)의 잔존층이 남도록 상기 제 1 산화막(39)을 선택적으로 식각한다.The first oxide film 39 is selectively etched using the selectively exposed and developed first photosensitive film 40 as a mask so that the remaining layer of the first oxide film 39 having a thickness of 190 to 210Å is left.
여기서, 상기 190 ~ 210Å두께의 제 1 산화막(39)의 잔존층이 남도록 상기 제 1 산화막(39)을 식각하기 때문에 상기 LDNMOS영역의 필드 산화막(38)에는 영향을 주지 않는다.Since the first oxide film 39 is etched so that the remaining layer of the first oxide film 39 having a thickness of 190 to 210Å is left, the field oxide film 38 of the LDNMOS region is not affected.
도 2d에서와 같이, 상기 제 1 감광막(40)을 제거한 후, 전면에 제 2 감광막(41)을 도포하고, 상기 제 2 감광막(41)을 상기 LDNMOS의 채널영역 상측에만 제거되도록 선택 사진 식각한다.As shown in FIG. 2D, after the first photoresist film 40 is removed, a second photoresist film 41 is coated on the entire surface, and the second photoresist film 41 is selectively etched so as to be removed only above the channel region of the LDNMOS. .
그리고, 상기 선택 사진 식각된 제 2 감광막(41)을 마스크로 전면에 BF2 +이온(42)을 80KeV의 에너지와 6.0E12㎝-2의 농도로 주입한다.Then, the BF 2 + ions 42 are injected at a concentration of 6.0 Ke12cm −2 and energy of 80 KeV on the entire surface of the selective photo-etched second photosensitive film 41.
도 2e에서와 같이, 상기 제 2 감광막(41)을 제거한 다음, 전면에 제 3 감광막(43)을 도포하고, 상기 제 3 감광막(43)을 상기 n형 웰(33) 상측에만 남도록 선택 사진 식각 공정 한다.As shown in FIG. 2E, after removing the second photoresist layer 41, a third photoresist layer 43 is applied to the entire surface of the second photoresist layer 41, and the third photoresist layer 43 is selected so that only the upper side of the n-type well 33 remains. Fair.
그리고, 상기 선택 사진 식각 공정된 제 3 감광막(43)을 마스크로 상기 190 ~ 210Å두께의 제 1 산화막(39)의 잔존층을 제거한다.The remaining layer of the first oxide film 39 having a thickness of 190 to 210 GPa is removed using the third photosensitive film 43 subjected to the selective photolithography process.
도 2f에서와 같이, 상기 제 3 감광막(43)을 제거하고, 전면의 열산화 공정으로 상기 노출된 에피택셜층(32)상에 190 ~ 210Å두께의 제 2 산화막(44)을 성장시킨다.As shown in FIG. 2F, the third photoresist layer 43 is removed, and a second oxide layer 44 having a thickness of 190 to 210 μm is grown on the exposed epitaxial layer 32 by thermal oxidation of the entire surface.
상기와 같은 공정들을 포함하여 LDPMOS와 LDNMOS를 형성한다.Including the above processes to form the LDPMOS and LDNMOS.
본 발명의 반도체 소자의 제조 방법은 LDNMOS영역의 LDPMOS 게이트 산화막을 잔존층이 남도록 선택 식각하므로, LDPMOS 게이트 산화막의 오버 에치시 발생되는 필드 산화막의 티닝 현상을 방지하여 소자의 항복전압 감소를 억제하므로 소자의 전기적 특성 및 신뢰성을 소자의 전기적 특성 및 신뢰성을 향상시키는 효과가 있다.Since the method for manufacturing a semiconductor device of the present invention selectively etches the LDPMOS gate oxide film in the LDNMOS region so that the remaining layer remains, the method reduces the breakdown voltage of the device by preventing the tinning of the field oxide film generated during overetching of the LDPMOS gate oxide film. The electrical properties and reliability of the device has the effect of improving the electrical properties and reliability.
Claims (5)
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