KR19990080831A - How to form trench isolation - Google Patents

Abstract

The present invention relates to trench isolation. A mask pattern for a trench formation region is formed by etching an insulating film formed on a semiconductor substrate, and a trench is formed by etching the semiconductor substrate using the mask pattern. In this case, an edge portion where the trench side walls and the bottom surface meet is formed to be rounded. An oxidation retardation gas is used at a predetermined temperature for a predetermined time to remove the substrate damage generated during the trench formation, thereby forming a thermal oxide film having a predetermined thickness on both side walls and the bottom surface of the trench. The edge portion of the upper portion of the trench is rounded by the thermal oxide film forming process. The trench is completely filled with device isolation material.

By such trench isolation, silicon lattice damage such as dislocation can be prevented, and the gate oxide dielectric property of the transistor can be improved.

Description

METHOD OF FORMING TRENCH INSULATION

TECHNICAL FIELD The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming trench isolation.

The isolation process between devices common in semiconductor manufacturing processes has been used to improve the conventional local oxidation of silicon (LOCOS) process. However, due to the recent high integration of semiconductor devices, the isolation process supplemented based on the existing LOCOS process has reached its limit.

In recent semiconductor devices, a shallow trench isolation (STI) process is used in which semiconductor devices of 256M DRAM or larger form narrow trenches on a silicon substrate, and fill the trenches with an insulating material to electrically isolate the devices.

1 is a diagram illustrating a conventional trench isolation.

Referring to FIG. 1, in the conventional trench isolation process, a thermal oxide film and a silicon nitride film are first formed on the semiconductor substrate 10. A trench formation region is defined on the silicon nitride film to form a photoresist film pattern. The silicon nitride layer and the first thermal oxide layer are sequentially etched until the upper portion of the semiconductor substrate 10 is exposed using the photoresist layer pattern.

After that, the semiconductor substrate 10 is etched to form a trench 12, and a second thermal oxide layer 14 is formed on both sidewalls and a lower surface of the trench 12 to remove etch damage of the trench 12.

A USG film 16 as a trench isolation film and a PE-TEOS film for alleviating stress of the USG film are formed on the silicon nitride film to fill the trench 12.

After the PE-TEOS film and the USG film 16 are sequentially planarized and etched to form trench isolation, the nitride film and the pad oxide film are removed in a subsequent process. In a subsequent process, a transistor including a gate oxide film and a gate electrode is formed.

Conventional trench isolation has a steep slope at the lower edge where the two side walls and the bottom face of the trench meet, so stress is concentrated on this area, resulting in silicon lattice damage such as dislocation, and the upper edge of the trench. Because the gate oxide and the second thermal oxide meet at a steep inclination, gate dielectric properties such as breakdown voltage, charge to breakdown, and the like become worse during transistor operation.

SUMMARY OF THE INVENTION The present invention has been proposed to solve the above-mentioned problems, and an object thereof is to provide trench isolation that can prevent silicon lattice damage such as dislocation and improve gate oxide dielectric properties in transistors. have.

1 illustrates a conventional trench isolation;

2 illustrates trench isolation in accordance with an embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

10, 100: semiconductor substrate 12, 106: opening

14, 102, 108: thermal oxide film 16, 110: USG film

18, 102: gate oxide film 104: silicon nitride film

(Configuration)

According to a feature of the present invention proposed to achieve the above object, trench isolation comprises the steps of: etching an insulating film formed on a semiconductor substrate to form a mask pattern for the trench formation region; Forming a trench by etching the semiconductor substrate using the mask pattern; Edge portions where the trench sidewalls and the bottom surface meet are formed to be rounded, and both sidewalls of the trench are formed by using an oxidation retardation gas at a predetermined temperature for a predetermined time to remove substrate damage generated during the trench formation. And forming a thermal oxide film having a predetermined thickness on a lower surface thereof. And forming a rounded edge portion of the upper portion of the trench by the thermal oxide film forming process, and completely filling the trench with a device isolation material.

Referring to FIG. 2D, the novel trench isolation formation method according to the embodiment of the present invention may include rounding of edge portions at which both sidewalls of the trench and the bottom surface meet each other, thereby preventing damage to the substrate generated during the trench formation. The edge portion of the upper portion of the trench is rounded by a thermal oxide film forming process for removal. Such trench isolation can prevent silicon lattice damage, such as dislocation, and improve the gate oxide dielectric properties of the transistor.

(Example)

Hereinafter, embodiments of the present invention will be described in detail with reference to FIGS. 2A to 2E.

2A to 2E are flowcharts sequentially illustrating a trench forming method according to the present invention.

Referring to FIG. 2A, a first thermal oxide film, which is a pad oxide film 102, is formed on the semiconductor substrate 100 to have a thickness of 160 μs for the protection of the semiconductor substrate 100, and on the first thermal oxide film 102. SiN film 104 is formed to a thickness of 1550 kPa. A trench formation region is defined on the SiN film 104 to form a photoresist film pattern (not shown), and the SiN film 104 and the first thermal oxide film are formed by a dry etching process using the photoresist film pattern. 102 are sequentially etched to form a mask pattern for trench formation.

Referring to FIG. 2B, a trench is formed by etching the semiconductor substrate 100 by using the mask pattern in a dry etching process. In this case, the depth of the trench 106 is in the range of 2500 kPa-2100 kPa.

The etching process includes two etching processes. In the first etching process, the semiconductor substrate 100 is etched vertically with the upper surface of the semiconductor substrate 100 to form an opening. The first etching process is performed at a pressure of 100 mT and a power of 400 W for 5 seconds using 35 sccm of CF ₄ gas.

In the second etching process, the bottom surface of the opening is etched, and both side walls and the bottom surface of the opening are etched roundly to form the trench 106. The second etching process is performed using a mixed gas of Cl ₂ , HBr, He, and O ₂ in a composition ratio of 30: 90: 10: 1 under a pressure of 100 mT and a power of 250 W.

Referring to FIG. 2C, a second thermal oxide layer 108 is formed on both sidewalls and a bottom surface of the trench 106 by a thermal oxidation process to remove etching damage of the trench 106. In this case, while the second thermal oxide film 108 is formed, both side walls and the bottom surface of the trench 106 are oxidized, and volume expansion occurs, and the volume expansion occurs at both side walls and the bottom surface of the trench 106. At the lower edge portion (a) where the second thermal oxide film is formed, the second thermal oxide film is thin and sharply formed. As a result, the stress of the trench 106 is concentrated on the edge region semiconductor substrate, thereby causing dislocation, which is a silicon lattice damage.

In order to solve the above problem, the second thermal oxide film 108 is formed to be thin to a thickness of less than about 240 kPa, and in order to reduce stress on the entire trench 106 generated in the second thermal oxide film 108 forming process, The process of forming the second thermal oxide film 108 is performed at a high temperature of about 1000 ° C. or higher so that the second thermal oxide film 108 causes a viscoelastic flow, and at the trench upper edge portion b, the substrate surface and the trench The second thermal oxide film 108 forming process must be performed for a long time so that steep slopes of both side walls are alleviated and rounded.

To this end, two gases are used in the process of forming the second thermal oxide film 108.

3 is a diagram illustrating a thermal oxide film forming process in the trench 106.

Referring to FIG. 3, the thermal oxide film forming process in the trench is a process for delaying the formation of the second thermal oxide film while the temperature reaches about 1000 ° C. (c). In this process, any one of an inert gas such as Ar and a nitrogen gas is used. Since the nitrogen gas causes a problem of damaging the surface of the silicon substrate, when the process is performed with nitrogen gas, about 5% of oxygen is included.

A mixed gas is used to delay the formation of the thermal oxide film so that the thermal oxide film of about 240 kPa is formed while the high temperature process (d) of about 1000 ° C. or more is performed for a long time. The prolonged high temperature process results in rounding of the upper edge where the side walls of the trench meet the substrate surface. The mixed gas is any one of a mixed gas containing an inert gas such as 95% Ar and 5% oxygen gas and a mixed gas containing 95% nitrogen gas and 5% oxygen gas. By using the mixed gas, a thermal oxide film having a thickness of about 240 kPa is formed in about 30 minutes.

Referring to FIG. 2D, a USG film 110, which is a trench insulating film, is formed on the semiconductor substrate 100 including the trench 106, and the trench 106 is filled to stress the USG film 110. A PE-TEOS film (not shown) is formed on the USG film 106 to mitigate the stress. The PE-TEOS film and the USG film 106 are sequentially flattened and etched until the upper surface of the silicon nitride film 104 is exposed.

After the silicon nitride film 104 and the first thermal oxide film 102 are removed in a subsequent process, a transistor forming process including the gate oxide film 112 is performed.

The present invention provides a conventional trench isolation in which the upper edge portion where both sidewalls of the trench and the upper surface of the semiconductor substrate meet and the lower edge portion where both sidewalls and the bottom surface of the trench meet each other have an inclination close to the vertical. Gate dielectric characteristics such as breakdown voltage, charge to breakdown, and silicon lattice damage such as dislocation due to concentration of trench stress in the edge region In order to solve the problem, by forming the upper and lower edge portions of the trench to be rounded, silicon lattice damages such as dislocations can be prevented and the gate dielectric characteristics of the transistor can be improved.

Claims (11)

Etching the insulating film formed on the semiconductor substrate 100 to form a mask pattern for the trench formation region; Forming a trench (106) by etching the semiconductor substrate (100) using the mask pattern; Edge portions where the trench side walls and the bottom surface meet is formed to be round (round), The thermal oxide film 108 having a predetermined thickness on both sidewalls and a bottom surface of the trench 106 using an oxidation retardation gas at a predetermined temperature for a predetermined time to remove damage to the substrate generated when the trench 106 is formed. Forming a; The edge portion of the upper portion of the trench 106 is rounded by the thermal oxide film forming process, And completely filling the trench (106) with device isolation material. The method of claim 1, The trench (106) has a depth within 2500 kPa-2100 kPa, and the thermal oxide film (108) is formed to have a thickness relatively less than about 240 kPa. The method of claim 1, The trench (106) forming process may include: vertically etching the semiconductor substrate (100) to form an opening; Etching the semiconductor substrate (100) below the opening, and forming a portion where the side walls and the bottom surface of the opening meet so that the lower edge portion is rounded. The method of claim 3, wherein The opening forming process is a trench isolation method is performed for 5 seconds using the first etching gas at a pressure of 100 mT, a power of 400W. The method of claim 4, wherein And the first etching gas comprises 35 sccm of CF ₄ . The method of claim 3, wherein The etching process below the opening is carried out for 60 seconds using a second etching gas at a pressure of 100 mT, a power of 250W, a magnetic field of 30G for 60 seconds. The method of claim 6, And the second etching gas is a mixed gas of Cl ₂ , HBr, He, and O ₂ , each having a composition ratio of 30: 90: 10: 1. The method of claim 1, The thermal oxide film forming process is performed at a temperature of at least 1000 ° C. for at least about 30 minutes. The method of claim 1, And the oxidation retardation gas is a mixed gas in which any one of nitrogen gas and inert gas is mixed with oxygen. The method of claim 9, And the oxidation retardation gas is a mixed gas in which the nitrogen gas and the oxygen gas have a composition ratio of 19: 1. The method of claim 9, And the oxygen retardation gas is a mixed gas having an inert gas and an oxygen gas having a composition ratio of 19: 1.