KR19990070644A - Error correction device and method - Google Patents

Abstract

An error correction apparatus and method are disclosed. The apparatus includes a memory for storing error data and error corrected data, a first syndrome calculation unit for calculating and outputting first and second syndromes from an upper byte of the error data stored in the memory, and an error data stored in the memory. A second syndrome calculation unit that calculates and outputs the third and fourth syndromes from the lower byte, and one of the outputs of the first syndrome calculation unit and the outputs of the second syndrome calculation unit in response to the first and second selection signals An output unit of the error correction processor and an error correction processor for correcting the error data of the error data from the syndromes selected by the syndrome selector, and outputting the error correction processor in response to the first and second selection signals; And logical operation means for outputting the result of the logical operation to the memory as error corrected data. Characterized in that.

Description

Error correction device and method

The present invention relates to a Compact Disk (CD) -Read Only Memory (ROM) system, and more particularly, to an error correction apparatus and a method for correcting errors contained in data from a CD-ROM system.

In a CD-ROM system using a storage media, loss of source data may occur due to a defect in the media itself or noise during transmission when restoring and transmitting the stored data. To this end, the CD-ROM system employs an appropriate error correction unit to correct a certain amount of errors by itself.

Recently, as data processing speed of CD-ROM is gradually increasing and speeding competition among companies is getting fiercer, the time required for ECC is becoming very important in speeding competition.

Hereinafter, a configuration and operation of a conventional error correction apparatus will be described as follows with reference to the accompanying drawings.

FIG. 1 is a block diagram of a conventional error correction apparatus, which includes an 8-bit memory 10, a syndrome generator 22, a buffer interface 24, and an error code correction (ECC) engine 20. It consists of the ECC processing part 26.

The 8-bit memory 10 of the error correction apparatus shown in FIG. 1 receives and stores data output from a digital signal processor (not shown) of the CD-ROM system, and the ECC engine 20 uses the 8-bit memory 10. The data stored in the data is read out, ECCed, and error corrected data is output back to the 8-bit memory 10. As described above, the conventional error correction apparatus shown in FIG. 1 corrects an error of data in a pipeline form.

FIG. 2 is a diagram for describing a time required for error correction performed in the apparatus shown in FIG. 1.

However, the conventional error correction apparatus shown in FIG. 1 described above inputs 8 bits of data from the memory 10 during the time T shown in FIG. 2 (Data In), and inputs it for the time t1 or t2. Since it corrects an error of one data, it takes more time to receive data from the 8-bit memory 10 and write the error-corrected data back to the 8-bit memory 10 than the time required for ECC processing. There is this.

An object of the present invention is to provide an error correction apparatus that can correct an error at high speed and improve a data processing speed.

Another object of the present invention is to provide an error correction method capable of improving data processing speed by correcting errors at high speed.

1 is a block diagram of a conventional error correction apparatus.

FIG. 2 is a diagram for describing a time required for error correction performed in the apparatus shown in FIG. 1.

3 is a block diagram of an error correction apparatus according to the present invention.

4A and 4B are diagrams for describing memory operation in a CD-ROM system.

FIG. 5 is a circuit diagram of a preferred embodiment according to the present invention of the syndrome selecting unit shown in FIG. 3.

FIG. 6 is a circuit diagram of one preferred embodiment of the present invention according to the present invention.

FIG. 7 is a diagram for describing a time for performing error correction in the error correction apparatus shown in FIG. 3.

In order to achieve the above object, an error correction apparatus according to the present invention for correcting the error of error data reproduced from a CD-ROM system and having an error includes: a memory for storing the error data and the error corrected data; A first syndrome calculator configured to calculate and output first and second syndromes from the upper byte of the stored error data, and a second to calculate and output third and fourth syndromes from the lower byte of the error data stored in the memory; Syndrome selection means for selectively outputting one of a syndrome calculation section, outputs of the first syndrome calculation section and outputs of the second syndrome calculation section in response to first and second selection signals, and syndromes selected by the syndrome selection means; An error correction processor for correcting and outputting the error of the error data from the first and second lines In response to the tack signal, it is preferable that the logic correction means is configured to output the error correction processor and the error data stored in the memory, and output the result of the logical operation as the error corrected data to the memory. .

In order to achieve the above another object, the present invention is performed in a memory for storing error data and error corrected data reproduced from a CD-ROM system and an error correction device for correcting the error and outputting the error corrected data. The error correction method may further include correcting the error by dividing the error data from the memory into an upper byte and a lower byte, and the upper byte and the lower byte and the upper byte and the lower byte of the error data corrected. It is preferable that each of the bytes is synthesized to obtain the error corrected data.

Hereinafter, the configuration and operation of an error correction apparatus according to the present invention will be described with reference to the accompanying drawings.

3 is a block diagram of an error correction apparatus according to the present invention, wherein the memory 40, the first and second syndrome calculation units 42 and 44, the logic operation unit 46, and the syndrome selection constituting the ECC engine 52 are selected. It consists of a unit 48 and an error correction processing unit 50.

4A and 4B are diagrams for explaining memory operations in a CD-ROM system, in which FIG. 4A shows P codeword data and FIG. 4B shows Q codeword data, respectively.

The error correction engine 52 shown in FIG. 3 is provided between a CD-ROM system (not shown) and a host computer (not shown), and a data interface (not shown) for interfacing data transfer between the CD-ROM system and the host computer. Can be provided within At this time, the memory 40 is provided outside the data interface (not shown).

In the case where the memory 40 shown in Fig. 3 is a 16-bit dynamic random access memory (DRAM), the error correction apparatus according to the present invention can obtain two code words at the same time. That is, the P code word data and the Q code word data shown in Figs. 4A and 4B, respectively, are not composed of data existing at consecutive address positions in the memory 40, but are composed of data having a constant interval. Therefore, the 16-bit data read out at one time from the memory 40 having the 16-bit bus means that the upper 8 and lower 8 bits are separate data belonging to different code words. Thus, while accessing memory 26 times to read one code word using the 8-bit memory 10 shown in FIG. 1, using the 16-bit memory 40 shown in FIG. 3 results in two code words. Can be obtained during the same time.

For this purpose, the detailed operation of the error correction apparatus shown in FIG. 3 will be described. The memory 40 is reproduced from the CD-ROM system and has error-corrected error data in the error correction processing unit 50 and the logic operation unit 46. Save the error corrected data that is output through). The first syndrome calculator 42 calculates the first and second syndromes SOH and S1H from the upper 8 bits of the 16-bit error data read from the memory 40, and the second syndrome calculator 44. Calculates the third and fourth syndromes SOL and S1L from the lower 8 bits of the 16-bit error data read from the memory 40 and outputs the third and fourth syndromes SOL and S1L to the syndrome selector 48. Here, since the first and second syndromes 42 and 44 use a widely known syndrome calculation method, description thereof is omitted.

Meanwhile, the first syndrome selecting unit 48 selects the first, second, third, and fourth syndromes SOH, S1H, SOL, and S1L output from the first and second syndrome calculation units 42 and 44. Selected in response to the first and second selection signals SEH and SEL input from the outside, and outputs the selected syndromes SO and S1 to the error correction processor 50. That is, the syndrome selecting unit 48 may output the first syndrome output unit 42 when the first selection signal SEH is activated at a "high" logic level and the second selection signal SEL is disabled. The syndrome and the second syndrome (SOH or S1H) are selected and output to the error correction processor 50. However, the syndrome selector 48 may output a third output from the second syndrome calculator 44 when the first select signal SEH is disabled and the second select signal SEL is activated at a high logic level. The syndrome and the fourth syndrome SOL or S1L are output to the error correction processor 50.

FIG. 5 is a circuit diagram of a preferred embodiment of the syndrome selector 48 shown in FIG. 3 according to the present invention, with first, second, third and fourth transfer gates 70, 72, 74 and 76. FIG. It is composed.

The first transfer gate 70 of the syndrome selector illustrated in FIG. 5 receives the first syndrome SOH input from the first syndrome calculator 42 in response to the first selection signal SEH to correct the error. The second transmission gate 72 transmits the second syndrome S1H to the error correction processor 50 in response to the first selection signal SEH. In the same principle, the third transmission gate 74 transmits the third syndrome SOL to the error correction processing unit 50 in response to the second selection signal SEL, and the fourth transmission gate 76 transmits the second transmission signal. The fourth syndrome S1L is transmitted to the error correction processor 50 in response to the selection signal SEL.

Meanwhile, the error correction processing unit 50 shown in FIG. 3 corrects and outputs an error of error data from the syndromes SO and S1 selected by the syndrome selecting unit 48. At this time, the error correction processing unit 50 is an ECC processing core generally used for ECC, and the description thereof is omitted.

On the other hand, the logic calculating section 46, in response to the first and second selection signals SEH and SEL input from the outside, the 8-bit data OUT1 and the memory 40 output from the error correction processing section 50. The 16-bit error data read out from the data is logically operated, and the result of the logical operation is output to the memory 40 as 16-bit data with error correction. That is, the logic operation unit 46 determines whether the 8-bit data currently being error corrected and output from the error correction processing unit 50 is a result of a code word consisting of an upper byte or a code word consisting of a lower byte. If it is an error detection value for the upper byte, the lower byte of the 16-bit error data is made as '0' and the result value shown in Equation 1 is output.

Here, C represents 16 bits of error data input from the memory 40 to the logic calculating section 46, A represents 8 bits of data input from the error correction processing section 50 to the logic calculating section 46, and B Denotes 1 byte whose value is 0, and A C represents an upper byte output from the logical operation unit 46, and B C represents the lower byte output from the logical operation unit 46, respectively.

FIG. 6 is a circuit diagram of a preferred embodiment of the logic operation unit 46 shown in FIG. 3 according to the present invention, and includes first and second AND gates 80 and 82 and an exclusive logic sum 84.

The first AND gate 80 of the logic operation unit 46 shown in FIG. 6 logically multiplies the first selection signal SEH and the 8-bit output OUT1 output from the error correction processing unit 50, and logically multiplies the result. Is output to the exclusive logical sum unit 84. The second AND gate 82 ANDs the second selection signal SEL and the eight-bit output OUT1 output from the error correction processing unit 50, and outputs the result of the AND operation to the exclusive AND unit 84. The exclusive OR unit 84 exclusively ORs the 8-bit data output from the first AND gate 80 and the upper byte of the 16-bit error data read out from the memory 40 and input through the input terminal IN. One result is output through the output terminal OUT2 as the upper byte of the error corrected data. In addition, the exclusive OR unit 84 exclusively ORs the lower byte of the 8-bit data output from the second AND gate 82 and the 16-bit error data read out from the memory 40 and error-excludes the result of the exclusive OR. The lower byte of the corrected data is output through the output terminal OUT2.

FIG. 7 is a diagram for describing a time for performing error correction in the error correction apparatus shown in FIG. 3.

Comparing the ECC execution time when the 8-bit memory 10 is used and the 16-bit memory 40 is used, as shown in FIG. 2, the conventional error correction apparatus writes data once for a time T. While inputting, correcting an error of the input data for a time t1, then inputting data again from the memory for a time T, and correcting an error of the input data for a time t2, while shown in FIG. As described above, the error correction apparatus according to the present invention inputs two pieces of data for a time T, corrects the lower byte of the input data, and then corrects the error of the upper byte. I / O speed will be very fast.

In addition, the error correction apparatus according to the present invention may correct the error of the upper byte and then correct the error of the lower byte. To this end, when the error of the upper byte of the error data is to be corrected first, the first selection signal SEH is activated to a "high" logic level, and when the error correction for the upper byte code word is completed, the first selection signal SEH is disabled and the second select signal SEL is activated to a "high" logic level and error correction is performed for the lower byte code word. Next, when the error correction for the lower byte code word is completed, the second selection signal SEL is disabled.

As described above, the error correction apparatus and method according to the present invention perform error correction by dividing the error data into the upper byte and the lower byte, so that the error correction execution time is very fast and the data processing speed is improved.

Claims (6)

An error correction apparatus for correcting said error of error data reproduced from a compact disc (ROM) -ROM system and having an error, A memory for storing the error data and the error corrected data; A first syndrome calculator configured to calculate and output first and second syndromes from an upper byte of the error data stored in the memory; A second syndrome calculation unit configured to calculate and output third and fourth syndromes from the lower byte of the error data stored in the memory; Syndrome selecting means for selectively outputting one of the outputs of the first syndrome calculating part and the outputs of the second syndrome calculating part in response to first and second selection signals; An error correction processor for correcting and outputting an error of the error data from syndromes selected by the syndrome selecting means; And In response to the first and second selection signals, a logical operation of outputting the error correction processing unit and the error data stored in the memory, and outputting the result of the logical operation as the error corrected data to the memory. And error correction means. The method of claim 1, wherein the syndrome selecting means A first transmission gate configured to transmit the first syndrome in response to the first selection signal; A second transmission gate configured to transmit the second syndrome in response to the first selection signal; A third transmission gate configured to transmit the third syndrome in response to the second selection signal; And A fourth transmission gate configured to transmit the fourth syndrome in response to the second selection signal, And the output of the first transfer gate or the third transfer gate and the output of the second transfer gate or the output of the fourth transfer gate are the selected syndromes. The method according to claim 1 or 2, wherein the logical computing means First AND product for ANDing and outputting the first selection signal and the output of the error correction processor; Second logical AND means for ANDing and outputting the second selection signal and the output of the error correction processor; And An exclusive OR of the output of the first AND function and the upper byte of the error data read out from the memory is output as an upper byte of the error corrected data, and the output of the second AND product is read from the memory And an exclusive logical OR means for exclusive ORing the lower byte of the error data and outputting the lower byte of the error corrected data as the lower byte of the error corrected data. 2. The apparatus of claim 1, wherein the first and second syndrome calculation units, the syndrome selection means, the error correction processing unit, and the logical operation unit are provided in a data interface unit provided for data transfer between the CD-ROM system and a host computer. Error correction apparatus, characterized in that it is included. The apparatus of claim 1, wherein the memory is 16-bit dynamic RAM. Error correction performed in a compact disc (CD) -ROM system, a memory for storing error data and error corrected data having errors, and an error correction device for correcting the error and outputting the error corrected data. In the method, Correcting the error by dividing the error data from the memory into an upper byte and a lower byte; And And synthesizing the upper byte and the lower byte of the error corrected and the upper byte and the lower byte of the error data, respectively, to obtain the error corrected data.