KR19990070239A - Silicon layer planarization method - Google Patents
Silicon layer planarization method Download PDFInfo
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- KR19990070239A KR19990070239A KR1019980004976A KR19980004976A KR19990070239A KR 19990070239 A KR19990070239 A KR 19990070239A KR 1019980004976 A KR1019980004976 A KR 1019980004976A KR 19980004976 A KR19980004976 A KR 19980004976A KR 19990070239 A KR19990070239 A KR 19990070239A
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- silicon layer
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- amorphous silicon
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 52
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 52
- 239000010703 silicon Substances 0.000 title claims abstract description 52
- 238000000034 method Methods 0.000 title claims abstract description 35
- 239000010408 film Substances 0.000 claims abstract description 56
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 34
- 239000010409 thin film Substances 0.000 claims abstract description 34
- 239000011521 glass Substances 0.000 claims abstract description 15
- 239000000758 substrate Substances 0.000 claims abstract description 15
- 230000003213 activating effect Effects 0.000 claims description 4
- 238000001312 dry etching Methods 0.000 claims description 2
- 238000001039 wet etching Methods 0.000 claims 1
- 238000002425 crystallisation Methods 0.000 abstract description 10
- 230000008025 crystallization Effects 0.000 abstract description 8
- 230000006866 deterioration Effects 0.000 abstract description 3
- 238000005499 laser crystallization Methods 0.000 abstract description 3
- 238000004519 manufacturing process Methods 0.000 abstract description 3
- 239000013078 crystal Substances 0.000 description 26
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 229910052814 silicon oxide Inorganic materials 0.000 description 6
- 238000010586 diagram Methods 0.000 description 3
- 239000007789 gas Substances 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000001678 irradiating effect Effects 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000009499 grossing Methods 0.000 description 1
- 238000005304 joining Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000002244 precipitate Substances 0.000 description 1
- 238000007711 solidification Methods 0.000 description 1
- 230000008023 solidification Effects 0.000 description 1
- 238000004381 surface treatment Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/30625—With simultaneous mechanical treatment, e.g. mechanico-chemical polishing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32115—Planarisation
- H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
Abstract
본 발명은 비정질실리콘층을 결정화할 시에 실리콘층을 평탄화하는 방법에 관한 것으로, 유리기판 상에 비정질실리콘 박막을 형성하는 공정과, 비정질실리콘 박막에 활성기 처리 및 레이저 결정화하여 표면에 선택적으로 절연막이 형성된 실리콘층을 형성하는 공정과, 절연막을 선택적으로 제거하는 공정을 구비한 것이 특징이다.The present invention relates to a method of planarizing a silicon layer when crystallizing an amorphous silicon layer, the process of forming an amorphous silicon thin film on a glass substrate, and an active layer treatment and laser crystallization on the amorphous silicon thin film to selectively insulating the surface And a step of forming the formed silicon layer and selectively removing the insulating film.
그리고, 유리기판 상에 비정질실리콘 박막을 형성하는 공정과, 비정질실리콘 박막에 호라성처리 및 레이저 결정화하여 표면에 제 1절연막이 형성된 실리콘층을 형성하는 공정과, 제 1절연막 상에 제 2절연막을 형성하는 공정을 구비한 것이 특징이다.Forming an amorphous silicon thin film on the glass substrate; forming a silicon layer having a first insulating film formed on the surface by performing a homogeneous treatment and laser crystallization on the amorphous silicon thin film; and forming a second insulating film on the first insulating film. It is characterized by including the step of forming.
따라서, 본 발명에서는 단일의 또는 이중의 절연막을 형성함으로써 결정화 시에 표면이 매끄럽지 못한 실리콘층을 평탄화할 수 있다.Therefore, in the present invention, by forming a single or double insulating film, the silicon layer whose surface is not smooth at the time of crystallization can be planarized.
그리고, 이 후에 형성될 게이트절연막으로 이용될 절연막을 실리콘층 제조 시에 동시에 형성하여서 그 표면을 평탄화시킴에 따라 결정화 시에 매끄럽지 못한 실리콘층 표면의 기복에 의해 발생되는 열화특성을 억제할 수 있는 잇점이 있다.In addition, since an insulating film to be used as a gate insulating film to be formed thereafter is simultaneously formed during the production of the silicon layer and the surface thereof is flattened, the deterioration characteristics caused by the undulation of the surface of the silicon layer, which is not smooth during crystallization, can be suppressed. There is this.
Description
본 발명은 실리콘층의 평탄화방법에 관한 것으로, 특히, 비정질실리콘을 결정화할 시에 활성처리하여 절연막을 형성함으로써 이를 이용하여 실리콘층 표면을 평탄화하는 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a planarization method of a silicon layer, and more particularly, to a method of planarizing a silicon layer surface by using an active process to form an insulating film when crystallizing amorphous silicon.
저온 다결정실리콘(poly-silicon)박막 트랜지스터는 비정질실리콘 박막 트랜지스터에 비해 전자이동도가 높기 때문에 유리기판 위에 데이타 구동회로와 게이트 구동회로를 픽셀 어레이와 동시에 제작이 가능하고, 픽셀소자에 적용될 때 스위치 소자의 크기가 작아도 되기 때문에 개구율을 비롯한 제반 화질이 뛰어나다.Low-temperature poly-silicon thin film transistors have higher electron mobility than amorphous silicon thin-film transistors, so that data driving circuits and gate driving circuits can be fabricated on the glass substrate simultaneously with the pixel array. Since the size may be small, the overall image quality is excellent, including the aperture ratio.
이러한 저온 다결정실리콘 박막 트랜지스터 공정의 핵심기술로는 400℃ 이하 저온 공정에서 엑시머 레이저 조사를 이용한 비정질 상태의 실리콘 박막의 결정화를 들 수 있다.The core technology of the low-temperature polysilicon thin film transistor process is the crystallization of the amorphous silicon thin film using excimer laser irradiation in a low temperature process below 400 ℃.
이 기술은 비정질실리콘에 레이저 에너지를 가함으로써 용융상태로 만든 후에 고화시키어 결정으로 형성시키는 것으로, 고화 시 최초에 생긴 결정을 중심으로 성장하며, 이 때, 결정은 성장방향이 단일하도록 성장되면, 단결정(single-crystallization)이 되고, 많은 결정이 동시에 성장되어 성장방향이 여러 방향이 되면 다결정(poly-crystallization)이 된다.In this technique, amorphous silicon is applied to laser energy to make it into a molten state, and then solidify to form crystals. The technology grows around the crystals formed at the time of solidification. (single-crystallization), many crystals are grown at the same time, when the growth direction is in several directions it becomes a poly-crystallization.
다결정인 경우에는 각각의 결정들이 성장하면서 결정경계(grain boundary)에서 서로 만나게 되는 데, 이 결정경계에는 결정방향이 다른 결정면의 접합으로 구조적으로 취약하며, 결정성장에 따른 결정면의 충돌로 심하게 돌출되게 된다. 이 실리콘층은 선택적으로 그 상부에 게이트절연막이 형성되며, 이 실리콘층은 구조적으로 안정하거나 표면이 평탄할수록 국부전계에 따른 스트레스를 덜 받아 소자특성이 우수하게 된다.In the case of polycrystals, each crystal grows and meets each other at the grain boundary. In this crystal boundary, the crystal direction is structurally weak due to the joining of different crystal planes, and the crystal planes are severely protruded due to the collision of the crystal planes. do. The silicon layer is selectively formed with a gate insulating film thereon, and the silicon layer is structurally stable or has a flat surface, which is less stressed by local electric fields, thereby improving device characteristics.
도 1A 내지 도 1B 는 종래기술에 따른 실리콘층을 형성하기 위한 제조공정도이다.1A to 1B are manufacturing process diagrams for forming a silicon layer according to the prior art.
그리고, 도 1는 도 1B 의 L1 부분을 부분확대한 단면도이다.1 is a partially enlarged cross-sectional view of the portion L1 of FIG. 1B.
도 1A 와 같이, 유리기판(100) 상에 완충산화막으로 사용될 실리콘산화막(102)을 증착하고, 이 실리콘산화막(102) 상에 결정화시킬 비정질실리콘 박막(104)을 순차적으로 형성한다.As shown in FIG. 1A, a silicon oxide film 102 to be used as a buffer oxide film is deposited on the glass substrate 100, and an amorphous silicon thin film 104 to be crystallized is formed sequentially on the silicon oxide film 102.
이 비정질실리콘 박막(104)은 진공챔버 내부에 주입된 실리콘가스를 PECVD(Plasma Enhanced Chemical Vapor Deposition) 방법으로 증착함으로써 형성된다.The amorphous silicon thin film 104 is formed by depositing silicon gas injected into the vacuum chamber by a plasma enhanced chemical vapor deposition (PECVD) method.
도 1B 와 같이, 비정질실리콘 박막(104)이 형성된 유리기판(100) 상에 적당한 에너지 밀도와 반복율을 갖는 레이저 빔을 일정영역에 국부적으로 조사하면서 용융시킨 후에, 다음 영역으로 이동시키는 동작을 반복 시행함으로써 비정질실리콘 박막 전면에 조사하여 실리콘층(104-1)을 형성한다.As shown in FIG. 1B, a laser beam having an appropriate energy density and repetition rate is locally melted while irradiating a laser beam having an appropriate energy density and repetition rate on the glass substrate 100 on which the amorphous silicon thin film 104 is formed, and then repeatedly moved to the next area. As a result, the entire surface of the amorphous silicon thin film is irradiated to form the silicon layer 104-1.
이 실리콘층(104-1) 상부에는, 도면에 도시되지는 않았지만, 게이트절연막과 게이트전극이 패터닝된다.Although not shown in the figure, the gate insulating film and the gate electrode are patterned on the silicon layer 104-1.
도 2를 참조하여 상술한 실리콘층(104-1)이 형성되는 과정을 알아보면, 우선, 레이저빔이 조사된 비정질실리콘 박막 부분은 완전히 용융된 상태가 된다. 이 부분에는 다 수개의 결정핵이 생성되고, 이 결정핵이 시드로 작용한다. 이 시드들은 레이저 조사 시에 발생된 열에 의해 동시 다발적으로 여러 방향으로 결정 성장이 진행된다. 그리고 이러한 결정성장은 시간이 지남에 따라 에너지가 외부로 방출되어 고화되면서 성장을 멈추게 되는 데, 결정경계의 부딪친 부위도 고화되어 돌출된 형태( C1)을 가진다. 그리고, 도면번호 b1 은 결정의 크기를 표시한 것이다. 이 결정의 크기(b1)은 낮은 에너지 밀도를 갖는 레이저빔 조사에 의해서는 거의 증가하지 않고, 높은 에너지 밀도를 갖는 레이저빔 조사에 의해서는 박막의 전체 깊이까지를 녹이므로 결정의 크기가 매우 커지게 되며, 또한, 결정도도 좋아지게 된다.Referring to the process of forming the silicon layer 104-1 described above with reference to FIG. 2, first, an amorphous silicon thin film portion irradiated with a laser beam is completely melted. In this part, several seed nuclei are generated, which act as seeds. These seeds undergo multiple crystal growth in multiple directions simultaneously due to heat generated during laser irradiation. The crystal growth stops as the energy is released to the outside and solidifies with time, and the bumps of the crystal boundary are also solidified and have a protruding form (C1). Reference numeral b1 denotes the size of the crystal. The size (b1) of the crystal is hardly increased by the laser beam irradiation having a low energy density, and by the laser beam irradiation having a high energy density, the crystal is melted up to the entire depth of the thin film so that the crystal size becomes very large. In addition, crystallinity is also improved.
그러나, 종래의 방법에서 실리콘층은 결정경계에서 돌출된 부위를 가짐에 따라 표면이 평탄하지 못하여 기복이 형성되며, 이 돌출된 부위의 열화에 의해 게이트절연막이 퐈괴되는 문제점이 있었다.However, in the conventional method, as the silicon layer has a protruding portion in the crystal boundary, the surface is not flat and undulation is formed, and there is a problem in that the gate insulating film is collapsed due to deterioration of the protruding portion.
상기의 문제점을 해결하고자, 본 발명의 목적은 실리콘층의 표면을 매끄럽게 처리하여 평탄화가 가능한 실리콘층의 평탄화방법을 제공하려는 것이다.In order to solve the above problems, an object of the present invention is to provide a method of planarizing a silicon layer that can be smoothed by smoothing the surface of the silicon layer.
본 발명의 실리콘층의 평탄화방법은 유리기판 상에 비정질실리콘 박막을 형성하는 공정과, 비정질실리콘 박막에 활성기 처리 및 레이저 결정화하여 표면에 선택적으로 절연막이 형성된 실리콘층을 형성하는 공정과, 절연막을 선택적으로 제거하는 공정을 구비한 것이 특징이다.The planarization method of the silicon layer of the present invention includes the steps of forming an amorphous silicon thin film on a glass substrate, forming a silicon layer having an insulating film selectively formed on the surface by activating and laser crystallizing the amorphous silicon thin film, and selecting an insulating film. It is characterized by including the process of removing.
본 발명의 실리콘층의 평탄화방법은 유리기판 상에 비정질실리콘 박막을 형성하는 공정과, 비정질실리콘 박막에 활성처리 및 레이저 결정화하여 표면에 제 1절연막이 형성된 실리콘층을 형성하는 공정과, 제 1절연막 상에 제 2절연막을 형성하는 공정을 구비한 것이 특징이다.The method of planarizing a silicon layer of the present invention comprises the steps of forming an amorphous silicon thin film on a glass substrate, a process of forming a silicon layer having a first insulating film formed on the surface by active treatment and laser crystallization on the amorphous silicon thin film, and a first insulating film It is characterized by including the process of forming a 2nd insulating film on it.
도 1A 내지 도 1B 는 종래기술에 따른 실리콘층을 형성하기 위한 제조공정도이고,1A to 1B are manufacturing process diagrams for forming a silicon layer according to the prior art,
도 2는 도 1B 의 L1 부분을 부분확대한 단면도이고,FIG. 2 is a partially enlarged cross-sectional view of part L1 of FIG. 1B;
도 3A 내지 도 3D 는 본 발명에 따른 제 1실시예로, 절연막을 이용하여 실리콘층 표면의 평탄화를 보인 도면이고,3A to 3D show a planarization of a silicon layer surface using an insulating film as a first embodiment according to the present invention.
도 4A 내지 도 4B 는 본 발명에 따른 제 2실시예로, 이중의 절연막을 이용하여 실리콘층 표면의 평탄화를 보인 공정도이다.4A to 4B are process diagrams showing planarization of a silicon layer surface using a double insulating film according to a second embodiment of the present invention.
*도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
100, 300, 400. 유리기판100, 300, 400. Glass substrate
102, 302, 402. 실리콘 산화막102, 302, 402. Silicon oxide film
104, 304, 404. 비정질실리콘 박막104, 304, 404. Amorphous Silicon Thin Film
104-1, 304-1, 404-1. 실리콘층104-1, 304-1, 404-1. Silicon layer
406-1. 절연막406-1. Insulating film
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하겠다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
도 3A 내지 도 3D 는 본 발명에 따른 제 1실시예로, 절연막을 이용함으로써 실리콘층 표면이 평탄화됨을 보인 공정단면도이다.3A to 3D are cross-sectional views of a first embodiment of the present invention in which the surface of a silicon layer is planarized by using an insulating film.
본 발명의 실리콘층을 평탄화하는 제 1실시예는 다음과 같다.A first embodiment of planarizing the silicon layer of the present invention is as follows.
도 3A 와 같이, 유리기판(300) 상에 완충산화막으로 사용될 실리콘산화막(302)을 증착한 후, 이 실리콘산화막(302) 상에 비정질실리콘 박막(304)을 순차적으로 형성한다.As shown in FIG. 3A, after depositing a silicon oxide film 302 to be used as a buffer oxide film on the glass substrate 300, an amorphous silicon thin film 304 is sequentially formed on the silicon oxide film 302.
이어서, 비정질실리콘 박막(304) 상에 산소 또는 질소(O2 ,N2또는 N2O)등의 가스를 이용하여 활성처리한다. 도면번호 306은 비정질실리콘 박막(304) 표면이 활성처리됨을 보인 것이다.Subsequently, the amorphous silicon thin film 304 is activated using a gas such as oxygen or nitrogen (O 2, N 2 or N 2 O). Numeral 306 shows that the surface of the amorphous silicon thin film 304 is activated.
도 3B 와 같이, 활성처리된 비정질실리콘 박막(304) 상에 레이저빔을 조사하여 국부적으로 용융시키어 점차적으로 전면을 결정화한다.As shown in FIG. 3B, a laser beam is irradiated locally on the activated amorphous silicon thin film 304 to gradually crystallize the front surface.
도 3C 와 같이, 결정화를 통해 실리콘층(304-1)이 형성되며, 이 실리콘층(304-1) 표면에는 상술한 O2 ,N2또는 N2O 등의 가스를 활성처리로 인해 절연막(306-1)이 형성된다.As shown in FIG. 3C, a silicon layer 304-1 is formed through crystallization, and an insulating film (such as O 2, N 2, or N 2 O, etc. described above) is formed on the surface of the silicon layer 304-1 by an active treatment. 306-1).
그리고, 결정화 과정에서, 결정은 성장되면서 결정경계에 달해서는 서로 부딪치어 충돌되고, 이러한 결정성장은 시간이 지남에 따라 에너지가 외부로 방출되어 고화되면서 성장을 멈추며, 경정경계의 충돌된 부위도 고화되어 돌출된 형태(C3)를 가진 실리콘층(304-1)이 형성된다.And, in the process of crystallization, as the crystals grow and reach the crystal boundary, they collide and collide with each other, and such crystal growth stops growing as the energy is released to the outside and solidifies over time. As a result, a silicon layer 304-1 having a protruding shape C3 is formed.
도 3D 와 같이, 실리콘층(304-1)은 결정경계에서 돌출되기 때문에 그 표면에 기복이 형성되므로, 이를 없애기 위해, 실리콘층(304-1)을 건식식각 방법 및 습식액인 BOE(Buffered Oxide Etchant)용액으로 표면처리함으로써 절연막(306-1)을 제거하여 실리콘층(304-1)의 표면을 평탄화한다.As shown in FIG. 3D, since the silicon layer 304-1 protrudes from the crystal boundary, relief is formed on the surface thereof. In order to eliminate this, the silicon layer 304-1 is a dry etching method and a wet liquid BOE (Buffered Oxide). The surface of the silicon layer 304-1 is planarized by removing the insulating film 306-1 by surface treatment with an etchant solution.
즉, 실리콘층(304-1) 표면에 형성된 절연막(306-1)은 그 표면에 돌출된 부위(C3) 및 이 돌출된 부위들 사이에는 평탄화 부위를 갖는 데, 이 때, 결정경계에서 돌출된 부위(C3)는 습식액인 BOE 용액에 의해 양방향으로 식각되므로 다른 부위에 비해 비교적 식각속도가 빠르게 진행된다. 따라서, 실리콘층(304-1)은 돌출된 부위들이 식각됨으로써 결과적으로 그 표면이 평탄하게 된다.That is, the insulating film 306-1 formed on the surface of the silicon layer 304-1 has a planarized portion between the portion C3 protruding from the surface and the protruding portions, wherein the insulating layer 306-1 protrudes from the crystal boundary. Site (C3) is etched in both directions by the BOE solution of the wet solution, so the etching speed is relatively faster than other sites. Thus, the surface of the silicon layer 304-1 is flattened as the protruding portions are etched.
이 후, 도면에 도시되지는 않았지만, 평탄화된 실리콘층 상에 게이트절연막 및 게이트전극이 형성된다.Thereafter, although not shown in the figure, a gate insulating film and a gate electrode are formed on the planarized silicon layer.
도 4A 내지 도 4B 는 본 발명에 따른 제 2실시예로, 이중의 절연막을 이용함으로써 실리콘층 표면이 평탄화됨을 보인 공정단면도이다.4A through 4B are process cross-sectional views showing a planarization of a silicon layer surface by using a double insulating film in accordance with a second embodiment of the present invention.
도 4A 와 같이, 유리기판(400) 상에 비정질실리콘 박막(404)을 증착하되, 유리기판(400)과 비정질실리콘 박막(404) 사이에는 완충산화막으로 사용될 실리콘산화막(402)을 개재시킨다. 도면번호 406은 비정질실리콘 박막(404) 표면이 활성처리됨을 보인 것이다.As shown in FIG. 4A, an amorphous silicon thin film 404 is deposited on the glass substrate 400, and a silicon oxide film 402 to be used as a buffer oxide film is interposed between the glass substrate 400 and the amorphous silicon thin film 404. Numeral 406 shows that the surface of the amorphous silicon thin film 404 is activated.
이 후, 비정질실리콘 박막(404)을 O2 ,N2또는 N2O 가스 등을 이용하여 활성처리한다.Thereafter, the amorphous silicon thin film 404 is activated by using O 2, N 2, or N 2 O gas or the like.
도 4B 와 같이, 활성처리(406)된 비정질실리콘 박막(404)에 국부적으로 레이저빔을 조사함으로써 용융시키고, 다음 영역으로 이동시키는 동작을 반복시행함으로써 전면을 결정화한다.As shown in Fig. 4B, the entire surface is crystallized by repeatedly performing the operation of activating the amorphous silicon thin film 404 locally by irradiating a laser beam and moving to the next region.
도 4C 와 같이, 상술한 결정화 과정을 통해 실리콘층(404-1)이 형성된다.As shown in FIG. 4C, the silicon layer 404-1 is formed through the above-described crystallization process.
이 실리콘층(404-1)은 상술한 활성처리로 인해 그 표면에 SiOX또는SiNX또는 SiNOX형태의 제 1절연막(406-1)이 형성된다.The silicon layer 404-1 is formed with a first insulating film 406-1 in the form of SiO X or SiN X or SiNO X on the surface of the silicon layer 404-1.
그리고 레이저 조사 과정에서, 결정들은 성장되면서 결정경계에서 서로 부딪치게 되며, 서서히 에너지가 외부로 방출됨에 따라 이 부위의 결정은 고화되면서 돌출된 형태(C4)로 석출되어 실리콘층(404-1)을 형성한다. 그리고 돌출된 부위(C4)들 사이의 간격이 결정입자의 크기(b4)가 된다.In the laser irradiation process, the crystals grow and collide with each other in the crystal boundary, and as energy is gradually released to the outside, the crystals in this region solidify and precipitate in a protruding form (C4) to form the silicon layer 404-1. do. The interval between the protruding portions C4 becomes the size b4 of the crystal grains.
도 4D 와 같이, 제 1절연막(406-1)에 충분한 두께로 제 2절연막(408)을 적층하여 2 중의 절연막을 형성한다. 그리고, 제 1절연막(406-1)으로는 핫캐리어가 적게 발생되도록 하는 SiOX또는SiNX또는 SiNOX가 사용되며, 이 후의 공정에서 제 1및 제 2절연막(406-1)(408)은 게이트절연막으로 사용된다.As shown in Fig. 4D, the second insulating film 408 is laminated with a sufficient thickness on the first insulating film 406-1 to form a double insulating film. As the first insulating film 406-1, SiO X, SiN X, or SiNO X is used to generate less hot carriers. In a subsequent process, the first and second insulating films 406-1 and 408 are It is used as a gate insulating film.
이 후, 도면에는 도시되지 않았지만, 제 1 및 제 2절연막(406-1)(408)이 형성된 실리콘층(404-1)에 게이트전극을 형성한다.Thereafter, although not shown in the drawing, a gate electrode is formed on the silicon layer 404-1 on which the first and second insulating films 406-1 and 408 are formed.
따라서, 본 발명의 제 2실시예에서는 실리콘층과 동시에 게이트절연막으로 사용될 절연막을 함께 형성시킬 수 있다.Therefore, in the second embodiment of the present invention, an insulating film to be used as the gate insulating film can be formed together with the silicon layer.
상술한 바와 같이, 본 발명에서는 단일의 또는 이중의 절연막을 이용함으로써 결정화 시에 표면이 매끄럽지 못한 실리콘층을 평탄화할 수 있다.As described above, in the present invention, a single or double insulating film can be used to planarize a silicon layer whose surface is not smooth at the time of crystallization.
그리고, 이 후에 형성될 게이트절연막으로 이용될 절연막을 실리콘층 제조 시에 동시에 형성하여서 그 표면을 평탄화시킴에 따라, 결정화 시에 매끄럽지 못한 실리콘층 표면의 기복에 의해 발생되는 열화특성을 억제할 수 있는 잇점이 있다.By forming an insulating film to be used as a gate insulating film to be formed later, at the same time forming the silicon layer to planarize the surface thereof, deterioration characteristics caused by the undulation of the surface of the silicon layer, which is not smooth during crystallization, can be suppressed. There is an advantage.
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