KR940006697B1 - Manufacturing method of soi mos - Google Patents
Manufacturing method of soi mos Download PDFInfo
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- KR940006697B1 KR940006697B1 KR1019910007108A KR910007108A KR940006697B1 KR 940006697 B1 KR940006697 B1 KR 940006697B1 KR 1019910007108 A KR1019910007108 A KR 1019910007108A KR 910007108 A KR910007108 A KR 910007108A KR 940006697 B1 KR940006697 B1 KR 940006697B1
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- oxide film
- oxidation layer
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- gate
- soi
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- 238000004519 manufacturing process Methods 0.000 title description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 17
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 17
- 239000010703 silicon Substances 0.000 claims abstract description 17
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 22
- 229920005591 polysilicon Polymers 0.000 claims description 20
- 239000000758 substrate Substances 0.000 claims description 7
- 238000005530 etching Methods 0.000 claims description 3
- 238000009826 distribution Methods 0.000 abstract description 12
- 238000010438 heat treatment Methods 0.000 abstract description 11
- 238000000034 method Methods 0.000 abstract description 11
- 239000013078 crystal Substances 0.000 abstract description 7
- 229910052782 aluminium Inorganic materials 0.000 abstract description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 2
- 230000015572 biosynthetic process Effects 0.000 abstract description 2
- 230000003647 oxidation Effects 0.000 abstract 6
- 238000007254 oxidation reaction Methods 0.000 abstract 6
- 239000004411 aluminium Substances 0.000 abstract 1
- 230000008020 evaporation Effects 0.000 abstract 1
- 238000001704 evaporation Methods 0.000 abstract 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000001953 recrystallisation Methods 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 238000010521 absorption reaction Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000006911 nucleation Effects 0.000 description 1
- 238000010899 nucleation Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
제1도는 일반적인 SOI모스 단면구조도.1 is a general cross-sectional view of the SOI Moss.
제2도는 종래 SOI모스 제조방법에 따른 열처리 시료 구조도.Figure 2 is a structure of the heat treatment sample according to the conventional SOI manufacturing method.
제3도의 (a) 내지 (c)는 SOI모스의 열처리 온도분포 특성도.(A) to (c) of FIG. 3 are heat-treatment temperature distribution characteristic diagrams of SOI moss.
제4도의 (a) 내지 (d)는 본 반명에 따른 SOI모스 제조 공정도.(A)-(d) of FIG. 4 is a manufacturing process diagram of SOI moss which concerns on this present name.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
11 : 실리콘기판 12, 15 : 산화막11 silicon substrate 12, 15 oxide film
13 : 마스크패턴 14 : 다결정실리콘층13 mask pattern 14 polysilicon layer
16 : 소오스전극 17 : 게이트전극16 source electrode 17 gate electrode
18 : 드레인전극18: drain electrode
본 발명은 SOI모스 소자의 제조방법에 관한 것으로 특히, SOI구조에서 산화막에 의해 절연되는 양질의 실리콘층을 얻을 수 있도록 한 SOI모스 소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a SOI MOS device, and more particularly, to a method for manufacturing a SOI MOS device in which a high quality silicon layer insulated by an oxide film in an SOI structure can be obtained.
제1도는 일반적인 SOI모스 소자의 단면구조도로서, 이에 도시된 바와 같이 실리콘기판(1)위에 제1산화막(SiO2)(2)이 형성되고, 상기 제1산화막(2)위에 다결정실리콘층(3)이 형성되며, 상기 제 2산화막(4)위에 게이트전극(6) 및 콘택홀을 통해 상기 다결정실리콘층(3)과 접촉되는 소오스(5), 드래인(7) 전극이 형성되어 구성된다.FIG. 1 is a cross-sectional structure diagram of a general SOI MOS device. As shown therein, a first oxide film (SiO 2 ) 2 is formed on a silicon substrate 1, and a polysilicon layer 3 is formed on the first oxide film 2. ) And a source 5 and a drain 7 electrode which are in contact with the polysilicon layer 3 through the gate electrode 6 and the contact hole on the second oxide film 4.
이와 같은 구조의 SOI모스 제조방법은 제2도에 도시된 바와 같이 실리콘기판(1)위의 제1산화막(2)을 증착하고, 그 제l산화막(2)위에 다결정실리콘층(3)을 증착후 페터닝한 다음 상기 다결정실리콘층(3)위에 제 2산화막(4)을 형성한다.In the method of manufacturing SOI moss having such a structure, a first oxide film 2 is deposited on a silicon substrate 1 and a polysilicon layer 3 is deposited on the first oxide film 2, as shown in FIG. After patterning, a second oxide film 4 is formed on the polysilicon layer 3.
이후, 상기의 소자를 열처리함으로써 다결정실리콘층(3)에 존재하는 결정립계의 밀도를 낮추거나 완전히 제거한 뒤 기존모스 소자 제조공정에 따라 능동소자를 구현하게 된다.Subsequently, by heat-treating the device, the density of grain boundaries present in the polysilicon layer 3 is reduced or completely removed, and the active device is implemented according to the existing MoS device manufacturing process.
즉, 실리콘기판(1)인 웨이퍼의 표면에 SiO2을 열적으로 성장시켜 제l산화막층(2)을 형성한 뒤 그 위에다 결정실리콘층(3)을 증착시킨다. 열처리시의 열적식각을 방지하고 수직방향으로의 온도분포를 개선하기 위해 다시 상기 다결정실리콘층(3)위에 캡산화막인 제2산화막(4)을 증착시킨다.That is, SiO 2 is thermally grown on the surface of the wafer, which is the silicon substrate 1, to form the first oxide film layer 2, and then the crystalline silicon layer 3 is deposited thereon. In order to prevent thermal etching during heat treatment and to improve the temperature distribution in the vertical direction, a second oxide film 4, which is a cap oxide film, is deposited on the polysilicon layer 3 again.
상기 다결정실리콘층(3)을 가열하기 위한 열원으로 Ar이나 CO2레이저를 사용하여 시표의 표면에 주사시키면, 다결정실리콘층(3)이 융해점 이상의 온도로 가열되었다가 식으면서 최초에 응고되는 위치를 핵으로하여 실리콘 격자들이 재배열되어 l0μm이상의 결정으로 성장할 수 있게 된다.When the polysilicon layer 3 is scanned on the surface of the target using Ar or a CO 2 laser as a heat source for heating the polysilicon layer 3, the polysilicon layer 3 is heated to a temperature above the melting point and cooled to a position where it is initially solidified. As a nucleus, the silicon lattice is rearranged to grow into crystals larger than l0μm.
이때 핵이 동시 다발적으로 형성되는 경우에는 각각의 핵에서 성장된 결정입정들이 경쟁적으로 성장하여 큰 결정입정을 얻기가 힘들기 때문에 제3도 (a)와 같이 다결정실리콘층(3)의 양 단부는 온도분포가 높고 중앙부는 온도분포가 낮은 것이 열처리에 바람직한 온도분포 곡선이 된다.At this time, when the nuclei are formed at the same time, since both crystal grains grown in each nucleus grow competitively and large crystal grains are hardly obtained, both ends of the polysilicon layer 3 as shown in FIG. The higher temperature distribution and the lower temperature distribution in the center form a preferable temperature distribution curve for heat treatment.
그러나, 종래 방식에서는 Ar레이저를 적용하는 경우 Ar레이저의 파장에 대해서는 다결정실리콘층(3)이 주된 흡수를 하게 되므로 레이저 빔의 강도 분포를 따라 제3도 (b)와 같이 가우시안 분포를 갖는 온도곡선이 된다.However, in the conventional method, when the Ar laser is applied, since the polysilicon layer 3 mainly absorbs the wavelength of the Ar laser, a temperature curve having a Gaussian distribution as shown in FIG. 3 (b) along the intensity distribution of the laser beam is obtained. Becomes
즉, 다결정실리콘층(3)의 중심부가 양 단부보다 Ar레이저를 더많이 흡수하게 되어 양 단부에서 다발적인핵 형성대가 생긴다.That is, the center of the polysilicon layer 3 absorbs more of the Ar laser than both ends, resulting in multiple nucleation zones at both ends.
또한, CO2레이저를 이용하면 다결정실리콘층(3)의 주변부위에 있는 산화막(2)(4)이 주된 흡수를 하므로 제3도 (다)와 같이 다결정실리콘층(3) 양 단부의 온도분포는 재결정화에 유리하나 실리콘층 내부 영역의온도분포가 평탄해지므로 결정이 역시 크게 성장하지 못하게 되는 문제점이 있었다.In addition, when the CO 2 laser is used, the oxide films 2 and 4 at the periphery of the polysilicon layer 3 absorb mainly, and thus the temperature distribution at both ends of the polysilicon layer 3 as shown in FIG. Although it is advantageous for recrystallization, the temperature distribution of the inner region of the silicon layer is flattened, which causes a problem that crystals do not grow significantly.
본 발명은 이와 같은 문제점을 감안하여 CO2레이저를 사용하는 경우 실리콘층 내부영역에 온도분포가 평탄대역이 되는 것을 방지하기 위해서 실리콘층 하부의 산화막층에 단차를 형성시켜 재결정화에 유리한 온도분포를 얻어 양질의 실리콘층을 얻어내기 위한 SOI모스 제조방법을 창안한 것이다.In view of the above problems, the present invention provides a temperature distribution advantageous for recrystallization by forming a step in the oxide layer under the silicon layer in order to prevent the temperature distribution from becoming a flat band inside the silicon layer when using a CO 2 laser. A method for producing SOI moss was obtained to obtain a high quality silicon layer.
본 발명은 실리콘기판위에 제1산화막을 형성하는 과정과, 상기 제l산화막위에 게이트영역을 정의하는 과정과, 상기에서 정의된 게이트영역의 제1산화막을 등방성식각하는 과정과, 상기의 제1산화막위에 다결정실리콘과 제2산화막을 형성하는 과정과, 상기 다결정실리콘을 열처리하는 과정과, 상기 제2산화막위의 게이트영역에 게이트전극을 형성하는 과정으로 이루어지도록 구성한 것으로, 이를 참조한 도면을 참조하여 상세히 설명하면 다음과 같다.The present invention provides a process of forming a first oxide film on a silicon substrate, defining a gate region on the first oxide film, isotropically etching the first oxide film of the gate region defined above, and the first oxide film. And forming a polysilicon and a second oxide film, a heat treatment of the polysilicon, and forming a gate electrode in the gate region on the second oxide film. The explanation is as follows.
제4도 (a) 내지 (d)는 본 발명에 따른 SOI모스 제조공정도로서, 제4도의 (a)에 도시한 바와 같이 실리콘기판(11)표면에 SiO2를 열적으로 성장시켜 제1산화막(12)을 형성한 후 상기 제1산화막(12)위에 감광막(PR)을 입힌 다음 게이트형성영역을 정의하고, 정의된 게이트영역의 감광막(13)을 사진식각(Photolithography)공정을 통해 제거하여 감광막패턴(13)을 형성한다.4A to 4D are process charts for producing SOI moss according to the present invention. As shown in FIG. 4A, SiO 2 is thermally grown on the surface of the silicon substrate 11 to form the first oxide film 12. ), And then, a photoresist film (PR) is coated on the first oxide film (12), and then a gate formation region is defined, and the photoresist film 13 of the defined gate region is removed by a photolithography process. 13).
이후, 제4도의 (b)에 도시한 바와 같이 불산용액을 이용해서 상기 제1산화막(12)을 등방성식각을 수행한다.Thereafter, as shown in FIG. 4B, the first oxide film 12 is isotropically etched using a hydrofluoric acid solution.
제4도의 (c)와 같이 감광막패턴(13)을 제거한 후 그 위에 모스를 이루는 다결정실리콘층(14)과, 캡산화막인 제2산화막(15)을 순차증착시켜 열처리 준비를 완료하고, 이와 같이 준비된 시료에 10w정도 출력을가지는 CO2레이저를 열원으로 열처리하면, 다결정실리콘층(14) 하부의 산화막 두께에 따라 에너지 흡수도에 차이가 생겨 제3도 (a)와 같은 재결정화에 유리한 온도분포가 형성되면서 모스트랜지스터의 체널쪽부터 큰 결정이 성장되어 양질의 다결정실리콘층(14)이 얻어진다.After removing the photosensitive film pattern 13 as shown in (c) of FIG. 4, the polycrystalline silicon layer 14 forming the moss and the second oxide film 15 serving as the cap oxide film are sequentially deposited to complete the heat treatment preparation. When heat-treated a CO 2 laser having a power of about 10w on the prepared sample with a heat source, the energy absorption is different depending on the thickness of the oxide film under the polysilicon layer 14, which is advantageous for the recrystallization as shown in FIG. As large crystals are grown from the channel side of the MOS transistor, the polysilicon layer 14 of good quality is obtained.
이와 같은 열처리가 끝난 뒤 기존 모스 제작공정에 따라 제4도 (d)와 같이 콘택영역을 정의한 후 그 콘택영역의 제2산화막(15)을 제거하여 콘택홀을 형성한 후 알루미늄등의 금속을 증착하여 소오스(16), 게이트(17) 및 드레인(18) 전극을 형성함으로써 SOI모스 소자를 제조한다.After the heat treatment is completed, the contact region is defined as shown in FIG. 4 (d) according to the existing MOS fabrication process, and the second oxide layer 15 of the contact region is removed to form a contact hole, and then deposit a metal such as aluminum. By forming the source 16, gate 17 and drain 18 electrodes, an SOI MOS device is manufactured.
이상에서 설명한 바와 같이 본 발명은 SOI소자가 기존 벌크소자에 대하여 가지는 모든 장점을 그대로 갖는 동시에 게이트를 낮은 위치에 형성시켜 단차에 대한 문제가 해결되며, 채널이 어느정도 곡률을 가지므로 해서 집적화에 용이한 효과가 있다.As described above, the present invention has all the advantages that the SOI device has over the existing bulk device, and at the same time, the gate is formed at a low position to solve the step problem, and the channel has a certain curvature to facilitate integration. It works.
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019910007108A KR940006697B1 (en) | 1991-05-02 | 1991-05-02 | Manufacturing method of soi mos |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019910007108A KR940006697B1 (en) | 1991-05-02 | 1991-05-02 | Manufacturing method of soi mos |
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| Publication Number | Publication Date |
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| KR920022551A KR920022551A (en) | 1992-12-19 |
| KR940006697B1 true KR940006697B1 (en) | 1994-07-25 |
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| KR1019910007108A KR940006697B1 (en) | 1991-05-02 | 1991-05-02 | Manufacturing method of soi mos |
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| KR (1) | KR940006697B1 (en) |
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