KR19990069751A - Semiconductor device manufacturing method - Google Patents
Semiconductor device manufacturing method Download PDFInfo
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- KR19990069751A KR19990069751A KR1019980004196A KR19980004196A KR19990069751A KR 19990069751 A KR19990069751 A KR 19990069751A KR 1019980004196 A KR1019980004196 A KR 1019980004196A KR 19980004196 A KR19980004196 A KR 19980004196A KR 19990069751 A KR19990069751 A KR 19990069751A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 18
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 16
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 45
- 229920005591 polysilicon Polymers 0.000 claims abstract description 45
- 239000012535 impurity Substances 0.000 claims abstract description 37
- 239000000758 substrate Substances 0.000 claims abstract description 25
- 238000010438 heat treatment Methods 0.000 claims abstract description 15
- 238000000151 deposition Methods 0.000 claims abstract description 13
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 11
- 239000010703 silicon Substances 0.000 claims abstract description 11
- 230000008021 deposition Effects 0.000 claims abstract description 4
- 238000000034 method Methods 0.000 claims description 24
- 230000015572 biosynthetic process Effects 0.000 claims 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 9
- 238000009792 diffusion process Methods 0.000 abstract description 6
- 230000006378 damage Effects 0.000 abstract description 2
- 230000008030 elimination Effects 0.000 abstract 1
- 238000003379 elimination reaction Methods 0.000 abstract 1
- 238000002955 isolation Methods 0.000 description 8
- 229920002120 photoresistant polymer Polymers 0.000 description 8
- 229910021417 amorphous silicon Inorganic materials 0.000 description 3
- 238000000059 patterning Methods 0.000 description 3
- 230000002542 deteriorative effect Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 230000006911 nucleation Effects 0.000 description 2
- 238000010899 nucleation Methods 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
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- Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- General Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Chemical & Material Sciences (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
본 발명은 불순물확산에 의한 게이트절연막의 파괴를 방지하고, 게이트전극내 실리콘의 그레인 사이즈를 미세하게 조절하여 소자의 신뢰성을 향상시키기 위한 반도체소자 제조방법을 제공하기 위한 것으로서, 기판에 N웰 및 P웰을 갖는 CMOS소자에 있어서, 상기 기판상에 게이트절연막을 형성하는 공정과, 상기 게이트절연막상에 일정간격을 갖는 복수개의 씨드를 형성한 후, 열처리하는 공정과, 상기 씨드를 포함한 기판상에 폴리실리콘을 증착한 후 열처리하여 상기 씨드를 중심으로 폴리실리콘내 실리콘의 그레인을 성장시키는 공정과, 상기 폴리실리콘 증착 및 열처리를 반복수행하여 실리콘의 그레인을 서로 엇갈려 적층시키는 공정과, 상기 그레인이 서로 엇갈려 적층된 폴리실리콘을 선택적으로 제거하여 앤모스 및 피모스 트랜지스터용 게이트전극들을 형성하는 공정과, 상기 각각의 게이트전극 양측에 해당 도전형의 소오스 및 드레인 불순물영역을 형성하는 공정을 포함하여 이루어지는 것을 특징으로 한다.The present invention is to provide a semiconductor device manufacturing method for preventing the destruction of the gate insulating film due to the diffusion of impurities, to improve the reliability of the device by finely adjusting the grain size of silicon in the gate electrode, N well and P A CMOS device having a well, comprising: forming a gate insulating film on the substrate, forming a plurality of seeds having a predetermined interval on the gate insulating film, and then performing heat treatment; Depositing silicon and then heat treatment to grow the grains of silicon in polysilicon around the seed; repeating the polysilicon deposition and heat treatment to alternately stack grains of silicon alternately; and the grains alternately Selective elimination of stacked polysilicon gates for NMOS and PMOS transistors A step of forming the electrode, including a step of forming a source and drain impurity regions of the conductivity type on both sides of the gate electrode, respectively characterized in that formed.
Description
본 발명은 반도체소자에 관한 것으로 특히 씨모스(CMOS)듀얼(DUAL)게이트전극 형성시 게이트전극용 실리콘결정의 그레인 사이즈를 미세하게 조절하여 그레인 바운더리(grain boundary)를 통한 불순물확산을 증대시켜 소자의 특성을 개선시키는데 적당한 반도체소자 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and in particular, to finely control the grain size of a silicon crystal for a gate electrode when forming a CMOS dual gate electrode, thereby increasing diffusion of impurities through grain boundaries. A semiconductor device manufacturing method suitable for improving characteristics.
일반적으로 씨모스 전계효과트랜지스터(CMOS FET)에서는 도 1에 도시한 바와 같이, 기판(11)에 P웰영역(12)과 N웰영역(13)을 형성하고, 소자격리막(14)을 사이에 두고 각각 N도전형의 불순물이 도핑된 폴리실리콘을 사용하여 제 1, 제 2 게이트전극(15,15a)들을 형성하였다.Generally, in the CMOS field effect transistor (CMOS FET), as shown in FIG. 1, the P well region 12 and the N well region 13 are formed in the substrate 11, and the device isolation film 14 is interposed therebetween. The first and second gate electrodes 15 and 15a were formed using polysilicon doped with N conductive impurities, respectively.
그리고, P웰영역(12)상의 게이트전극(15)을 마스크로 N도전형의 불순물을 주입하여 소오스 및 드레인 불순물영역(17)을 형성함으로써 NMOS트랜지스터를 구현한다.An NMOS transistor is formed by implanting an N conductivity type impurity using a gate electrode 15 on the P well region 12 as a mask to form source and drain impurity regions 17.
또한 N웰영역(13)상의 게이트전극(15a)을 마스크로 P도전형의 불순물을 주입하여 소오스 및 드레인 불순물영역(18)을 형성함으로써 PMOS트랜지스터를 구현하였다.In addition, a PMOS transistor is implemented by forming a source and drain impurity region 18 by injecting a P conductive type impurity with the gate electrode 15a on the N well region 13 as a mask.
여기서, 미설명부호 "16"은 게이트절연막이다.Here, reference numeral 16 denotes a gate insulating film.
그러나 이와같은 CMOS트랜지스터의 문턱전압을 조절하기 위해서는 기판(11)에 고농도의 P+불순물을 주입하여야 한다.However, in order to control the threshold voltage of the CMOS transistor, a high concentration of P + impurities must be injected into the substrate 11.
이때, PMOS영역에서는 베리드 채널(buried channel)이 형성되어 펀치스루(punch through) 등의 소자특성의 저하시키는 요인으로 작용한다.At this time, a buried channel is formed in the PMOS region, which acts as a factor of deteriorating device characteristics such as punch through.
이를 극복하기 위해 PMOS와 NMOS에 각각 P도전형과 N도전형의 게이트전극을 형성하였다.To overcome this problem, P-conducting and N-conducting gate electrodes were formed in PMOS and NMOS, respectively.
이하, 종래기술에 따른 반도체소자 제조방법을 첨부된 도면을 참조하여 설명하기로 한다.Hereinafter, a semiconductor device manufacturing method according to the prior art will be described with reference to the accompanying drawings.
도 2a 내지 2d는 종래 반도체소자 제조방법을 설명하기 위한 공정단면도이다.2A through 2D are cross-sectional views illustrating a method of manufacturing a conventional semiconductor device.
도 2a에 도시한 바와 같이, 기판(11)상의 소정영역에 소자격리막(14)을 형성하고, 소자격리막(14)양측의 기판(11)에 각각 P웰영역(12)과 N웰영역(13)을 형성한다.As shown in FIG. 2A, the device isolation film 14 is formed in a predetermined region on the substrate 11, and the P well region 12 and the N well region 13 are formed on the substrate 11 on both sides of the device isolation film 14, respectively. ).
도면에는 도시되지 않았지만 마스크를 이용하여 P웰영역을 형성할 부위의 기판(11)을 노출시킨 후 P도전형의 불순물을 주입하고, 마찬가지로 마스크를 이용하여 N웰영역을 형성할 부위의 기판(11)을 노출시킨 후 N도전형의 불순물을 주입한다.Although not shown in the drawing, the substrate 11 of the portion where the P well region is to be formed using a mask is exposed, and then an impurity of P conductivity is implanted, and the substrate 11 of the portion where the N well region is to be formed using a mask. ), And then N impurities are implanted.
도 2b에 도시한 바와 같이, 기판(11)상에 게이트절연막(16)을 형성한 후, 소자격리막(14)을 포함한 기판(11)전면에 N도전형(또는 P도전형)의 불순물이 도핑된 폴리실리콘층을 형성한 후, P웰영역(12)상에만 소정부분 남도록 패터닝하여 제 1 게이트전극(15)을 형성한다.As shown in FIG. 2B, after the gate insulating film 16 is formed on the substrate 11, an N conductive (or P conductive) impurity is doped on the entire surface of the substrate 11 including the device isolation film 14. After the polysilicon layer is formed, the first gate electrode 15 is formed by patterning the polysilicon layer so that a predetermined portion remains only on the P well region 12.
여기서, 상기 제 1 게이트전극(15)은 NMOS트랜지스터용 게이트전극이다.The first gate electrode 15 is a gate electrode for an NMOS transistor.
상기 제 1 게이트전극(15)을 형성함에 있어서, N도전형의 폴리실리콘층상에 제 1 포토레지스트(도면에 도시되지 않음)를 도포한 후 제 1 게이트전극(15)이 형성될 부위의 제 1 포토레지스트만을 남긴다.In forming the first gate electrode 15, a first photoresist (not shown) is applied on the N-conductive polysilicon layer, and a first portion of the first gate electrode 15 is to be formed. Only the photoresist is left.
상기 제 1 포토레지스트를 마스크로 이용한 식각공정으로 N도전형의 불순물이 도핑된 폴리실리콘층을 제거한다.In the etching process using the first photoresist as a mask, the polysilicon layer doped with N-conductive impurities is removed.
이어, 도 2c에 도시한 바와 같이, 상기 제 1 포토레지스트를 제거하고 기판(11)을 포함한 전면에 P도전형의 불순물이 도핑된 폴리실리콘층을 형성한 후, N웰영역(13)상의 소정부위에만 남도록 패터닝하여 제 2 게이트전극(15a)을 형성한다.Subsequently, as shown in FIG. 2C, after the first photoresist is removed and a polysilicon layer doped with a P conductivity type impurity is formed on the entire surface including the substrate 11, a predetermined portion of the N well region 13 is formed. The second gate electrode 15a is formed by patterning only the portion to remain.
상기 제 1 게이트전극(15)을 형성할 때와 마찬가지로 상기 폴리실리콘층상에 제 2 포토레지스트(도면에 도시되지 않음)를 도포한 후, 상기 제 2 게이트전극(15a)이 형성될 부위의 제 2 포토레지스트만을 남긴다.As in the case of forming the first gate electrode 15, a second photoresist (not shown) is applied on the polysilicon layer, and then a second portion of the portion where the second gate electrode 15a is to be formed. Only the photoresist is left.
상기 제 2 포토레지스트를 마스크로 이용한 식각공정으로 P도전형의 불순물이 도핑된 폴리실리콘층을 제거한다.In the etching process using the second photoresist as a mask, the polysilicon layer doped with P-conductive impurities is removed.
이어, 도 2d에 도시한 바와 같이, 상기 제 2 포토레지스트를 제거하여 PMOS트랜지스터용 제 2 게이트전극(15a)을 형성한 후, 각각 소오스 및 드레인 불순물영역(17,18)을 형성한다.2D, the second photoresist is removed to form the second gate electrode 15a for the PMOS transistor, and then source and drain impurity regions 17 and 18 are formed, respectively.
여기서, 제 1, 제 2 게이트전극(15,15a)에 도핑된 N 및 P도전형의 불순물이 게이트절연막(16)을 통과하여 기판(11)의 채널부근까지 침투되어야 하는데 게이트절연막(16)을 최대한 파괴하지 않도록 해야 한다.Here, the N and P conductive impurities doped in the first and second gate electrodes 15 and 15a should penetrate through the gate insulating film 16 to the vicinity of the channel of the substrate 11. Try not to destroy as much as possible.
게이트절연막(16)을 최대한 파괴하지 않도록 하기 위해서는 두가지 방법이 있다.There are two ways to prevent the gate insulating film 16 from being destroyed as much as possible.
그중 첫 번째 방법은 게이트전극을 형성함에 있어 불순물이 도핑된 폴리실리콘층을 사용하지 않고 불순물이 도핑되지 않은 비정질실리콘을 사용하는 방법이 있다.The first method is to use an amorphous silicon which is not doped with an impurity without using a polysilicon layer doped with an impurity in forming a gate electrode.
즉, 불순물이 도핑되지 않은 비정질실리콘층을 형성한 다음 불순물을 주입하여 열처리에 의해 불순물이 확산되도록 하는 방법이 있다.That is, there is a method of forming an amorphous silicon layer that is not doped with impurities and then injecting impurities to diffuse the impurities by heat treatment.
또다른 방법은 고온에서 폴리실리콘층을 한 번 더 증착하여 폴리실리콘층의 그레인 사이즈를 미세하게 조절하는 방법이다.Another method is to finely control the grain size of the polysilicon layer by depositing the polysilicon layer once more at high temperature.
상기와 같은 방법으로 종래에는 게이트전극의 그레인 사이즈를 조절하고 불순물확산에 따른 게이트절연막의 파괴를 방지하였다.In the same manner as described above, the grain size of the gate electrode is controlled in the related art and the destruction of the gate insulating film due to the diffusion of impurities is prevented.
그러나 상기와 같은 종래 반도체소자 제조방법은 다음과 같은 문제점이 있었다.However, the conventional semiconductor device manufacturing method as described above has the following problems.
게이트전극을 불순물이 도핑되지 않은 비정질실리콘층을 형성한 후, 불순물주입 및 확산을 행할 경우, 열처리에 의해 생성되는 게이트전극내 폴리실리콘의 그레인 사이즈가 상당히 커지게 되어 도펀트 디플리션(dopants depletion)을 해소할 만한 그레인 바운더리 패스(grain boundary path)가 충분히 형성되지 않는 문제점이 있었다.When the impurity implantation and diffusion are performed after the gate electrode is formed of an amorphous silicon layer that is not doped with impurities, the grain size of the polysilicon in the gate electrode generated by the heat treatment becomes considerably large, and dopant depletion is caused. There was a problem that the grain boundary path (grain boundary path) is not sufficiently formed to solve the problem.
그리고 고온에서 폴리실리콘층을 한 번 더 증착하는 경우에는 그레인 사이즈를 미세화하는데 한계가 있었다.In addition, in the case of depositing the polysilicon layer once more at a high temperature, there was a limit in miniaturizing the grain size.
즉, 고온에서 폴리실리콘층을 한 번 더 증착할 경우, 그레인 사이즈의 미세화가 용이하지 않아 불순물확산이 어렵고 또한 그레인 바운더리가 서로 교차되도록 제어되지 않으므로 불순물확산을 위한 최소한의 열처리에도 쉽게 불순물이 기판의 채널부근으로 확산되어 게이트절연막의 특성을 열화시키는 문제점이 있었다.In other words, when the polysilicon layer is deposited at a high temperature once more, the grain size is not easily refined and impurities are difficult to spread, and since grain boundaries are not controlled to cross each other, impurities are easily removed even at the minimum heat treatment for impurity diffusion. Diffusion near the channel has a problem of deteriorating the characteristics of the gate insulating film.
본 발명은 상기한 문제점을 해결하기 위해 안출한 것으로써, 게이트절연막의 특성을 향상시키면서 게이트전극내 폴리실리콘의 그레인 사이즈를 미세하게 조절하여 소자의 특성을 향상시키는데 적당한 반도체소자 제조방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and provides a semiconductor device manufacturing method suitable for improving the characteristics of the device by finely controlling the grain size of polysilicon in the gate electrode while improving the characteristics of the gate insulating film. There is a purpose.
도 1은 일반적인 CMOS소자를 도시한 단면도1 is a cross-sectional view showing a general CMOS device
도 2a 내지 2d는 종래기술에 따른 반도체소자 제조방법을 설명하기 위한 공정단면도2A through 2D are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the related art.
도 3a 내지 3d는 본 발명에 따른 반도체소자 제조방법을 설명하기 위한 공정단면도3A to 3D are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.
도 4a 내지 4e는 본 발명에 따른 게이트전극용 폴리실리콘 형성방법을 설명하기 위한 공정도Figures 4a to 4e is a process chart for explaining the polysilicon forming method for the gate electrode according to the present invention
도면의 주요부분에 대한 부호의 설명Explanation of symbols for main parts of the drawings
11 : 반도체기판 12 : P웰영역11 semiconductor substrate 12 P well region
13 : N웰영역 14 : 소자격리막13: N well region 14: device isolation film
15,15a : 제 1, 제 2 게이트전극 16 : 게이트절연막15, 15a: first and second gate electrodes 16: gate insulating film
17 : NMOS트랜지스터용 소오스 및 드레인 불순물영역17 source and drain impurity region for NMOS transistor
18 : PMOS트랜지스터용 소오스 및 드레인 불순물영역18: Source and drain impurity region for PMOS transistor
41 : 씨드 42,42a : 폴리실리콘41: seed 42,42a: polysilicon
상기의 목적을 달성하기 위한 본 발명의 반도체소자 제조방법은 기판에 N웰 및 P웰을 갖는 CMOS소자에 있어서, 상기 기판상에 게이트절연막을 형성하는 공정과, 상기 게이트절연막상에 일정간격을 갖는 복수개의 씨드를 형성한 후, 열처리하는 공정과, 상기 씨드를 포함한 기판상에 폴리실리콘을 증착한 후 열처리하여 상기 씨드를 중심으로 폴리실리콘내 실리콘의 그레인을 성장시키는 공정과, 상기 폴리실리콘 증착 및 열처리를 반복수행하여 실리콘의 그레인을 서로 엇갈려 적층시키는 공정과, 상기 그레인이 서로 엇갈려 적층된 폴리실리콘을 선택적으로 제거하여 앤모스 및 피모스 트랜지스터용 게이트전극들을 형성하는 공정과, 상기 각각의 게이트전극 양측에 해당 도전형의 소오스 및 드레인 불순물영역을 형성하는 공정을 포함하여 이루어지는 것을 특징으로 한다.A semiconductor device manufacturing method of the present invention for achieving the above object is a CMOS device having an N well and a P well on a substrate, the process of forming a gate insulating film on the substrate, and having a predetermined interval on the gate insulating film Forming a plurality of seeds, and then heat-treating, depositing polysilicon on the substrate including the seeds, and then heat-treating them to grow grains of silicon in polysilicon around the seeds, and depositing the polysilicon and Repeatedly performing heat treatment to alternately stack grains of silicon, and selectively removing polysilicon stacked between the grains to form gate electrodes for NMOS and PMOS transistors, and the respective gate electrodes. Forming a source and drain impurity region of a corresponding conductivity type on both sides; It is characterized by.
이하, 본 발명의 반도체소자 제조방법을 첨부된 도면을 참조하여 설명하기로 한다.Hereinafter, a method of manufacturing a semiconductor device of the present invention will be described with reference to the accompanying drawings.
먼저, 본 발명은 게이트전극용 폴리실리콘층을 형성하기 이전에 게이트절연막상에 초기 씨드를 형성하고 이후에 폴리실리콘층을 증착하는 과정에서 상기 씨드를 중심으로 그레인 성장시킨다.First, the present invention forms grains on the seed in the process of forming an initial seed on the gate insulating film before forming the polysilicon layer for the gate electrode and then depositing the polysilicon layer.
소오스가스를 사용하지 않고 열처리를 수행하고 다시 폴리실리콘층을 증착하여 불안정한 그레인 바운더리 경계부위에서부터 그레인을 성장시키는 방법이다.It is a method of growing grain from an unstable grain boundary boundary by performing heat treatment without using source gas and depositing a polysilicon layer again.
도 3a 내지 3d는 본 발명에 따른 반도체소자 제조방법을 설명하기 위한 공정단면도이다.3A through 3D are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.
도 3a에 도시한 바와 같이, 기판(11)상의 소정영역에 소자격리막(14)을 형성하고, 소자격리막(14)양측의 기판(11)에 각각 P웰영역(12)과 N웰영역(13)을 형성한다.As shown in FIG. 3A, the device isolation film 14 is formed in a predetermined region on the substrate 11, and the P well region 12 and the N well region 13 are formed on the substrate 11 on both sides of the device isolation film 14, respectively. ).
도면에는 도시되지 않았지만 마스크를 이용하여 P웰영역을 형성할 부위의 기판(11)을 노출시킨 후 P도전형의 불순물을 주입하고, 마찬가지로 마스크를 이용하여 N웰영역을 형성할 부위의 기판(11)을 노출시킨 후 N도전형의 불순물을 주입한다.Although not shown in the drawing, the substrate 11 of the portion where the P well region is to be formed using a mask is exposed, and then an impurity of P conductivity is implanted, and the substrate 11 of the portion where the N well region is to be formed using a mask. ), And then N impurities are implanted.
도 3b에 도시한 바와 같이, 기판(11)상에 게이트절연막(16)을 형성한 후, 소자격리막(14)을 포함한 기판(11)전면에 N도전형(또는 P도전형)의 불순물이 도핑된 폴리실리콘층을 형성한 후, P웰영역(12)상에만 소정부분 남도록 패터닝하여 제 1 게이트전극(15)을 형성한다.As shown in FIG. 3B, after the gate insulating film 16 is formed on the substrate 11, an N conductive (or P conductive) impurity is doped on the entire surface of the substrate 11 including the device isolation film 14. After the polysilicon layer is formed, the first gate electrode 15 is formed by patterning the polysilicon layer so that a predetermined portion remains only on the P well region 12.
이때, 제 1 게이트전극(15)용 폴리실리콘 형성공정을 보다 상세히 설명하면 다음과 같다.In this case, the polysilicon forming process for the first gate electrode 15 will be described in detail as follows.
도 4a 내지 4e는 본 발명에 따른 제 1 게이트전극 형성공정을 설명하기 위한 공정도이다.4A to 4E are process charts for explaining a first gate electrode forming process according to the present invention.
도 4a에 도시한 바와 같이, 기판(11)상에 형성된 게이트절연막(16)상에 간격을 조절하여 실리콘 씨드(41)을 형성한다.As shown in FIG. 4A, the silicon seed 41 is formed by adjusting a gap on the gate insulating film 16 formed on the substrate 11.
씨드(41)형성은 온도가 600∼700℃, 압력이 10-4Torr 조건에서 50∼150초동안 SiH4또는 Si2H6의 소오스가스를 플로잉(flowing)한다.The seed 41 is formed by flowing a source gas of SiH 4 or Si 2 H 6 for 50 to 150 seconds at a temperature of 600 to 700 ° C. and a pressure of 10 −4 Torr.
이후, 1차열처리공정을 진행하는데 온도 및 압력조건은 동일하게 하고 단지 소오스가스 대신에 N2가스를 플로잉(flowing)한다.Thereafter, the first heat treatment process is performed, and the temperature and pressure conditions are the same, and only N 2 gas is flowing instead of the source gas.
이어, 도 4b에 도시한 바와 같이, 1차적으로 폴리실리콘(42)을 증착하여 상기 게이트절연막(16)상에 형성된 씨드(41)들을 중심으로 그레인 성장시킨다.Subsequently, as shown in FIG. 4B, polysilicon 42 is first deposited to grain grow around the seeds 41 formed on the gate insulating layer 16.
이때 온도가 600∼700℃, 압력이 10-4Torr 조건에서 SiH4또는 Si2H6의 소오스가스를 플로잉(flowing)한다.At this time, a source gas of SiH 4 or Si 2 H 6 is flowed under a temperature of 600 to 700 ° C. and a pressure of 10 −4 Torr.
이와같이, 1차적으로 폴리실리콘(42)을 증착하여 그레인을 성장시킨 후, 도 4c에 도시한 바와 같이, 2차 열처리공정을 진행하는데 공정조건은 1차 열처리공정과 동일하게 한다.As described above, after the polysilicon 42 is first deposited to grow grain, as shown in FIG. 4C, the secondary heat treatment process is performed, and the process conditions are the same as the primary heat treatment process.
이때 그레인이 성장하면서 그레인 바운더리 경계부위는 에너지적으로 불안정한 상태가 된다.As the grain grows, the grain boundary boundary becomes energy unstable.
따라서, 그레인 바운더리 경계부위는 또다른 핵생성을 위한 싸이트(site)가 된다.Thus, the grain boundary boundary is another site for nucleation.
이후, 도 4d에 도시한 바와 같이, 2차적으로 폴리실리콘(42a)을 증착하여 핵생성 싸이트로 제공되는 그레인 바운더리 경계부위을 중심으로 그레인 성장시킨다.Thereafter, as illustrated in FIG. 4D, polysilicon 42a is secondarily deposited to grow grain around the grain boundary boundary provided to the nucleation site.
이때 온도가 600∼700℃, 압력이 10-4Torr 조건에서 SiH4또는 Si2H6의 소오스가스를 플로잉(flowing)한다.At this time, a source gas of SiH 4 or Si 2 H 6 is flowed under a temperature of 600 to 700 ° C. and a pressure of 10 −4 Torr.
이상과 같이, 최초 씨드(41)형성 후, 열처리-폴리실리콘(42)증착-열처리-폴리실리콘(42a)증착공정을 반복적으로 수행하여 그레인 바운더리가 서로 엇갈려서 적층되도록 한다.As described above, after the initial seed 41 is formed, the heat treatment-polysilicon 42 deposition-heat treatment-polysilicon 42a deposition process is repeatedly performed so that grain boundaries are alternately stacked.
상기 열처리-폴리실리콘 증착을 반복적으로 수행하였을 경우에 그레인 바운더리를 도 4e에 도시하였다.Grain boundaries are shown in FIG. 4E when the heat treatment-polysilicon deposition is repeatedly performed.
이상과 같이, NMOS트랜지스터의 게이트전극용 폴리실리콘 형성공정을 완료한 다음, 사진식각 공정으로 패터닝하여 도 3b에 도시한 바와 같이, NMOS트랜지스터용 제 1 게이트전극(15)을 형성한다.As described above, the polysilicon forming process for the gate electrode of the NMOS transistor is completed and then patterned by a photolithography process to form the first gate electrode 15 for the NMOS transistor, as shown in FIG. 3B.
이후, 상기 폴리실리콘 형성공정과 동일한 공정을 이용하여 도 3c에 도시한 바와 같이, PMOS트랜지스터용 제 2 게이트전극(15a)을 형성하고 각각 마스크를 이용하여 도 3d에 도시한 바와 같이, NMOS트랜지스터 및 PMOS트랜지스터의 소오스 및 드레인 불순물영역(17,18)을 형성하면 본 발명에 따른 반도체소자 제조공정이 완료된다.Thereafter, as shown in FIG. 3C using the same process as the polysilicon forming process, the second gate electrode 15a for the PMOS transistor is formed, and as shown in FIG. 3D using a mask, respectively, an NMOS transistor and When the source and drain impurity regions 17 and 18 of the PMOS transistor are formed, the semiconductor device manufacturing process according to the present invention is completed.
이상 상술한 바와 같이, 본 발명의 반도체소자 제조방법은 게이트전극용 폴리실리콘내의 그레인 사이즈를 미세하게 조절할 수 있으므로 작은 선폭의 게이트전극내에 많은 실리콘 그레인 바운더리를 형성할 수 있으므로 불순물확산의 증대로 인하여 불순물 공핍을 방지할 수 있다.As described above, the semiconductor device manufacturing method of the present invention can finely control the grain size in the polysilicon for the gate electrode, so that many silicon grain boundaries can be formed in the gate electrode having a small line width. Depletion can be prevented.
또한 그레인 바운더리가 서로 엇갈려 적층되므로 불순물이 채널부근으로 침투하는 통로를 단절시켜 게이트절연막의 리키지 커런트(leakage current)특성과 브랙다운(breakdown)특성을 개선시키는 효과가 있다.In addition, since grain boundaries are stacked on top of each other, a passage through which impurities penetrate near the channel may be interrupted to improve leakage current and breakdown characteristics of the gate insulating layer.
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